Curriculum Vitae

Research and Teaching Activities (2008-2012)April 2012

Olivier Sentieys

Professor, Signal Processing and Computer Engineering (CNU-61)University of Rennes IENSSAT graduate eng. school (Ecole Nationale Superieure des Sciences Appliquees et de Technologie)

Electronics and Computer Engineering DepartementLaboratory: IRISA (UMR CNRS 6074) and INRIA Rennes - Bretagne AtlantiqueAddress: 6 rue de kerampont - 22300 Lannion, sentieys@irisa.frBorn, April 11, 1967 in Paris, married, two children

http://perso.univ-rennes1.fr/olivier.sentieys

http://people.rennes.inria.fr/Olivier.Sentieys

1 Main current responsibilities

• Head, “Computer Architecture” Department of IRISA Lab.

• Head, Cairn project-team, joint team with INRIA, CNRS, University of Rennes 1 and ENS Cachan-Antenne de Bretagne.

– Composed of 14 permanent academic researchers (5 Professors, 7 Ass. Prof., 1 Inria researcher,1 CNRS researcher), 26 PhD students, 3 PostDoc and 6 temporary research engineers.

– Located on two sites: Rennes (Campus de Beaulieu and ENS Cachan) and Lannion (CampusENSSAT)

– http://www.irisa.fr/cairn

– http://www.inria.fr/en/teams/cairn

• Head, ”Embedded Systems” branch of the SISEA (Signal, Images, Embedded Systems and Control)Master of Research (M2R) of Rennes University.

• Member of the board of governors of ENSSAT.

• President of the Scientific Council of ENSSAT.

• Recipient of PES (prime d’excellence scientifique) since 2010.

• Co-leader of the “embedded software roadmap” in the Future and Emerging Technologies (FET) Flag-ship Initiatives “Guardian Angels for a Smarter Life” European Project. National coordination forINRIA.

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2 Education

1999 Habilitation, University of Rennes I, ”Design methods for integrated circuits and embedded systemsin the domain of wireless communications (in french).

1993 PhD, University of Rennes I, Signal Processing and Telecommunications, ”High-level synthesis ofVLSI architectures for signal and image processing: towards the design of heterogeneous multpro-cessors”, supervised by Prof. E. Martin.

1990 DEA (MSc) in Signal Processing and Telecommunications (with highest honor), University ofRennes I.

1990 ”Diplome d’ingenieur”, ENSSAT, Electronics and Computer Engineering Departement.

3 Professional experience

9/2007 - On leave (half time) at INRIA Research Institute.9/2002 - University Professor, University of Rennes I.9/2001 - 8/2002 Full-time researcher at INRIA/IRISA Rennes.9/1994 - 8/2001 Associate Professor, University of Rennes I.

2003 - 2009 Invited Professor several times at Laval University, Canada, total of 3 months.9/2010 Invited Professor, University of Massachusetts, Amherst, USA, 2 weeks.9/2012 Invited Professor, University of Sherbrooke, Canada, 1 month.

4 Main scientific and teaching responsibilities

6/2010 - Head, “Computer Architecture” Department of IRISA Lab.1/2008 - Scientific leader of Cairn project-team at IRISA/INRIA (45 people).5/2002 -12/2007

Scientific co-leader of R2D2 team at IRISA (30 people).

9/1996 - 4/2002 Scientific leader of Signal - Architecture team of the LASTI Lab. (20 people).

2001 - Head, ”Embedded Systems” branch of the SISEA (Signal, Images, Embedded Systemsand Control) Master of Research (M2R) of Rennes University.

9/1999 - 9/2001 Head, electronics engineering departement at ENSSAT.

1996 - Scientific leader of about 25 research contracts and funded collaborations.2002 Co-founder of Aphycare technologies, a company developing embedded sensors for

biomedical applications and elderly person surveillance.

5 Research activities

My research activities are in the two complementary fields of embedded systems and signal processing.Roughly, I work firstly on the definition of new system-on-chip architectures, especially the paradigm ofreconfigurable systems, and their associated CAD tools, and secondly on some aspects of signal processinglike finite arithmetic effects and cooperation in mobile systems. For more information, see the activity reportof the team at http://raweb.inria.fr/rapportsactivite/RA2011/cairn/uid0.html

Recent research themes:

• Dynamically reconfigurable coarse-grain architectures, reconfigurable memory structures, embeddedFPGA, hardware description language [PSD08] [LPS09b] [MCK+09] [CEPS11b] [JPSP10];

• High-level synthesis of specialized virtual components under power and accuracy constraints [NMS09][MSHN12];

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(a) PowWow pro-cessing, radio andenergy harvestingboards

(b) On-Chip Randomness Ex-traction Ochre-V2 Chip Layout

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(c) Power-Gated WSNNode Chip Layout

Figure 1: Hardware chips and platform developed.

• Automatic floating-point to fixed-point conversion, analytical accuracy evaluation of fixed-point sys-tems [CSM+11a] [MRS08] [RMSS12] [PRM+10] [RMSS10];

• Hardware architectures for advanced wireless and MIMO systems [NBVS09] [NMO09] [TRS10];

• High-rate true random number generation, hardware acceleration of statistical test [SSR09a] [SSR09b][STSR09];

• Power consumption estimation and reduction in SoCs [CSLJ08a] [CLS10] [PDS12] [PPS10b] [PPS10c][PDS10b] [PDS10c] [TSD11a] [TSD11];

• Ultra-low-power architectures for wireless sensor networks [PDS09b] [PDS10c] [PDS10b]

• Advanced signal processing for power reduction in wireless sensor networks, cooperative wireless sys-tems [NBS08b] [NBS08a] [ZGBS11] [ABM+11] [NBS11d] [ABM+12] [TBS11b].

Software and Hardware Developed

• An automatic floating point to fixed point conversion flow (for HLS and embedded processors). ID.Fixis an infrastructure for the automatic transformation of software code aiming at the conversion offloating-point data types into a fixed-point representation. http://idfix.gforge.inria.fr.

• Interconnect Explorer is a high-level power and delay estimation tool for on-chip interconnects.

• PowWow (Power Optimized Hardware and Software FrameWork for Wireless Motes) is a hardwareand software platform designed to handle wireless sensor network (WSN) protocols and related appli-cations (see Fig. 1a). Based on our MAC protocol and other innovating features, PowWow results ina very light memory usage and in 15x less power consumption than the equivalent ZigBee standard.http://powwow.gforge.inria.fr.

• Ochre (On-Chip Randomness Extraction) is a set of synthesizable IP models for true- and pseudo-random number generation and hardware accelerated statistical tests [SSR09b] [STSR09]. It includesIP cores of different oscillator-based TRNGs, different PRNGs (linear feedback shift registers, cellularautomata, AES-based) and several statistical tests (FIPS 140-1 and AIS31). This set of IPs has beenused to design Ochre V1 and V2 (see Fig. 1b) chips.

• As a proof of concept of our power-gated hardware task approach [PDS10c] [PDS10b], a chip (see Fig.1c) has been designed and fabricated in a 65nm CMOS from STMicroelectronics. The area is about1mm2 in a QFN52 package.

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Keywords: Embedded System Design, System-on-Chip, Reconfigurable Architectures, Low-Power Inte-grated Circuits and Systems, Finite Arithmetic Effects, Signal Processing for Wireless Communications,Cooperation in Mobile Systems, Wireless Sensor Networks

6 Scientific organization and expertise

• Member of the French National University Council (CNU section 61) from 1999 to 2007.

• Member of the ANR ARPEGE evaluation committee (2010).

• Member of AERES evaluation committee for research laboratories.

• O. Sentieys is a member of the “Allistene” alliance between INRIA, CNRS and CEA, Working Groupon software systems since 2010.

• Expert for Natural Sciences and Engineering Research Council of Canada (NSERC), ANVAR, RegionRhone-Alpes, Region Languedoc and fonds quebecois de la recherche sur la nature et les technologies(FQNRT).

• Expert for ANR and CNRS (blanc, jc, redoc, arpege, cosinus, PEPS).

• Expert for Primes d’Excellence Scientifique (PES) in 2009.

• Chair of the IEEE Circuits and Systems (CAS) French Chapter (2004-).

• Member of the steering committee of the SOC-SIP Expert Group at the CNRS and of the GDRSOC-SIP.

• Member of the Steering Committee of GRETSI.

• Member of IEEE and ACM.

7 Program committees, editorial boards, conference organization

• Editorial board of Journal of Low Power Electronics, American Scientific Publishers, and of ISRNSensor Networks.

• Guest editors of Eurasip Journal of Advances in Signal Processing, special issue on Quantization ofVLSI Digital Signal Processing Systems, 2010.

• Technical Program Committee member of: IEEE/ACM DATE’11–12, IEEE DDECS’08–12, IEEEISQED’08–12, IEEE DDECS’08–12, ACM SBCCI’08–12, AFRICON’11, WUPS’10–11, DCIS’08-10,FTFC’08–12, SympA, Gretsi.

• Track Chair at NEWCAS’11, Publicity Co-Chair of IEEE ISCAS’10, member of the International Ad-visory Committee Co-Chair in IEEE APCCAS 2010, Track Chair at NEWCAS’12 and IEEE VTC’12,and Publicity Co-Chair of IEEE VTC’12.

• Reviewer for the following international journals: IEEE Trans. on Signal Processing, IEEE Trans.on VLSI Systems, Journal of VLSI Signal Processing, IEEE Trans. on Circuits And Systems II, IETComputers & Digital Techniques, IEE Proc. Circuits, Devices & Systems, Transactions on High-Performance Embedded Architectures and Compilers Journal (Transactions on HiPEAC), Signal Pro-cessing (Elsevier), Journal of Real-Time Image Processing, Technique et Science Informatiques (TSI),Traitement du Signal (TS).

• Reviewer for the following international conferences: IEEE/ACM Design Automation Conference(DAC), IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP), IEEE Int.

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Symposium on Circuits and Systems (ISCAS), IEEE Wireless Communications and Networking Con-ference (WCNC’2007), Euromicro Digital Systems Design Symposium, ACM International Confer-ence on Computing Frontiers, IEEE NEWCAS, IEEE Symposium on Industrial Embedded Systems(IES’2006), GRETSI, etc.

Invited Talks and Awards

• A. Pasha has won the ”Best Student Paper Award” at IEEE INMIC’09 for his paper “Toward UltraLow-Power Hardware Specialization of a Wireless Sensor Network Node” with S. Derrien and O.Sentieys.

• Conferences and Workshops: WPMC’11, ISSC’10 (keynote), National Workshop of the GdR SoC-SiP2009.

• Tutorials: WUPS’11.

• Seminars: Univ. of Massachusetts USA, Laval Univ. CA, and 5 in France.

• Summer Schools: FETCH’12, ECOFAC’10, ARCHI’09.

• Tool Demonstrations: ITEA Symposium 2009, DATE’09, DATE’11, WPMC’11.

Summer Schools

• Member of the steering committee of a CNRS spring school for graduate students on embedded systemsarchitectures and associated design tools (ARCHI) (ecole thematique sur les architectures des systemesmateriels enfouis et methodes de conception associees).

• Member of the steering committee of a CNRS spring school for graduate students on low power real-time embedded systems (ECOFAC) (ecole thematique sur la conception faible consommation pour lessystemes embarques temps reel).

• Co-organized ARCHI’2009 spring school in Pleumeur-Bodou, March 30–April 3, 2009. http://www.

irisa.fr/archi09/

• Co-organized ECOFAC’2010 spring school in Plestin les Greves, March 29–April 2, 2010. http:

//ecofac2010.irisa.fr/

8 PhD Supervisions (2006-now)

• Supervision or co-supervision of 25 defended PhD Theses. One is full-time researcher at CNRD,7 are Associate Professors (ENSSAT, INSA Rennes, ENSICaen, IUT de Lannion, Vietnam, Tunisie),4 researchers at CEA, and the others are engineers or Postdocs.

• Supervision or co-supervision of 11 on-going PhD theses.

• Recipient of PEDR since 1998 (renewing in 2002 and 2006).

• Recipient of Prime d’Excellence Scientifique (PES) since 2010.

On-going PhDs

• Cecile Beaumin-Palud, Reconfigurable Architecture for High-Performance Video Transcoding, Oct.2008, co-supervised with E. Casseau.

• Karthick Parashar, System-level Approach for Implementation and Optimization of Signal ProcessingApplications into Fixed-Point Architectures, Oct. 2008, co-supervised with D. Menard.

• Michel Theriault, Transmit Beam-forming for Distributed Wireless Access with Centralized SignalProcessing, Nov. 2008, co-supervised with S. Roy (U. Laval, CA).

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• Mahtab Alam, Power Aware Signal Processing for Reconfigurable Radios in the context of WirelessSensor Networks, Nov. 2009, co-supervised with D. Menard and O. Berder.

• Vivek Tovinakere Dwarakanath, Ultra-Low Power Reconfigurable Controllers for Wireless Sensor Net-works, Oct. 2009.

• Vinh Tran, Energy Optimisation of Cooperative Transmissions for Wireless Sensor Networks, Oct.2009, co-supervised with O. Berder.

• Matthieu Texier, Low-Power Embedded Multi-Core Architectures for Mobile Systems, Oct. 2009,co-supervised with R. David (CEA).

• Jean-Charles Naud, Source-to-Source Transformations for Fixed-Point, Nov. 2009, co-supervised withD. Menard.

• Amine Didioui, RF Transmission System for Self-Powered Wireless Sensor Networks, Oct. 2010, co-supervised with C. Bernier (CEA LETI).

• Pramod Udupa, Sampling, synchronising, digital processing and FPGA implementation of 100Gbpsoptical OFDM signals, Jan. 2011, co-supervised with O. Berder and L. Bramerie (Foton).

• Trong Nhan Le, Global Power Management System for Self-Powered Autonomous Wireless SensorNodes, Jan. 2011, co-supervised with O. Berder and C. Belleudy (U. Nice).

• Ganda-Stephane Ouedraogo, Automatic Synthesis of Hardware Accelerators from High-Level Specifi-cations of Physical Layer Waveform for Flexible Radio, Oct. 2011, co-supervised with M. Gautier.

Defended PhDs

• Hai Nam Nguyen, Dynamic Precision Scaling for Energy Reduction in Embedded Systems, Dec. 2011,co-supervised with D. Menard. Now with Open Web Solutions, Paris.

• Adeel Pasha, System-Level Synthesis of Ultra Low-Power Wireless Sensor Network Node Controllers:A Complete Design-Flow, Dec. 2010, co-supervised with S. Derrien. Now a researcher at LahoreUniversity of Management Sciences, Pakistan.

• Erwan Grace, Memory-Oriented Reconfigurable Embedded Architecture, oct. 2010, co-supervised withD. Chillet and R. David (CEA). Now with Alcatel-Lucent.

• Tuan Duc Nguyen, Cooperative MIMO Strategies for Energy Constrained Wireless Sensor Networks,may 2009, co-supervised with O. Berder. Now Assistant Professor at International University - Viet-nam National Univ. - Hochiminh City.

• Renaud Santoro, High-Rate True Random Number Generators with Guaranteed Quality, dec. 2009,co-supervised with S. Roy (Laval Univ., CA), cotutelle. Now with Alcatel-Lucent.

• Antoine Courtay, Power Consumption of On-Chip Interconnections: High-Level Estimation and Architecture-Level Optimizations, nov. 2008, co-supervised with J. Laurent (LESTER, Lorient). Now a PostDocat Univ. Nice.

• Taofik Saıdi, Architectures for MIMO communications with parallel and adaptive sampling, 2008. Nowwith Amesys.

• Julien Lallet, Mozaıc: a Generic Platform for Modeling and Design of Dynamically ReconfigurableArchitectures, nov. 2008, co-supervised with S. Pillement. Now with Alcatel-Lucent after a PostDocat the Heinz Nixdorf Institut of Univ. Paderborn.

• Imene Benkermi, Real-Time Operating System for heterogeneous parallel reconfigurable architectures,2007. Now with Valeo.

• Nicolas Herve, Design Methodology for Fixed-Point Reconfigurable Architectures, 2007. Now a Post-Doc at University of Sao Paulo, Brasil.

• Mickael Cartron, Energy Optimization of Wireless Sensor Networks, dec. 2006. Now Researcher atCEA List Saclay.

• Romuald Rocher, Accuracy and Range Evaluation of Fixed-Point Systems, dec. 2006, co-supervisedwith D. Menard. Now Assistant Professor at Univ. Rennes 1 (IUT de Lannion).

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9 Research Collaborations and Contracts (2008-2012)

9.1 International Collaborations

International collaborations with: EPFL, Switzerland; UC Louvain-La-Neuve, Belgium; IMEC, Belgium;ENIT Tunisia; Quebec University at Trois-Rivieres, Canada; Laval University, Quebec, Canada; Erlangen-Nuremberg University, Germany; Dresden University of Technology, Germany; USA, University of Mas-sachusetts, Amherst, USA.

9.2 Industrial Collaborations

Collaborations with large companies like STmicroelectronics (Grenoble), Thomson (Rennes), Thales (Paris),Alcatel-Lucent (Lannion), France-Telecom Orange Labs (Lannion) or SMEs like Geensys (Nantes), Aphy-care Technologies (Lannion), SmartQuantum (Lannion), Sensaris (Grenoble), Envivio (Rennes), Ekinops(Lannion).

9.3 Scientific Responsibilities of Research Contracts and Platforms

• European Project Future and Emerging Technologies (FET) Flagship Initiatives “Guardian An-gels for a Smarter Life”, Zero-Power Systems: these small devices, products of nanotechnology, will com-bine low-power electronics with new sources of energy, taken form their immediate environment (sun, bodymovements, changes in temperature). Collaboration with about fifty academic and industrial partners suchas EPFL, ETHZ, IMEC, KUL, UCL, CNRS, CEA LETI, VTT, TUM, Fraunhofer, etc. 2013-2023. http:

//www.ga-project.eu

• European Project FP7 FLEXTILES, Self Adaptive Heterogeneous Manycore Based on Flexible Tiles.Collaboration with Thales (FR), UR1 (FR), KIT (GE), TU/e (NL), CSEM (SW), CEA LETI (FR), Sundance(UK). 2011-2014. 380ke.

• European Project FP7 ALMA, Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb. Collaboration with KIT (GE), UR1 (FR), Recore Systems (NL), Univ. of Peloponnese(GR), TEI-MES (GR), Intracom SA (GR), Fraunhofer (GE). 2011-2014. 400ke.

• Coordination of the French ANR Project DEFIS, Design of Fixed-Point Systems. Collaboration withINRIA/CAIRN, LIP6, LIRMM, CEA LIST, Thales, Inpixal. 2011-2015. 252ke.

• French ANR Project FAON, Frequency based Access Optical Network. Collaboration with Orange Labs,IRISA, FOTON, LAB-STICC, CEA LETI. 2011-2014. 180ke.

• French FUI Project 100GFlex, Multiband optical OFDM at 100 Gbits/s. Collaboration with Mitsubishi-Electric R&D Center Europe, IRISA, Institut Telecom, Ekinops, Orange Labs, Yenista Optics, Foton. 2010-2013.350ke.

• French ANR Project GRECO, GREen wireless Communicating Objects. Collaboration with Thales, UR1,CEA List, CEA Leti, Im2nP, LEAT, Insight-SiP. 2010-2013. 255ke.

• PERECAP, Research and Experimental Platform on Autonomous Wireless Sensor Networks. Collaborationseveral teams at the regional level, 2008-2013. Responsibility and scientific animation of the platform. 650ke.

• MOB-ITS, Mobile and Interactive Information Access for Intelligent Transportation Systems Applications.Collaboration with two other teams from IRISA, 2008-2013. Responsibility and scientific animation of theplatform. 470ke (1.1 Me for the whole platform and infrastructures).

• Coordination of the S2S4HLS Project from the Nano2012 Program, Source-to-Source transformationsfor High-Level Synthesis. Collaboration with STMicroelectronics (Grenoble), 2008-2012. 689ke.

• French ANR Project Open-People, Open Power and Energy Optimization PLatform and Estimator. Col-laboration with LabSticc (Lorient), INRIA Trio (Nancy), INRIA Dart (Lille/Valenciennes), Leat (Nice), Thales(Colombes), InPixal (Rennes), 2009-2011. 204ke.

• Transmedi@ Project, funded by Images and Networks competitiveness cluster, Reconfigurable Video Transcod-ing. Collaboration with Alcatel, Envivio, Telecom Bretagne, IETR/Supelec, 2008-2010. 269ke.

• ITEA2 European Project Geodes, Global Energy Optimisation for Distributed Embedded Systems. Collab-oration with Thales (FR, IT, NL), Sensaris (FR), CNRS (LEAT and IRISA) (FR), CETMEF/MARTEC (FR),Infineon (AU), Thomson (FR), TUV (AU), UAQ (IT), Phillips (NL), Organo (AU), TI-WMC (NL), 2008-2011.316ke.

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• French ANR Project Cifaer, Flexible Intra-Vehicule Communications and Embedded Reconfigurable Archi-tectures. Collaboration with IETR Rennes, Ireena Nantes, Atmel, Geensys, 2008-2011. 146ke.

• Spring Project, funded by Images and Networks competitiveness cluster, Shelf Proof Random IntegratedNumber Generator. Collaboration with SmartQuantum, 2008-2009. 99ke.

• Coordination of the Regional Project CAPTIV, Consommation et strAtegies cooPeratives pour les Trans-missions entre Infrastructures et Vehicules. Collaboration with IETR, Telecom Bretagne, 2006-2008. 162ke.

9.4 Participation to Research Contracts

• French ANR Project OCELOT, Oscilloscope de Constellations a base d?Echantillonnage Lineaire toutOpTique. Collaboration with APEX Tech., IRISA, FOTON, Telecom ParisTech. 2011-2014. 150ke.

• French ANR Project ROMA, Reconfigurable Operators for Multimedia Applications. Collaboration withCEA LIST, LIRMM, Thomson R&D. 2007-2010. 174ke.

• French ANR Project SVP : SurVeiller et Prevenir. Collaboration with CEA LETI, ANACT, Aphycare,INRIA, UPMC/LIP6, LPBEM, Thales, 2006-2008. 210ke.

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Main Publications (2008-2012)

Edition of Special Issues of Journals

[CSM+11b] Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. Lopez, and David Novo. Editors of thespecial issue on Quantization of VLSI Digital Signal Processing Systems. EURASIP Journal on Advances inSignal Processing, 2011.

International Journals

[CSLJ08a] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. High-level Interconnect Delay and Power Estimation.Journal of Low Power Electronics (JOLPE), 4(1):21–33, 2008.

[MRS08] D. Menard, R. Rocher, and O. Sentieys. Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10):3197–3208, November2008.

[MSRS08] D. Menard, R. Serizel, R. Rocher, and O. Sentieys. Accuracy Constraint Determination in Fixed-PointSystem Design. EURASIP Journal on Embedded Systems, 2008:12, 2008.

[PSD08] S. Pillement, O. Sentieys, and R. David. DART: A Functional-Level Reconfigurable Architecture for HighEnergy Efficiency. EURASIP Journal on Embedded Systems (JES), pages 1–13, 2008. Article ID 562326, 13 pages.

[LPS09b] Julien Lallet, Sebastien Pillement, and Olivier Sentieys. Efficient and Flexible Dynamic Reconfiguration forMulti-Context Architectures. Journal of Integrated Circuits and Systems, 4(1):36–44, 2009.

[CLS10] A. Courtay, J. Laurent, and O. Sentieys. Spatial switching data coding technique analysis and improvementsfor interconnect power consumption optimization. Journal of Low Power Electronics (JOLPE), 6(1):32–43, April2010.

[RMSS10] R. Rocher, D. Menard, O. Sentieys, and P. Scalart. Accuracy evaluation of fixed-point based lms algorithm.Digital Signal Processing, 20(3):640–652, May 2010.

[PPS10a] S. Piestrak, S. Pillement, and O. Sentieys. Comments on ’a low-power dependable berger code for fullyasymmetric communication’. IEEE Communications Letters, 14(8):761–763, August 2010.

[PPS10b] S. Piestrak, S. Pillement, and O. Sentieys. On designing efficient codecs for bus-invert berger code for fullyasymmetric communication. IEEE Transactions on Circuits and Systems II, 57(10):777 –781, October 2010.

[PPS10c] S. Pillement, JM. Philippe, and O. Sentieys. Spatio-temporal coding to improve speed and noise toleranceof on-chip interconnect. MicroElectronics Journal, 41(8):480 – 486, 2010.

[CSM+11a] Gabriel Caffarena, Olivier Sentieys, Daniel Menard, Juan A. Lopez, and David Novo. Editorial: Quanti-zation of VLSI digital signal processing systems. EURASIP Journal on Advances in Signal Processing, 2011:1–2,2011.

[ABM+11] Mahtab Alam, Olivier Berder, Daniel Menard, Thomas Anger, and Olivier Sentieys. A hybrid model foraccurate energy analysis of WSN nodes. EURASIP Journal on Embedded Systems, 2011(Article ID 307079):1–16,January 2011.

[CEPS11b] Daniel Chillet, Antoine Eiche, Sebastien Pillement, and Olivier Sentieys. Real-time scheduling on hetero-geneous system-on-chip architectures using an optimised artificial neural network. Journal of Systems Architecture- Embedded Systems Design, 57(4):340–353, April 2011.

[NBS11d] Tuan-Duc Nguyen, Olivier Berder, and Olivier Sentieys. Energy-efficient cooperative techniques forinfrastructure-to-vehicle communications. IEEE Transactions on Intelligent Transportation Systems, 12(3):659–668, September 2011.

[TSD11a] Vivek D. Tovinakere, Olivier Sentieys, and Steven Derrien. A polynomial based approach to wakeup timeand energy estimation in power-gated logic clusters. Journal of Low Power Electronics (JOLPE), 7(4):482–489,December 2011.

[ZGBS11] R. Zhang, J.M. Gorce, O. Berder, and O. Sentieys. Lower bound of energy-latency trade-off of opportunisticrouting in multi-hop networks. EURASIP Journal on Wireless Communciations and Networking, 2011 (Article ID265083):17, 2011.

[ABM+12] Mahtab Alam, Olivier Berder, Daniel Menard, and Olivier Sentieys. TAD-MAC: traffic-aware dynamicMAC protocol for wireless body area sensor networks. IEEE Journal on Emerging and Selected Topics in Circuitsand Systems, 2(1):1–11, March 2012.

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[PDS12] Adeel Pasha, Steven Derrien, and Olivier Sentieys. System-level synthesis for wireless sensor node controllers:A complete design flow. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(1):2.1–2.24, January 2012.

[RMSS12] Romuald Rocher, Daniel Menard, Olivier Sentieys, and Pascal Scalart. Analytical approach for numericalaccuracy estimation of fixed-point systems with smooth operations. IEEE Transactions on Circuits and SystemsI, To Appear, 2012.

[MSHN12] Daniel Menard, Olivier Sentieys, Nicolas Herve and Hai-Nam Nguyen. High-Level Synthesis under fixed-point accuracy constraint. Journal of Electrical and Computer Engineering (JECE), To Appear, 2012.

[ZBGS12] Ruifeng Zhang, Olivier Berder, Jean-Marie Gorce and Olivier Sentieys. Energy-Delay Tradeoff in WirelessMultihop Networks with Unreliable Links. Ad Hoc Networks Journal, To Appear, 2012.

Book Chapters

[CPS10] D. Chillet, S. Pillement, and O. Sentieys. Algorithm-Architecture Matching for Signal and Image Processing,chapter RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip, pages 117–144. Springer, 2010.

[ST12] O. Sentieys and A. Tisserand. Systemes embarques, chapter Circuits FPGA. Techniques de l’Ingenieur, 2012.

[SB12] O. Sentieys and O. Berder. Micro et nanosystemes autonomes en energie, chapter Optimisation energetiquedes reseaux de capteurs. Hermes-Lavoisier, 2012.

[SB12] O. Sentieys and O. Berder. Energy Autonomous Micro and Nanosystems, chapter Optimizing Energy Efficiencyof Sensor Networks. Wiley, 2012.

Patents

[CSLJ09] Antoine Courtay, Olivier Sentieys, Johann Laurent, and Nathalie Julien. Process and device for encoding,and associated electronic system and storage medium, Feb. 2009. US Patent, Reference US 2011/0019766 A1.

International Conferences and Workshops

[HMS08] T. Hilaire, D. Menard, and O. Sentieys. Bit accurate roundoff noise analysis of fixed-point linear controllers.In IEEE International Conference on Computer-Aided Control Systems (CACSD’08), pages 607–612, September2008.

[LPS08] J. Lallet, S. Pillement, and O. Sentieys. Efficient dynamic reconfiguration for multi-context embedded fpga.In Proceedings of the 21st annual symposium on Integrated circuits and system design, SBCCI’08, pages 210–215,New York, NY, USA, 2008. ACM.

[NBS08a] T.D. Nguyen, O. Berder, and O. Sentieys. Efficient space time combination technique for unsynchronizedcooperative miso transmission. In IEEE 67th Vehicular Technology Conference (VTC Spring 2008), pages 629–633,Marina Bay, Singapore, May 2008.

[NBS08b] T.D. Nguyen, O. Berder and O. Sentieys. Impact of transmission synchronization error and cooperativereception techniques on the performance of cooperative MIMO systems. In Proceedings of IEEE InternationalConference on Communications (ICC’08), pages 4601–4605, Beijing, China, May 2008.

[CLSJ09a] A. Courtay, J. Laurent, O. Sentieys, and N. Julien. Interconnect explorer: A high-level power estimationtool for on-chip interconnects. In Proc. of the IEEE/ACM Design Automation Conference (DAC), User Track,San Francisco, USA, 2009.

[CLSJ09] Antoine Courtay, Johann Laurent, Olivier Sentieys, and Nathalie Julien. Novel cross-transition eliminationtechnique improving delay and power consumption for on-chip buses. In Lars Svensson and Jose Monteiro, editors,Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, volume 5349 ofLecture Notes in Computer Science, pages 359–368. Springer Berlin / Heidelberg, 2009.

[LPS09c] Julien Lallet, Sebastien Pillement, and Olivier Sentieys. xMAML: a Modeling Language for DynamicallyReconfigurable Architectures. In Proc. of the 12th Euromicro Conference on Digital System Design: Architectures,Methods and Tools (DSD), pages 680 – 687, Patras, Greece, August 2009.

[NBVS09] Q.-T. Ngo, O. Berder, B. Vrigneau, and O. Sentieys. Minimum distance based precoder for mimo-ofdmsystems using a 16-qam modulation. In Proc. of the IEEE International Conference on Communications (ICC),pages 1–5, Dresden, Germany, June 2009.

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[NMO09] H.N. Nguyen, D. Menard, and O.Sentieys. Design of Optimized Fixed-point WCDMA Receiver. In Proc.of the XVII European Signal and Image Processing Conference (EUSIPCO’09), Glascow, Scotland, August 2009.EURASIP.

[NMS09] H.-N. Nguyen, D. Menard, and O. Sentieys. Dynamic precision scaling for low power WCDMA receiver. InProc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, pages 205–208, Taipei, Taiwan,May 2009.

[PDS09a] M. A. Pasha, S. Derrien, and O. Sentieys. Toward Ultra Low-Power Hardware Specialization of a WirelessSensor Network Node. In Proc. of the 13th IEEE International Multitopic Conference, INMIC 2009, Islamabad,Pakistan, December 2009.

[PDS09b] M. A. Pasha, S. Derrien, and O. Sentieys. Ultra low-power fsm for control oriented applications. In Proc.of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, pages 1577 – 1580, Taipei, Taiwan,May 2009.

[MCK+09] Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stephane Chevobbe, StephaneGuyetant, and Raphael David. Reconfigurable operator based multimedia embedded processor. In Jurgen Becker,Roger Woods, Peter Athanas, and Fearghal Morgan, editors, Reconfigurable Computing: Architectures, Tools andApplications, volume 5453 of Lecture Notes in Computer Science, pages 39–49. Springer Berlin / Heidelberg, 2009.

[SSR09a] R. Santoro, O. Sentieys, and S. Roy. On-line monitoring of random number generators for embedded security.In Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, pages 3050 – 3053, Taipei,Taiwan, May 2009.

[SSR09b] R. Santoro, O. Sentieys, and S. Roy. On-the-Fly Evaluation of FPGA-Based True Random Number Gen-erator. In Proc. of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI’09, pages 55–60, Tampa,Florida, USA, May 2009.

[STSR09] R. Santoro, A. Tisserand, O. Sentieys, and S. Roy. Arithmetic operators for on-the-fly evaluation of TRNGs.In Proc. of the Advanced Signal Processing Algorithms, Architectures and Implementations XVIII, volume 7444,pages 1–12, San Diego, CA, USA, August 2009. SPIE.

[JPSP10] Syed Jafri, Stanislaw Piestrak, Olivier Sentieys, and Sebastien Pillement. Design of a fault-tolerant coarse-grained reconfigurable architecture: A case study. In Proc. of the 11th IEEE International Symposium on QualityElectronic Design (ISQED), pages 845–852, San Diego, CA, USA, March 2010. IEEE.

[PRMS10a] K. Parashar, R. Rocher, D. Menard, and O. Sentieys. Analytical approach for analyzing quantizationnoise effects on decision operators. In Proc. of the 35th IEEE International Conference on Acoustics, Speech, andSignal Processing (ICASSP), pages 1554 – 1557, Dallas, Texas, USA, March 2010.

[PRMS10a] K. Parashar, R. Rocher, D. Menard, and O. Sentieys. A hierarchical methodology for word-length opti-mization of signal processing systems. In Proc. of the 23rd International Conference on VLSI Design, VLSID’10,pages 318–323, Bangalore, India, January 2010.

[PDS10c] M. A. Pasha, S. Derrien, and O. Sentieys. A complete design-flow for the generation of ultra low-powerwsn node architectures based on micro-tasking. In Proc. of the 47th IEEE/ACM Design Automation Conference(DAC), pages 693 – 698, Anaheim, CA, USA, June 2010.

[TRS10] M. Theriault, S. Roy, and O. Sentieys. Transmitter architecture for the evaluation of beamforming schemesin the ieee 802.11n standard. In Proc. of the 11th annual IEEE Wireless and Microwave Technology (WAMI)Conference, pages 1–4, Melbourne, FL, USA, April 2010.

[PDS10b] A. Pasha, S. Derrien, and O. Sentieys. System-Level Synthesis for Ultra Low-Power Wireless Sensor Nodes.In Proc. of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD),pages 493 – 500, Lille, France, September 2010.

[PMRS10] Karthick Parashar, Daniel Menard, Romuald Rocher, and Olivier Sentieys. Shaping Probability DensityFunction of Quantization Noise in Fixed Point Systems. In Proc. of the 44th Annual Asilomar Conference onSignals, Systems, and Computers, Monterey, CA, November 2010.

[PRM+10] K. Parashar, R. Rocher, D. Menard, O. Sentieys, D. Novo, and F. Catthoor. Fast performance evaluation offixed-point systems with un-smooth operators. In Proc. of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD, pages 9–16, San Jose, CA, November 2010. IEEE/ACM.

[NBS10] T-D. Nguyen, O. Berder, and O. Sentieys. Cooperative miso and relay comparison in energy constrainedwsns. In Proc. of the 71st IEEE International Vehicular Technology conference (VTC), pages 1–5, Taipei, Taiwan,May 2010.

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[NMBS10] T.D. Nguyen, L. Mai, O. Berder, and O. Sentieys. Cooperative mimo and relay association strategy. InInternational Conferences on Advanced Technologies for Communications (ATC), pages 327 – 330, Ho Chi Minhcity, Vietnam, October 2010.

[TBS10] L.Q.V. Tran, O. Berder, and O. Sentieys. Energy efficiency of cooperative strategies in wireless sensornetworks. In International Conferences on Advanced Technologies for Communications (ATC), pages 29 – 32, HoChi Minh city, Vietnam, October 2010.

[TSD11] Vivek D. Tovinakere, Olivier Sentieys, and Steven Derrien. Wakeup time and wakeup energy estimation inpower-gated logic clusters. In Proc. of the 24th International Conference on VLSI Design (VLSID), pages 340 –345, Chennai, India, January 2011.

[TBS11b] Le-Quang-Vinh Tran, Olivier Berder, and Olivier Sentieys. Non-regenerative full distributed space-timecodes in cooperative relaying networks. In Proc. of the IEEE International Wireless Communications and Net-working Conference (WCNC), pages 1529 – 1533, Cancun, Mexico, March 2011.

[TBS11c] Le-Quang-Vinh Tran, Olivier Berder, and Olivier Sentieys. Spectral efficiency and energy efficiency ofdistributed space-time relaying models. In Proc. of the IEEE Conference on Consumer Communications andNetworking Conference (CCNC), pages 1088 –1092, Las Vegas, US, January 2011.

[TSD11] Vivek D. Tovinakere, Olivier Sentieys, and Steven Derrien. A Semiemperical Model for Wakeup TimeEstimation in Power-Gated Logic Clusters. In Proc. of the 49th IEEE/ACM Design Automation Conference(DAC), pages 1–6, San Francisco, CA, USA, June 2012.

[BQS+08] O. Berder, P. Quemerais, O. Sentieys, J. Astier, T.D. Nguyen, J. Menard, G. Le Mestre, Y. Le Roux,Y. Kokar, G. Zaharia, R. Benzerga, X. Castel, M. Himdi, G. El Zein, S. Jegou, P. Cosquer, and M. Bernard.Cooperative communications between vehicles and intelligent road signs. In Proceedings of the 8th InternationalConference on ITS Telecommunications (ITST), pages 121 – 126, Phuket, Thailand, October 2008.

[CPS08] D. Chillet, S. Pillement, and O. Sentieys. Reconfigurable artificial neural network model for task schedulingon reconfigurable soc. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008), pages 92–99, Bruxelles, Belgium, November 2008.

[CSLJ08b] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. Interconnect Explorer: a High-Level Estimation Toolfor On-Chip Interconnects. In Sophia Antipolis MicroElectronics Forum (SAME 2008), Nice, France, October2008. University Booth.

[CSLJ08c] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. New directions in interconnect performance optimiza-tion. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages1–6, Tozeur, Tunisia, March 2008.

[GDCS08] E. Grace, R. David, D. Chillet, and O. Sentieys. Morea: A memory-oriented reconfigurable embeddedarchitecture. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , pages124–131, Bruxelles, Belgium, November 2008.

[NMRS08] H.-N. Nguyen, D. Menard, R. Rocher, and O. Sentieys. Accuracy Constraint Determination in Fixed-PointSystem Design. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , pages132–139, Bruxelles, Belgium, November 2008.

[PPS08] S. Pillement, JM. Philippe, and O. Sentieys. A new approach of coding to improve speed and noise toleranceof on-chip busses. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era(DTIS), pages 1–6, Tozeur, Tunisia, March 2008.

[CLSJ09c] A. Courtay, J. Laurent, O. Sentieys, and N. Julien. On-chip interconnects energy consumption: High-levelestimation and architectural optimizations. In PhD forum of IEEE/ACM Design, Automation & Test in EuropeConference, DATE’09, Nice, France, 2009.

[NBS09] T-D. Nguyen, O. Berder, and O. Sentieys. Cooperative strategies comparison for infrastructure and vehiclecommunications in captiv. In Proc. of the 9th International Conference on ITS Telecommunication (ITST), Lille,France, October 2009.

[ACPS10] A.Eiche, D. Chillet, S. Pillement, and O. Sentieys. Task placement for dynamic and partial reconfigurableregion. In Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pages82–88, Edinburgh, UK, October 2010.

[BS10] O. Berder and O. Sentieys. Powwow: Power optimized hardware/software framework for wireless motes. InProc. of the Workshop on Ultra-Low Power Sensor Networks (WUPS), co-located with Int. Conf. on Architectureof Computing Systems (ARCS 2010), pages 229–233, Hannover, Germany, February 2010.

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[BSCC10] Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, and Arnaud Carer. A coarse-grain reconfigurablehardware architecture for rvc-cal-based design. In Proc. of the Conference on Design and Architectures for Signaland Image Processing (DASIP), pages 161–168, Edinburgh, UK, October 2010.

[MNR+10] D. Menard, D. Novo, R. Rocher, F. Catthoor, and O. Sentieys. Quantization Mode Opportunities in Fixed-Point System Design. In Proc. of the XVIII European Signal and Image Processing Conference (EUSIPCO’10),pages 542–546, Aalborg, Denmark, August 2010. EURASIP.

[PDS10a] A. Pasha, S. Derrien, and O. Sentieys. A Novel Approach for Ultra Low-Power WSN Node Generation. InProc. of the IET Irish Signals and Systems Conference (ISSC 2010), pages 204 – 209, Cork, Ireland, June 2010.

[PRMS10b] K. Parashar, R. Rocher, D. Menard, and O. Sentieys. Estimating Frequency Characteristics of Quantiza-tion Noise for Performance Evaluation of Fixed Point Systems. In Proc. of the XVIII European Signal and ImageProcessing Conference (EUSIPCO’10), pages 552–556, Aalborg, Denmark, August 2010. EURASIP.

[ABMS11a] Mahtab Alam, Olivier Berder, Daniel Menard, and Olivier Sentieys. Accurate energy consumption evalua-tion of preamble sampling MAC protocols for WSN. In Proc. of the Workshop on Ultra-Low Power Sensor Networks(WUPS), co-located with Int. Conf. on Architecture of Computing Systems (ARCS), Como, Italy, February 2011.

[ABMS11b] Mahtab Alam, Olivier Berder, Daniel Menard, and Olivier Sentieys. Traffic-aware adaptive wake-up-interval for preamble sampling MAC protocols of WSN. In Proc. of the International Workshop on Cross-LayerDesign (IWCLD), Rennes, France, December 2011.

[APSP11] Muhammad Moazam Azeem, Stanislaw Piestrak, Olivier Sentieys, and Sebastien Pillement. Error recoverytechnique for coarse-grained reconfigurable architectures. In Proc. IEEE 14th International Symposium on Designand Diagnostics of Electronic Circuits & Systems (DDECS), pages 441–446, April 2011.

[BCBS11a] Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, and Olivier Sentieys. Parallelism level impact on energyconsumption in reconfigurable devices. In Proc. International Workshop on Highly-Efficient Accelerators andReconfigurable Technologies (HEART), Londres, May 2011. Also in SIGARCH Comput. Archit. News, 39(4):104–105, Sept. 2010.

[BCSB11] Robin Bonamy, Daniel Chillet, Olivier Sentieys, and Sebastien Bilavarn. Towards a power and energyefficient use of partial dynamic reconfiguration. In Proc. 6th Int. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pages 1–4, Montpellier, France, June 2011.

[BSB+11] Dominique Blouin, Eric Senn, Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, and Christian Samoyeau.FPGA modeling for SoC design exploration. In Proc. International Workshop on Highly-Efficient Accelerators andReconfigurable Technologies (HEART), Londres, May 2011.

[ECPS11] Antoine Eiche, Daniel Chillet, Sebastien Pillement, and Olivier Sentieys. Parallel evaluation of Hopfieldneural networks. In Proc. International Conference on Neural Computation Theory and Applications (NCTA),Paris, France, October 2011.

[NMMS11b] Jean-Charles Naud, Quentin Meunier, Daniel Menard, and Olivier Sentieys. Fixed-point accuracy eval-uation in the context of conditional structures. In Proc. of the 19th European Signal Processing Conference(EUSIPCO), Barcelona, Spain, September 2011.

[NMS11] Hai-Nam Nguyen, Daniel Menard, and Olivier Sentieys. Novel algorithms for word-length optimization. InProc. 19th European Signal Processing Conference (EUSIPCO), Barcelona, Spain, September 2011.

[TDCS11] Matthieu Texier, Raphael David, Karim Ben Chehida, and Olivier Sentieys. Graphic rendering applicationprofiling on a shared memory MPSoC architecture. In Proc. of the Conference on Design and Architectures forSignal and Image Processing (DASIP), Tampere Finland, November 2011.

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