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Unit 5

5.1: CMOS Process Flow: The difference between new and old process flow are as

mentioned here. Minimum length of the channel, L min < 0.35 micro m in the case of

sub micron CMOS process. The device isolation technique is Shallow Trench Isolation

(STI) instead of local oxidation of Silicon (LOCOS). n+ poly is employed for NMOS and

p+ poly for PMOS formulation. Drains are lightly doped to reduce short channel effects.

Silicided source / drain / gates are used to reduce parasitic resistances. NMOS & PMOS

are developed as surface devices and thus PMOS is not a buried channel device.

The steps in CMOS Process Flow:

Step 1: The Process starts with p type wafer or p+ wafer with p- epitaxial layer. Thin

oxide and nitride are deposited. The purpose of deposition is for active areas patterning.

Photo resist is deposited and patterned on its top. Exposed area of nitride is then

removed. The step is shown in fig. 5.1 (a)

Step 2: Silicon areas that are exposed are etched. It is the part not covered by photo resist.

Thus, shallow trenches are formed as shown in fig 5.1 (b)

fig. 5.1 (a)

SShhaalllloowwttrreenncchheess

fig. 5.1 (b)


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Step 3: Shallow trenches formed in step 2 are filled with Chemical Vapor Oxide (CVD)

(STI). The process is known as Chemical Mechanical Polishing (CMP). Thus, the top is

now flat as in fig. 5.1 (c).

Step 4: Implants are used to make body of the PMOS (n well) transistors. Fig. 5.1

(d) shows the wafer after implant.

Step 5: Patterning the polysilicon gates on the top of the wafer is carried out in this step.

The effect of it is shown in fig. 5.1 (e).

Step 6: Light and shallow implants are used in lightly doped drain (LDD) MOSFET

formulation as in fig. 5.1 (f)

fig. 5.1 (c)

fig. 5.1 (d)

fi . 5.1 (e)


3/26

Step 7: in this step, lateral oxide spacer adjacent to the gate poly is formed. Implants to

heavily doped gates, sources and drains are formed. p+ poly is used in PMOS

formulation. The result of the same is shown in fig. 5.1 (g).

Step 8: in this last step, silicide is deposited. It is combination of silicon and tungsten

metal.

There are certain advantages of CMOS Process. CVD or STI enables to define smaller

openings in the top of the wafer. This leads to smaller active area windows. Thus,

effective encroachment on the device width is reduced. Now, MOSFET can be placedcloser together. p+ poly used in PMOS formulation results in surface device. Because of

which, conduction between the source and drain is along the oxide / semi conductor

interface. And not through buried channel. In surface device, threshold voltage of the

PMOS is easier to set precisely. There is no need to counter dope the channel for the

purpose. It is also observed that short channel effect less severe. Use of Silicide produces

fi . 5.1 f

fig. 5.1 (g)

fig. 5.1 h)


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devices with significantly less parasitic series gate and source / drain resistances.

However, Silicide complicates the process. Surface device reduces mobility and increase

in flicker noise.

5.2.1: Implementation of Capacitors: four types of capacitors will be considered in the

discussion to follow. They are MOSFET as a capacitor, Native / natural MOSFET

capacitor, Floating capacitor and Metal capacitor.

Using MOSFET as a capacitor: As shown in fig. 5.2, source, drain and body are

connected to ground. Gate is available as one terminal. The capacitor thus formed is a

unipolar capacitor.

As in fig. 5.3, VGS should be much greater than 400mV for the device to behave as a

capacitor. If it is not satisfied, capacitor exhibits non linearity.

Using native MOSFET capacitor: It is formed by laying out poly over n+ active in n well.

It is also unipolar capacitor. The symbolic representation of it is shown in fig.

fig. 5.2

fig. 5.3


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The laying out of native capacitor is shown in fig. 5.5. poly over n+ active in n well

reduces threshold voltage. Thus, it suits for low voltage applications. The capacitance

versus voltage in native capacitor is shown in fig. 5.6. The threshold voltage is 100mv.

The floating Capacitor: here, two PMOS are laid together, adjacent or inter-digitated in

the same n well. Capacitors are in series as in fig. 5.7. the increase in voltage at A causes

accumulation of charges under the left side MOSFET gate oxide. Equal and opposite

charge is stored in B MOSEFT. Minimum voltage requirement is shown in fig. 5.8

fig. 5.4

fig. 5.5

fig. 5.6


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The Metal Capacitor: Metals (copper) have large layout area. Thus, fringe capacitance

contribution is small. The capacitance between the two plates is given by C12=area x

capacitance per area. Thickness of the metal increases if it is away from substrate. The

layout is shown in fig. 5.8

The two parallel plates in parallel plate capacitor are metal 1 and metal 2. The capacitor

is also referred to as metal1-metal2 capacitor. The typical capacitance per micro m 2area

is 25-50aF/micro m2. It requires an area of 100 micro m x 200 micro m for 1pF capacitor.

Capacitor with large bottom plate suffers from parasitic capacitance. It is the capacitance

between metal1 and substrate. Its value is significant and 80 % to 100 % of actual

capacitance. The presence of parasitic capacitance results in slow response from a circuit

and waste of power.

Vx VDDfig. 5.8

fig. 5.7

fig. 5.8


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The 4 layers Metal Capacitor is shown in fig. 5.9. the total capacitance is given by

C=C12 + C23 + C34. 50aF/micro m2requires area of 100 micro m x 200/3 = 66 micro m

for 1pF capacitor. Thus, reduces area by 1/3rd

. Capacitance between metal 1 and substrate

is now less, in comparison with total capacitance C and hence there is reduction in

parasitic capacitance.

There is possibility of metal1 only capacitor also. Two metal pieces are placed close to

each other in the layer above substrate. There is fringe capacitance, in metal1 only

capacitor. It is because of minimum width and distance between two pieces of metal1. If

0.5 micro meters is the width and distance, effect is predominant. Effect of fringe

capacitance is more than parasitic capacitance. The layout of metal1 only capacitor and

fringe effect is shown in fig. 5.10 and 5.11 respectively. Fringe capacitance is due to

electric field terminating on the close adjacent metal.

fig. 5.9

fig. 5.10


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Problem 1: Estimate the area of metal1 only 1 pF capacitor in a layout as shown in fig.

5.P1. Also determine parasitic capacitance.

Solution

Capacitance per 1 micro m2 is 25aF is given.

Thus, for 1pF, area = 1pF/25aF = 40000 micro m2

Parasitic capacitance (usually 50%) =1pF/2 = 0.5pF

Capacitance With Via is yet another capacitance layout. Lateral capacitance between

vias, as in metal1- metal4 is shown in fig. 5.12. The capacitance per unit area increases,

though not linearly. It is of the order of 200aF/micro m2. The bottom plate capacitance

remains at 15aF/micro m2. For higher levels of metal, the rules for width and spacing

between the metals are different. Thus, thumb rule for implementation of capacitance in a

mixed signal circuit is lateral capacitance with several layers of metal and vias.

fig. 5.11

fig. 5.P1


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Example 2: Estimate the area of lateral capacitor for 1 pF capacitor in a layout.Solution:

Capacitance per 1 micro m2 is 200aF because of lateral capacitance. .

For 1pF, area = 1pF/200aF=5000 micro m2

5.2.2: Properties of Resistors: the typical properties of variety of resistors is listed intable 3.1

One of the properties of resistor is its Voltage Coefficient of Resistor (VCR). It is due to

mismatch in voltages across two equal valued resistors even when same voltage is

applied across each resistor. Mismatch = VCR x difference in voltages across two

resistors. Extension of depletion region into n type material in n well, leads to VCR

problem. The Mismatch % is the variation in the same valued resistors.RR/

fig. 5.12

Table 5.1


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Temperature Coefficient of Resistor (TCR) is variation of resistance value with

temperature. All these errors will lead non linear behavior of resistor. Polysilicon, p+, n+

poly. p+, n+ diffusion are the various types of resistors with and without Silicide. The

error is found to be less in polysilicon. Hence it is used in high precision circuits, such as

DAC.

Example 3

Determine the minimum and maximum area required to implement resistor of 1Kohm

in a Submicron CMOS process and also name the resistor type.

Solution

Minimum Resistance per micro m2is for p+ silicide

Area = 1k/2=500 micro m2

Thus requires maximum area.

Maximum Resistance per micro m2 is for n wellArea = 1k/500=2 micro m

2

Thus requires minimum area

Example 4

Determine the minimum and maximum mismatch error while two 1Kohm are

connected in parallel in the case of n well and p+ diff.

Solution

Mismatch error in n well =0.001

For two 1K in parallel,

Value=500.0005 ohm

Error=0.0001%

Minimum mismatch

Mismatch error in p+ diff =0.01 500.005

Error=0.001%

Maximum mismatch

Example 5

Determine the mismatch error while two 1Kohm are connected

(a) in parallel in the case of p+ without silicide.

(b) in series in the case of p+ without silicide.

Comment on the results

SolutionMismatch error in p+ without silicide =0.002

For two 1K in parallel,

Value=500.001 ohm

Error=0.0002%

For two 1K in series,

Value=2000.004 ohm


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Error=0.0002%

5.2.3: Implementation of Resistors: There is a limitation on width and length of the

resistor which can be implemented in CMOS submicron process. The minimum width of

resistor is 10 times the process feature size (Lmin) and minimum length of resistor is 100

times the process feature size (Lmin). This ensures less mismatching and less self

heating. The larger the area the better is heat dissipation. Simplified layout of a resistor is

depicted in fig. 5.13. also, it is shown a resistor with large width and length for better

matching and power dissipation. Multiple connecting leads (contacts) reduce the metal-

resistive material contact resistance.

The problems encountered in implementing resistor are conductivity modulation and

process gradient. Conductivity modulation is because of the difficulty in implementing a

metal over resistive material. The metal at a potential higher than the resistor attracts

more electrons causing non uniform distribution of electrons and spots of lower

resistivity in the resistor. This is referred to as Conductivity modulation.

Modification in conductivity is avoided by avoiding running metal over resistor. Or using

high levels of metal to route the resistive signals, thus, increasing the distance betweenthe resistors and overlaying metal. Sometimes, conductivity modulation is avoided by

inserting a conducting shield connected to analog ground and metal1 between resistors

and routing wire above the resistive array.

Process Gradient is due to fault in manufacturing process. Each resistor of same value

may have different gradient value. This is called process gradient. Taking the example of

fig. 5.13: simplified layout view of resistor


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difficulty in implementing R-2R DAC, there are several resistors of either R or 2R value.

The binary weights given to different digital inputs vary if resistors are not exactly R and

its double. The layout of resistors for R-2R DAC with process gradient is shown in fig.

5.14. For the purpose of explanation, process gradient is assumed to be linear and +1

along horizontal dimension and +5 along vertical dimension. To get 2R resistor of value

38 (Kohm or any multiple) units of resistor, resistance with value 6, 8,11 and 13 are to be

connected in series as shown in fig. 5.14. The process gradient of resistor 6 and 8 are

respectively (1+5) % and (3+5) %, whereas process gradient of resistor 11 and 13 are

respectively 11% and 13%. Total process gradient of the series resistor is thus 38 units.

Similarly, to form any value resistor, the process gradient also comes out to be same % as

the resistor. Thus, delta R/R is same for all resistors. Thus, the problems associated with

process gradient, if linear, can be removed. The remaining errors in resistor are due to

temperature and voltage, the discussion of their elimination is beyond the scope of this

chapter.

5.3: Digital Circuit Design: Basic Building blocks in a digital circuit are MOSFET

switch, bidirectional switch, delay elements, counters and adders. MOSFET Switch

employs either NMOS or PMOS. Digital switching resistance is function of width (W)

fig. 5.14


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and length (L) of the device and also function of submicron CMOS process. For NMOS

switch, digital switching resistance is given by

Rn=VDS/ ID (5.1)

The circuit arrangement for determination of digital switching resistance is shown in fig.

5.15. VDSis varied and IDis noted. The plot of Rnversus Voltage sweep at drain is shown

in fig. 5.16. It is observed that the resistance increase with increase in VDSand decrease

with increase in W/L of the device. Mathematically, digital switching resistance of the

switch is,

fi . 5.16

fi . 5.15

W

L

KP

VVK

W

LkR

n

THNDDn )(1

10n

+

=


14/26

Example 1

In the arrangement shown in fig. 5.17, determine the effective digital resistance of the

MOSFET.

Determine the delay time for a load of 1pF.

Solution

The MOSFET has W / L =10/1.Rn=10Kohm(L / W)=10K/10=1Kohm

Delay time for a load of 1pF=RnxC=1ns

The plot of input and output versus time is shown in fig. 5.18. When the input is zero,

output is 1.5V. When the input makes transition to 1.5 V at 2ns, the output changes to

zero volts by taking a delay time of 1ns.

5.3.1: PMOS switch

The arrangement for determination of digital switching resistance in the case of PMOS is

shown in fig. 5.19. The resistance of PMOS switch is given by eq (5.2). The resistance is

double the resistance of NMOS device. The plot of resistance versus voltage sweep is

shown in fig. 5.20.

fi . 5.17

fi . 5.18


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5.3.2: Comparison of NMOS and PMOS switch

In NMOS Rn increases with increase in VDD and in PMOS Rn decreases with increase

in VDD. In NMOS source connected to ground and in PMOS source connected to VDD.

NMOS switch can not pass logic high well whereas, PMOS switch can not pass logic low

well. In both NMOS and PMOS switches, the expression given holds good for all sourceto drain voltages. It is an average estimate. An average estimate of resistance suits for

complementary static CMOS logic design. Device size selection is based on drive

strength.

fi . 5.19

fi . 5.20

W

L

KP

VVK

W

LkR

p

THPDDp )(1

20p

+

=


16/26

Example 2:

Estimate the high-to-low and low-to-high delays in the circuit shown. Assume the deviceto be of NMOS.

Solution Given W / L =40/20 Digital switching resistance, Rn=10Kohm(L/W)

=10K(20/40)=5Kohm

Capacitive load, C = 1pF

high-to-low and low-to-high delays = RnC= 5Kx1p=5ns

Example 3

Repeat the same for PMOS Given W / L =40/20 Digital switching resistance, Rn=20Kohm(L/W)

=10Kohm

Capacitive load, C = 1pF high-to-low and low-to-high delays =10ns

PMOS Device is slower than NMOS device

5.3.3: Bidirectional Switch: It is also referred to as pass gate. The current flow is in

bidirectional. The effective switching resistance is too large. It is because NMOS switch

can not pass logic high well and PMOS switch can not pass logic low well. The circuit

arrangement for the pass gate is shown in fig. 5.22. Vin is passed over to the output by

increasing the gate voltage.

In Out

1pF

40/20

fi . 5.21


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5.3.4: Importance of Delay Element: It is used in implementation of digital averaging

or comb filter. Average of past & present input samples y(n)=(x(n)+x(n-1))/2. Thus

H(z)=(1+z-1 )/2. Number of past inputs referred in moving average filter is of the order

of 100s or 1000s. Delay elements are also used in decimation circuit with factor K and in

noise shaping filter. ADC, DAC etc.

Delay Element is continuously clocked circuit. Requirements of delay elements are that it

should be with low power consumption and should occupy smaller layout area. Delay

element as a cascade of two pass transistors and inverters is shown in fig. 5.23.

Working of Delay Element: Whenever the clock is high, the output of the master is

transferred to the slave. Whenever the clock is low, the output is unchanged. Thus, it is a

rising edge triggered D flip-flop. The plot of input, clock and output is shown in fig. 5.24.

fig. 5.22

fi . 5.23


18/26

It requires two clock signals and has true output (no complement output). NMOS switch

employed can not pass logic high well. Maximum input to the inverters is VDD-VTHN.

VDD source has to supply excess current, 50 micro A for 100MHz clock speed. It leads

to more power dissipation.

Clocked CMOS Logic: It is shown in fig. 5.25. it has less power dissipation, it is because

of 10 micro A for 100MHz clock speed. Layout area is larger. It has an advantage of ease

of implementing RESET. It requires two clock signals and has true output (no

complement output). It is also rising edge triggered D flip-flop.

OUT

IN

CLK

fig. 5.24

fi . 5.25


19/26

No marginal logic levels. That is, levels are either 0 or VDD. The same Input-output

relationship with respect to clock is maintained as in simple delay element. A single

Clock Delay Element is shown in fig. 5.26. It is referred to as True Single Phase

Clocking (TSPC). Layout area is nearly same as Clocked CMOS Logic. It is rising edge

triggered. It exhibits less power dissipation, less than 10 micro A for 100MHz clock

speed. Two outputs, true and complement outputs hence Divide-by-2 circuit is possible.

At the rising edge of the clock, output=D input. For Divide-by-2 circuit, output should

change at the occurrence of every rising edge. D input can be changed before the

occurrence of the rising edge of the clock by connecting it to complement output. The

output of Divide-by-2 Circuit using TSPC is shown in fig. 5.27. Divide-by-2 circuit

divides the clock frequency by 2. Some of the applications are in decimation and

interpolation multirate systems and in up / down counter.

fi . 5.26

fi . 5.26


20/26

In ripple up counter shown in fig. 5.28, each D flip-flop is TSPC. The complement output

of each flip flop is connected to its D input. The clock for a flip flop is derived from

complement output of lower order bit flip flop. Output is taken from true output points of

flip flop. Whereas in ripple Down Counter, as shown in fig. 5.29, the complement output

of each flip flop is connected to its D input. The clock for a flip flop is derived from

complement output of lower order bit flip flop. Output is taken from complement output

points of flip flop.

fi . 5.27

fig. 5.28fi . 5.29


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Synchronous Up Counter is designed using ripple up counter. The output of ripple down

counter is fed to a set of D flip flops which are clocked simultaneously. The output is

taken from complemented output of second stage of flip flop. The arrangement is shown

in fig. 5.30. In a similar way, Synchronous down Counter is designed using ripple up

counter. The output of which is fed to a set of D flip flops which are clocked

simultaneously. The arrangement is shown in fig. 5.31. in this case, the output is taken

from complemented output of second stage of flip flop.

Synchronous Up / Down Counter: It is designed to count either in up direction or in down

direction. The direction of count is decided by select line. A multiplexer selects data of n

fi . 5.30

fi . 5.31


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bits with its LSB as 1 and all other bits as zeros if up counter is selected. The counter

output is zero initially. The output of counter is fed as one input to the adder and other

input is n bit data through multiplexr. During up counter, n bit data gets added with the

counter output every time and there will be an output counting in up direction. In a

similar way, during down counter selection, n bit data is all ones and counter output is

initially zero. Thus the first output from the counter will be all ones. During next cycle,

when all ones are added with all ones, the count reduces by one. This continues and the

counter counts down. The circuit arrangement for the same is shown in fig. 5.32.

5.3.5: Full Adder: The circuit arrangement for full adder using MOSFET is shown in

fig. 5.33. the simplication of truth table for full adder gives the expression for the sum

and carry as in eq. 5.1 and 5.2.

fi . 5.32

fi . 5.33

(5.2))(.. coutcbacbasum inininininin +++=

(5.1))(. ininininin bacbacout ++=


23/26

4-bit Pipelined Adder: Using the circuit arrangement of fig. 5.33, a 4 bit full adder is

implemented as shown in fig. 5.34. Least significant bits of two data are added and carry

is propagated to the next stage. The output of this addition is made available only after

the addition of all bits using three bufrers to hold the results. In a simlar way other higher

significant bits are added.

5.4: Analog Circuit Design:

5.4.1: Biasing:For the circuit of OPAMP differential amplifier the biasing is shown in

fig. 5.35. Selecting excess gate voltage is done as follows. Let minimum voltage across

drain and source of a MOSFET, VDSsat= V . Gate to source voltage, VGS=VTHN+ V . In

0.15 micro m submicron process, threshold voltage=0.4V for both NMOS & PMOS

devices. For the circuit of OPAMP differential amplifier shown in fig. 5.35, KVL from

VDD to ground is applied. Through M8, M2, M3, M5. Leads to

VDD= VSG8+ VDS2+ VSD3+ VGS5

Solving for, V it is 175mV.

fi . 5.34

THNTHPDD VVVVVVV ++++++=


24/26

Selecting channel length: Small signal output resistance proportional to channel length in

NMOS & PMOS devices. Increase channel length decreases speed. Increase in output

resistance increases gain. Typical plot of output resistance versus drain-source voltage is

shown in fig. 5.36 for NMOS device. As W/L increase resistance increases.

Small signal transconductance: Transconductance of PMOS is less than that of NMOS.

The plot of transconductance versus frequency for both NMOS and PMOS are shown in

fig. 5.37 and fig. 5.38 respectively for NMOS and PMOS devices. For NMOS the value

is 185 micro A/V and for PMOS it is 105 micro A/V.

fi . 5.35


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fig. 5.36

fi . 5.37


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MOSFET Transition Frequency: It is the frequency at which AC gate current is equal to

AC drain current

High speed devices have large transition frequency. Transition frequency of NMOS

device is around 4.5x10^9 Hz and that for PMOS is slightly more than 10^9 Hz. The plot

of ratio of AC gate current to AC drain current versus frequency are shown in fig. 5.38

and fig. 5.39.

Transition frequency of PMOS device

dBi

i

d

d 01==L

Vf GST =

fi . 5.38

fi . 5.39

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