Cyclone IV Transceivers Architecture, Cyclone IV Device Handbook, Volume 2, Chapter 1. CYIV-52001-3.7
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Cyclone IV Device Handbook, Volume 2 February 2015
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1. Cyclone IV Transceivers Architecture
Cyclone® IV GX devices include up to eight full-duplex transceivers at serial data rates between 600 Mbps and 3.125 Gbps in a low-cost FPGA. Table 1–1 lists the supported Cyclone IV GX transceiver channel serial protocols.
You can implement these protocols through the ALTGX MegaWizard™ Plug-In Manager, which also offers the highly flexible Basic functional mode to implement proprietary serial protocols at the following serial data rates:
600 Mbps to 2.5 Gbps for devices in F324 and smaller packages
600 Mbps to 3.125 Gbps for devices in F484 and larger packages
For descriptions of the ports available when instantiating a transceiver using the ALTGX megafunction, refer to “Transceiver Top-Level Port Lists” on page 1–85.
f For more information about Cyclone IV transceivers that run at 2.97 Gbps data rate, refer to the Cyclone IV Device Family Pin Connection Guidelines.
Table 1–1. Serial Protocols Supported by the Cyclone IV GX Transceiver Channels
Protocol Data Rate (Gbps) F324 and smaller packages
F484 and larger packages
Gbps Ethernet (GbE) 1.25 v v
Common Public Radio Interface (CPRI) 0.6144, 1.2288, 2.4576, and 3.072 v (2) v
OBSAI 0.768, 1.536, and 3.072 v (2) v
XAUI 3.125 — v
Serial digital interface (SDI) HD-SDI at 1.485 and 1.4835 v
v 3G-SDI at 2.97 and 2.967 —
Serial RapidIO® (SRIO) 1.25, 2.5, and 3.125 — v
Serial Advanced Technology Attachment (SATA) 1.5 and 3.0 — v
V-by-one 3.125 — v
Notes to Table 1–1:
(1) Provides the physical interface for PCI Express (PIPE)-compliant interface that supports Gen1 ×1, ×2, and ×4 initial lane width configurations. When implementing ×1 or ×2 interface, remaining channels in the transceiver block are available to implement other protocols.
(2) Supports data rates up to 2.5 Gbps only.
February 2015 CYIV-52001-3.7
1–2 Chapter 1: Cyclone IV Transceivers Architecture Transceiver Architecture
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1 The Cyclone IV GX device includes a hard intellectual property (IP) implementation of the PCIe MegaCore® functions, supporting Gen1 ×1, ×2, and ×4 initial lane widths configured in the root port or endpoint mode. For more information, refer to “PCI- Express Hard IP Block” on page 1–46.
Transceiver Architecture Cyclone IV GX devices offer either one or two transceiver blocks per device, depending on the package. Each block consists of four full-duplex (transmitter and receiver) channels, located on the left side of the device (in a die-top view). Figure 1–1 and Figure 1–2 show the die-top view of the transceiver block and related resource locations in Cyclone IV GX devices.
Figure 1–1. F324 and Smaller Packages with Transceiver Channels for Cyclone IV GX Devices
Note to Figure 1–1:
(1) Channel 2 and Channel 3 are not available in the F169 and smaller packages.
MPLL_2
MPLL_1
F324 and smaller packages
Chapter 1: Cyclone IV Transceivers Architecture 1–3 Transceiver Architecture
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For more information about the transceiver architecture, refer to the following sections:
“Architectural Overview” on page 1–4
“Transmitter Channel Datapath” on page 1–5
“Receiver Channel Datapath” on page 1–11
“Transceiver Clocking Architecture” on page 1–26
“Transceiver Channel Datapath Clocking” on page 1–29
“FPGA Fabric-Transceiver Interface Clocking” on page 1–43
“Calibration Block” on page 1–45
“PCI-Express Hard IP Block” on page 1–46
Figure 1–2. F484 and Larger Packages with Transceiver Channels for Cyclone IV GX Devices
MPLL_8 GPLL_2
MPLL_5
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Architectural Overview Figure 1–3 shows the Cyclone IV GX transceiver channel datapath.
Each transceiver channel consists of a transmitter and a receiver datapath. Each datapath is further structured into the following:
Physical media attachment (PMA)—includes analog circuitry for I/O buffers, clock data recovery (CDR), serializer/deserializer (SERDES), and programmable pre-emphasis and equalization to optimize serial data channel performance.
Physical coding sublayer (PCS)—includes hard logic implementation of digital functionality within the transceiver that is compliant with supported protocols.
Outbound parallel data from the FPGA fabric flows through the transmitter PCS and PMA, is transmitted as serial data. Received inbound serial data flows through the receiver PMA and PCS into the FPGA fabric. The transceiver supports the following interface widths:
FPGA fabric-transceiver PCS—8, 10, 16, or 20 bits
PMA-PCS—8 or 10 bits
f The transceiver channel interfaces through the PIPE when configured for PCIe protocol implementation. The PIPE is compliant with version 2.00 of the PHY Interface for the PCI Express Architecture specification.
Figure 1–3. Transceiver Channel Datapath for Cyclone IV GX Devices
Byte Serializer 8B/10B Encoder
Serializer
February 2015 Altera Corporation Cyclone IV Device Handbook, Volume 2
Transmitter Channel Datapath The following sections describe the Cyclone IV GX transmitter channel datapath architecture as shown in Figure 1–3:
TX Phase Compensation FIFO
Transmitter Output Buffer
TX Phase Compensation FIFO The TX phase compensation FIFO compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock, when interfacing the transmitter channel to the FPGA fabric (directly or through the PIPE and PCIe hard IP). The FIFO is four words deep, with latency between two to three parallel clock cycles. Figure 1–4 shows the TX phase compensation FIFO block diagram.
1 The FIFO can operate in registered mode, contributing to only one parallel clock cycle of latency in Deterministic Latency functional mode. For more information, refer to “Deterministic Latency Mode” on page 1–73.
f For more information about FIFO clocking, refer to “FPGA Fabric-Transceiver Interface Clocking” on page 1–43.
Byte Serializer The byte serializer divides the input datapath width by two to allow transmitter channel operation at higher data rates while meeting the maximum FPGA fabric frequency limit. This module is required in configurations that exceed the maximum FPGA fabric-transceiver interface clock frequency limit and optional in configurations that do not.
f For the FPGA fabric-transceiver interface frequency specifications, refer to the Cyclone IV Device Data Sheet.
Figure 1–4. TX Phase Compensation FIFO Block Diagram
Note to Figure 1–4:
(1) The x refers to the supported 8-, 10-, 16-, or 20-bits transceiver channel width.
tx_phase_comp_fifo_errorTX Phase Compensation
or the 8B/10B encoder
Cyclone IV Device Handbook, February 2015 Altera Corporation Volume 2
For example, when operating an EP4CGX150 transmitter channel at 3.125 Gbps without byte serializer, the FPGA fabric frequency is 312.5 MHz (3.125 Gbps/10). This implementation violates the frequency limit and is not supported. Channel operation at 3.125 Gbps is supported when byte serializer is used, where the FPGA fabric frequency is 156.25 MHz (3.125 Gbps/20).
The byte serializer forwards the least significant byte first, followed by the most significant byte.
8B/10B Encoder The optional 8B/10B encoder generates 10-bit code groups with proper disparity from the 8-bit data and 1-bit control identifier as shown in Figure 1–5.
f The encoder is compliant with Clause 36 of the IEEE 802.3 Specification.
The 1-bit control identifier (tx_ctrlenable) port controls the 8-bit translation to either a 10-bit data word (Dx.y) or a 10-bit control word (Kx.y). Figure 1–6 shows the 8B/10B encoding operation with the tx_ctrlenable port, where the second 8'hBC data is encoded as a control word when tx_ctrlenable port is asserted, while the rest of the data is encoded as a data word.
1 The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters for which the tx_ctrlenable port should be asserted. If you assert tx_ctrlenable port for any other set of characters, the 8B/10B encoder might encode the output 10- bit code as an invalid code (it does not map to a valid Dx.y or Kx.y code), or an unintended valid Dx.y code, depending on the value entered. It is possible for a downstream 8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting any code error flags. Altera recommends not to assert tx_ctrlenable port for unsupported 8-bit characters.
Figure 1–5. 8B/10B Encoder Block Diagram
Figure 1–6. Control and Data Word Encoding with the 8B/10B Encoder
tx_ctrlenable
February 2015 Altera Corporation Cyclone IV Device Handbook, Volume 2
The following describes the 8B/10B encoder behavior in reset condition (as shown in Figure 1–7):
During reset, the 8B/10B encoder ignores the inputs (tx_datain and tx_ctrlenable ports) from the FPGA fabric and outputs the K28.5 pattern from the RD- column continuously until the tx_digitalreset port is deasserted.
Upon deassertion of the tx_digitalreset port, the 8B/10B encoder starts with a negative disparity and transmits three K28.5 code groups for synchronization before it starts encoding and transmitting data on its output.
Due to some pipelining of the transmitter PCS, some "don't cares" (10'hxxx) are sent before the three synchronizing K28.5 code groups.
The encoder supports forcing the running disparity to either positive or negative disparity with tx_forcedisp and tx_dispval ports. Figure 1–8 shows an example of tx_forcedisp and tx_dispval port use, where data is shown in hexadecimal radix.
In this example, a series of K28.5 code groups are continuously sent. The stream alternates between a positive disparity K28.5 (RD+) and a negative disparity K28.5 (RD-) to maintain a neutral overall disparity. The current running disparity at time n + 1 indicates that the K28.5 in time n + 2 should be encoded with a negative disparity. Because tx_forcedisp is high at time n + 2, and tx_dispval is low, the K28.5
Figure 1–7. 8B/10B Encoder Behavior in Reset Condition
Figure 1–8. Force Running Disparity Operation
tx_digitalreset
clock
During reset
dataout[9..0] K28.5- K28.5- K28.5- xxx xxx K28.5+K28.5- K28.5- Dx.y+
Don’t cares after reset Synchronization Normal operation
tx_ctrlenable
clock
tx_forcedisp
tx_dispval
Current Disparity RD- RD+ RD+ RD- RD- RD+RD- RD+
dataout[9..0] 17C 283 17C 17C283 283
txin[7..0] BC
n + 5 n + 6 n + 7
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at time n + 2 is encoded as a positive disparity code group. In the same example, the current running disparity at time n + 5 indicates that the K28.5 in time n + 6 should be encoded with a positive disparity. Because tx_forcedisp is high at time n + 6, and tx_dispval is high, the K28.5 at time n + 6 is encoded as a negative disparity code group.
Miscellaneous Transmitter PCS Features The transmitter PCS supports the following additional features:
Polarity inversion—corrects accidentally swapped positive and negative signals from the serial differential link during board layout by inverting the polarity of each bit. An optional tx_invpolarity port is available to dynamically invert the polarity of every bit of the 8-bit or 10-bit input data to the serializer in the transmitter datapath. Figure 1–9 shows the transmitter polarity inversion feature.
1 tx_invpolarity is a dynamic signal and might cause initial disparity errors at the receiver of an 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors.
Figure 1–9. Transmitter Polarity Inversion
Converted data output to the transmitter serializer
Output from transmitter PCS
LSB
1
0
0
0
1
1
0
1
1
1
MSB
LSB
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Bit reversal—reverses the transmit bit order from LSB-to-MSB (default) to MSB-to-LSB at the input to the serializer. For example, input data to serializer D[7..0] is rewired to D[0..7] for 8-bit data width, and D[9..0] is rewired to D[0..9] for 10-bit data width. Figure 1–10 shows the transmitter bit reversal feature.
Input bit-flip—reverses the bit order at a byte level at the input of the transmitter phase compensation FIFO. For example, if the 16-bit parallel transmitter data at the tx_datain port is '10111100 10101101' (16'hBCAD), selecting this option reverses the input data to the transmitter phase compensation FIFO to '00111101 10110101' (16'h3DB5).
Bit-slip control—delays the data transmission by a number of specified bits to the serializer with the tx_bitslipboundaryselect port. For usage details, refer to the “Transmit Bit-Slip Control” on page 1–76.
Serializer The serializer converts the low-speed parallel 8-bit or 10-bit data from the transmitter PCS to high-speed serial data for the transmitter output buffer. The serializer operates with a high-speed clock at half of the serial data rate. The serializer transmission sequence is LSB to MSB.
Figure 1–10. Transmitter Bit Reversal Operation in Basic Single-Width Mode
Output from transmitter PCS Converted data output to the
transmitter serializer
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
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Transmitter Output Buffer Figure 1–11 shows the transmitter output buffer block diagram.
The Cyclone IV GX transmitter output buffers support the 1.5-V PCML I/O standard and are powered by VCCH_GXB power pins with 2.5-V supply. The 2.5-V supply on VCCH_GXB pins are regulated internally to 1.5-V for the transmitter output buffers. The transmitter output buffers support the following additional features:
Programmable differential output voltage (VOD)—customizes the VOD up to 1200 mV to handle different trace lengths, various backplanes, and various receiver requirements.
Programmable pre-emphasis—boosts high-frequency components in the transmitted signal to maximize the data eye opening at the far-end. The high-frequency components might be attenuated in the transmission media due to data-dependent jitter and intersymbol interference (ISI) effects. The requirement for pre-emphasis increases as the data rates through legacy backplanes increase.
Programmable differential on-chip termination (OCT)—provides calibrated OCT at differential 100 or 150 with on-chip transmitter common mode voltage (VCM) at 0.65 V. VCM is tri-stated when you disable the OCT to use external termination.
1 Disable OCT to use external termination if the link requires a 85 termination, such as when you are interfacing with certain PCIe Gen1 or Gen2 capable devices.
f The Cyclone IV GX transmitter output buffers are current-mode drivers. The resulting VOD voltage is therefore a function of the transmitter termination value. For lists of supported VOD settings, refer to the Cyclone IV Device Data Sheet.
Figure 1–11. Transmitter Output Buffer Block Diagram
Note to Figure 1–11:
(1) Receiver detect function is specific for PCIe protocol implementation only. For more information, refer to “PCI Express (PIPE) Mode” on page 1–52.
GXB_TXp
GXB_TXn
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Receiver Channel Datapath The following sections describe the Cyclone IV GX receiver channel datapath architecture as shown in Figure 1–3 on page 1–4:
“Receiver Input Buffer” on page 1–11
“Clock Data Recovery” on page 1–15
“Deserializer” on page 1–16
“Word Aligner” on page 1–17
“Deskew FIFO” on page 1–22
“Rate Match FIFO” on page 1–23
“8B/10B Decoder” on page 1–23
“Byte Deserializer” on page 1–24
“Byte Ordering” on page 1–24
“RX Phase Compensation FIFO” on page 1–25
Receiver Input Buffer Table 1–2 lists the electrical features supported by the Cyclone IV GX receiver input buffer.
Table 1–2. Electrical Features Supported by the Receiver Input Buffer
I/O Standard Programmable Common Mode Voltage (V) Coupling
1.4-V PCML 0.82 AC, DC
1.5-V PCML 0.82 AC, DC
2.5-V PCML 0.82 AC
LVDS 0.82 AC, DC (1)
Note to Table 1–2:
(1) DC coupling is supported for LVDS with lower on-chip common mode voltage of 0.82 V.
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The high-speed serial link can be AC- or DC-coupled, depending on the serial protocol implementation. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter DC common mode voltage as shown in Figure 1–12. Receiver OCT and on-chip biasing circuitry automatically restores the common mode voltage. The biasing circuitry is also enabled by enabling OCT. If you disable the OCT, then you must externally terminate and bias the receiver. AC-coupled links are required for PCIe, GbE, Serial RapidIO, SDI, XAUI, SATA, V-by-One and Display Port protocols.
Figure 1–12. AC-Coupled Link with OCT
Physical Medium
Transmitter Receiver
TX V
Physical Medium
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In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at the receiver input buffer as shown in Figure 1–13. The link common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage. When using the receiver OCT and on-chip biasing circuitry in a DC coupled link, you must ensure the transmitter common mode voltage is compatible with the receiver common mode requirements. If you disable the OCT, you must terminate and bias the receiver externally and ensure compatibility between the transmitter and the receiver common mode voltage.
Figure 1–14 shows the receiver input buffer block diagram.
The receiver input buffers support the following features:
Figure 1–13. DC-Coupled Link with OCT
Figure 1–14. Receiver Input Buffer Block Diagram
Transmitter Receiver
TX V
50 or 75 50 or 75
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Programmable equalization—boosts the high-frequency gain of the incoming signal up to 7 dB. This compensates for the low-pass filter effects of the transmission media. The amount of high-frequency gain required depends on the loss characteristics of the physical medium.
Programmable DC gain—provides equal boost to incoming signal across the frequency spectrum with DC gain settings up to 6 dB.
Programmable differential OCT—provides calibrated OCT at 100 or 150 with on-chip receiver common mode voltage at 0.82 V. The common mode voltage is tri- stated when you disable the OCT to use external termination.
Offset cancellation—corrects the analog offset voltages that might exist from process variations between the positive and negative differential signals in the equalizer stage and CDR circuit.
Signal detection—detects if the signal level present at the receiver input buffer is higher than the threshold with a built-in signal threshold detection circuitry. The circuitry has a hysteresis response that filters out any high-frequency ringing caused by ISI effects or high-frequency losses in the transmission medium. Detection is indicated by the assertion of the rx_signaldetect signal. Signal detection is only supported when 8B/10B encoder/decoder block is enabled. When not supported, the rx_signaldetect signal is forced high, bypassing the signal detection function.
1 Disable OCT to use external termination if the link requires a 85 termination, such as when you are interfacing with certain PCIe Gen1 or Gen2 capable devices.
f For specifications on programmable equalization and DC gain settings, refer to the Cyclone IV Device Data Sheet.
February 2015 Altera Corporation Cyclone IV Device Handbook, Volume 2
Clock Data Recovery Each receiver channel has an independent CDR unit to recover the clock from the incoming serial data stream. The high-speed recovered clock is used to clock the deserializer for serial-to-parallel conversion of the received input data, and low-speed recovered clock to clock the receiver PCS blocks. Figure 1–15 illustrates the CDR unit block diagram.
Each CDR unit gets the reference clock from one of the two multipurpose phase-locked loops (PLLs) adjacent to the transceiver block. The CDR works by tracking the incoming data with a phase detector and finding the optimum sampling clock phase from the phase interpolator unit. The CDR operations are controlled by the LTR/LTD controller block, where the CDR may operate in the following states:
Lock-to-reference (LTR) state—phase detector disabled and CDR ignores incoming data
Lock-to-data (LTD) state—phase detector enabled and CDR tracks incoming data to find the optimum sampling clock phase
State transitions are supported with automatic lock mode and manual lock mode.
Automatic Lock Mode Upon receiver power-up and reset cycle, the CDR is put into LTR state. Transition to the LTD state is performed automatically when both of the following conditions are met:
Signal detection circuitry indicates the presence of valid signal levels at the receiver input buffer. This condition is valid for PCI Express (PIPE) mode only. CDR transitions are not dependent on signal detection circuitry in other modes.
The recovered clock is within the configured part per million (ppm) frequency threshold setting with respect to the CDR clocks from multipurpose PLL.
Figure 1–15. CDR Unit Block Diagram
Notes to Figure 1–15:
(1) Optional RX local divider for CDR clocks from multipurpose PLL is only available in each CDR unit for EP4CGX30 (F484 package), EP4CGX50, and EP4CGX75 devices. This block is used with the transceiver dynamic reconfiguration feature. For more information, refer to the Cyclone IV Dynamic Reconfiguration chapter and AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices.
(2) CDR state transition in automatic lock mode is not dependent on rx_signaldetect signal, except when configured in PCI Express (PIPE) mode only.
rx_datain
rx_freqlocked
High-speed recovered clock (for deserializer)
CDR clocks from MPLL
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Actual lock time depends on the transition density of the incoming data and the ppm difference between the receiver input reference clock and the upstream transmitter reference clock.
Transition from the LTD state to the LTR state occurs when either of the following conditions is met:
Signal detection circuitry indicates the absence of valid signal levels at the receiver input buffer. This condition is valid for PCI Express (PIPE) mode only. CDR transitions are not dependent on signal detection circuitry in other modes.
The recovered clock is not within the configured ppm frequency threshold setting with respect to CDR clocks from multipurpose PLLs.
In automatic lock mode, the switch from LTR to LTD states is indicated by the assertion of the rx_freqlocked signal and the switch from LTD to LTR states indicated by the de-assertion of the rx_freqlocked signal.
Manual Lock Mode State transitions are controlled manually by using rx_locktorefclk and rx_locktodata ports. The LTR/LTD controller sets the CDR state depending on the logic level on the rx_locktorefclk and rx_locktodata ports. This mode provides the flexibility to control the CDR for a reduced lock time compared to the automatic lock mode. In automatic lock mode, the LTR/LTD controller relies on the ppm detector and the phase relationship detector to set the CDR in LTR or LTD mode. The ppm detector and phase relationship detector reaction times can be too long for some applications that require faster CDR lock time.
In manual lock mode, the rx_freqlocked signal is asserted when the CDR is in LTD state and de-asserted when CDR is in LTR state. For descriptions of rx_locktorefclk and rx_locktodata port controls, refer to Table 1–27 on page 1–87.
1 If you do not enable the optional rx_locktorefclk and rx_locktodata ports, the Quartus II software automatically configures the LTR/LTD controller in automatic lock mode.
f The recommended transceiver reset sequence varies depending on the CDR lock mode. For more information about the reset sequence recommendations, refer to the Reset Control and Power Down for Cyclone IV GX Devices chapter.
Deserializer The deserializer converts received serial data from the receiver input buffer to parallel 8- or 10-bit data. Serial data is assumed to be received from the LSB to the MSB. The deserializer operates with the high-speed recovered clock from the CDR with the frequency at half of the serial data rate.
February 2015 Altera Corporation Cyclone IV Device Handbook, Volume 2
Word Aligner Figure 1–16 shows the word aligner block diagram. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization. The word aligner supports three operational modes as listed in Table 1–3.
Manual Alignment Mode
In manual alignment mode, the rx_enapatternalign port controls the word aligner with either an 8- or 10-bit data width setting.
The 8-bit word aligner is edge-sensitive to the rx_enapatternalign signal. A rising edge on rx_enapatternalign signal after deassertion of the rx_digitalreset signal triggers the word aligner to look for the word alignment pattern in the received data stream. It updates the word boundary if it finds the word alignment pattern in a new word boundary. Any word alignment pattern received thereafter in a different word boundary causes the word aligner to re-align to the new word boundary only if there is a rising edge in the rx_enapatternalign signal.
The 10-bit word aligner is level-sensitive to the rx_enapatternalign signal. The word aligner looks for the programmed 7-bit or 10-bit word alignment pattern or its complement in the received data stream, if the rx_enapatternalign signal is held high. It updates the word boundary if it finds the word alignment pattern in a new word boundary. If the rx_enapatternalign signal is deasserted, the word aligner maintains the current word boundary even when it receives the word alignment pattern in a new word boundary.
Figure 1–16. Word Aligner Block Diagram
Word Aligner
Bit-Slip Circuitry
rx_syncstatus
rx_patterndetect
Modes PMA-PCS Interface Widths Allowed Word Alignment Pattern Lengths
Manual Alignment 8-bit 16 bits
10-bit 7 or 10 bits
Bit-Slip 8-bit 16 bits
Automatic Synchronization State Machine 10-bit 7 or 10 bits
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After updating the word boundary, word aligner status signals (rx_syncstatus and rx_patterndetect) are driven high for one parallel clock cycle synchronous to the most significant byte of the word alignment pattern. The rx_syncstatus and rx_patterndetect signals have the same latency as the datapath and are forwarded to the FPGA fabric to indicate the word aligner status. Any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle.
Figure 1–17 shows the manual alignment mode word aligner operation in 10-bit data width mode. In this example, a /K28.5/ (10'b0101111100) is specified as the word alignment pattern.
The word aligner aligns to the /K28.5/ alignment pattern (red) in cycle n because the rx_enapatternalign signal is asserted high. The rx_syncstatus signal goes high for one clock cycle indicating alignment to a new word boundary. The rx_patterndetect signal also goes high for one clock cycle to indicate initial word alignment.
At time n + 1, the rx_enapatternalign signal is deasserted to instruct the word aligner to lock the current word boundary.
The alignment pattern is detected again (green) in a new word boundary across cycles n + 2 and n + 3. The word aligner does not align to this new word boundary because the rx_enapatternalign signal is held low.
The /K28.5/ word alignment pattern is detected again (blue) in the current word boundary during cycle n + 5 causing the rx_patterndetect signal to go high for one parallel clock cycle.
1 If the word alignment pattern is known to be unique and does not appear between word boundaries, you can hold the rx_enapatternalign signal constantly high because there is no possibility of false word alignment. If there is a possibility of the word alignment pattern occurring across word boundaries, you must control the rx_enapatternalign signal to lock the word boundary after the desired word alignment is achieved to avoid re-alignment to an incorrect word boundary.
Figure 1–17. Word Aligner in 10-bit Manual Alignment Mode
rx_enapatternalign
rx_clock
rx_patterndetect
rx_syncstatus
n + 5
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Bit-Slip Mode
In bit-slip mode, the rx_bitslip port controls the word aligner operation. At every rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. When the received data after bit-slipping matches the programmed word alignment pattern, the rx_patterndetect signal is driven high for one parallel clock cycle.
1 You can implement a bit-slip controller in the user logic that monitors either the rx_patterndetect signal or the receiver data output (rx_dataout), and controls the rx_bitslip port to achieve word alignment.
Figure 1–18 shows an example of the word aligner configured in bit-slip mode. For this example, consider that 8'b11110000 is received back-to-back and 16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively, which matches the specified 16-bit alignment pattern 16'b0000111100011110. This results in the assertion of the rx_patterndetect signal.
Automatic Synchronization State Machine Mode
In automatic synchronization state machine mode, the word aligner achieves synchronization after receiving a specific number of synchronization code groups, and falls out of synchronization after receiving a specific number of erroneous code groups. This mode provides hysteresis during link synchronization, which is required by protocols such as PCIe, GbE, XAUI, and Serial RapidIO.
1 This mode is only supported using the 8B/10B encoded data with 10-bit input to the word aligner.
Figure 1–18. Word Aligner Configured in Bit-Slip Mode
01111000
n
11110000
rx_bitslip
rx_patterndetect
11110000
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
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Table 1–4 lists the synchronization state machine parameters for the word aligner in this mode.
After deassertion of the rx_digitalreset signal in automatic synchronization state machine mode, the word aligner starts looking for the synchronization code groups, word alignment pattern or its complement in the received data stream. When the programmed number of valid synchronization code groups or ordered sets are received, the rx_syncstatus signal is driven high to indicate that synchronization is acquired. The rx_syncstatus signal is constantly driven high until the programmed number of erroneous code groups are received without receiving intermediate good groups; after which the rx_syncstatus signal is driven low. The word aligner indicates loss of synchronization (rx_syncstatus signal remains low) until the programmed number of valid synchronization code groups are received again.
In addition to restoring word boundaries, the word aligner supports the following features:
Programmable run length violation detection—detects consecutive 1s or 0s in the data stream, and asserts run length violation signal (rx_rlv) when a preset run length threshold (maximum number of consecutive 1s or 0s) is detected. The rx_rlv signal in each channel is clocked by its parallel recovered clock and is asserted for a minimum of two recovered clock cycles to ensure that the FPGA fabric clock can latch the rx_rlv signal reliably because the FPGA fabric clock might have phase differences, ppm differences (in asynchronous systems), or both, with the recovered clock. Table 1–5 lists the run length violation circuit detection capabilities.
Table 1–4. Synchronization State Machine Parameters
Parameter Allowed Values
Number of erroneous code groups received to lose synchronization 1–64
Number of continuous good code groups received to reduce the error count by one 1–256
Table 1–5. Run Length Violation Circuit Detection Capabilities
Supported Data Width Detector Range Increment Step
SettingsMinimum Maximum
8-bit 4 128 4
10-bit 5 160 5
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Receiver polarity inversion—corrects accidental swapped positive and negative signals from the serial differential link during board layout. This feature works by inverting the polarity of every bit of the input data word to the word aligner, which has the same effect as swapping the positive and negative signals of the differential link. Inversion is dynamically controlled using rx_invpolarity port. Figure 1–19 shows the receiver polarity inversion feature.
The generic receiver polarity inversion feature is different from the PCI Express (PIPE) 8B/10B polarity inversion feature. The generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner and is not available in PCI Express (PIPE) mode. The PCI Express (PIPE) 8B/10B polarity inversion feature inverts the polarity of the data bits at the input of the 8B/10B decoder and is available only in PCI Express (PIPE) mode.
1 The rx_invpolarity signal is dynamic and might cause initial disparity errors in an 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors.
Receiver bit reversal—by default, the Cyclone IV GX receiver assumes LSB to MSB transmission. If the link transmission order is MSB to LSB, the receiver forwards the incorrect reverse bit-ordered version of the parallel data to the FPGA fabric on the rx_dataout port. The receiver bit reversal feature is available to correct this situation. This feature is static in manual alignment and automatic synchronization state machine mode. In bit-slip mode, you can dynamically enable the receiver bit reversal using the rx_revbitorderwa port. When enabled,
Figure 1–19. Receiver Polarity Inversion
Input to word alignerOutput from deserializer
0
1
1
1
0
0
1
0
0
0
MSB
LSB
1
0
0
0
1
1
0
1
1
1
MSB
LSB
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the 8-bit or 10-bit data D[7..0] or D[9..0] at the output of the word aligner is rewired to D[0..7] or D[0..9] respectively. Figure 1–20 shows the receiver bit reversal feature.
1 When using the receiver bit reversal feature to receive MSB-to-LSB transmission, reversal of the word alignment pattern is required.
Receiver bit-slip indicator—provides the number of bits slipped in the word aligner for synchronization with rx_bitslipboundaryselectout signal. For usage details, refer to “Receive Bit-Slip Indication” on page 1–76.
Deskew FIFO This module is only available when used for the XAUI protocol and is used to align all four channels to meet the maximum skew requirement of 40 UI (12.8 ns) as seen at the receiver of the four lanes. The deskew operation is compliant to the PCS deskew state machine diagram specified in clause 48 of the IEEE P802.3ae specification.
The deskew circuitry consists of a 16-word deep deskew FIFO in each of the four channels, and control logics in the central control unit of the transceiver block that controls the deskew FIFO write and read operations in each channel.
For details about the deskew FIFO operations for channel deskewing, refer to “XAUI Mode” on page 1–67.
Figure 1–20. Receiver Bit Reversal (1)
Note to Figure 1–20:
(1) The rx_revbitordwa port is dynamic and is only available when the word aligner is configured in bit-slip mode.
Output of word aligner before RX bit reversal
Output of word aligner after RX bit reversal
rx_revbitordwa (1) = HIGH
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
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Rate Match FIFO In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. Frequency differences in the order of a few hundred ppm can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain. Figure 1–21 shows the rate match FIFO block diagram.
The rate match FIFO compensates for small clock frequency differences of up to ±300 ppm (600 ppm total) between the upstream transmitter and the local receiver clocks by performing the following functions:
Insert skip symbols when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency
Delete skip symbols when the local receiver reference clock frequency is less than the upstream transmitter reference clock frequency
The 20-word deep rate match FIFO and logics control insertion and deletion of skip symbols, depending on the ppm difference. The operation begins after the word aligner synchronization status (rx_syncstatus) is asserted.
1 Rate match FIFO is only supported with 8B/10B encoded data and the word aligner in automatic synchronization state machine mode.
8B/10B Decoder The 8B/10B decoder receives 10-bit data and decodes it into an 8-bit data and a 1-bit control identifier. The decoder is compliant with Clause 36 of the IEEE 802.3 specification.
Figure 1–22 shows the 8B/10B decoder block diagram.
Figure 1–21. Rate Match FIFO Block Diagram
Rate Match FIFO
8B/10B Decoder
10
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Byte Deserializer The byte deserializer halves the FPGA fabric-transceiver interface frequency while doubles the parallel data width to the FPGA fabric.
For example, when operating an EP4CGX150 receiver channel at 3.125 Gbps with deserialization factor of 10, the receiver PCS datapath runs at 312.5 MHz. The byte deserializer converts the 10-bit data at 312.5 MHz into 20-bit data at 156.25 MHz before forwarding the data to the FPGA fabric.
Byte Ordering In the 16- or 20-bit FPGA fabric-transceiver interface, the byte deserializer receives one data byte (8 or 10 bits) and deserializes it into two data bytes (16 or 20 bits). Depending on when the receiver PCS logic comes out of reset, the byte ordering at the output of the byte deserializer may not match the original byte ordering of the transmitted data. The byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset.
Figure 1–23 shows a scenario where the most significant byte and the least significant byte of the two-byte transmitter data appears straddled across two word boundaries after the data is deserialized at the receiver.
The byte ordering block restores the proper byte ordering by performing the following actions:
Look for the user-programmed byte ordering pattern in the byte-deserialized data
Inserts a user-programmed pad byte if the user-programmed byte ordering pattern is found in the most significant byte position
You must select a byte ordering pattern that you know appears at the least significant byte position of the parallel transmitter data.
The byte ordering block is supported in the following receiver configurations:
16-bit FPGA fabric-transceiver interface, 8B/10B disabled, and the word aligner in manual alignment mode. Program a custom 8-bit byte ordering pattern and 8-bit pad byte.
16-bit FPGA fabric-transceiver interface, 8B/10B enabled, and the word aligner in automatic synchronization state machine mode. Program a custom 9-bit byte ordering pattern and 9-bit pad byte. The MSB of the 9-bit byte ordering pattern and pad byte represents the control identifier of the 8B/10B decoded data.
Figure 1–23. Example of Byte Deserializer at the Receiver
Byte Serializer
Byte Deserializer
Transmitter Receiver
D1
D1
xx
D3
D2
D5
D4
xx
D6
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The byte ordering block operates in either word-alignment-based byte ordering or user-controlled byte ordering modes.
In word-alignment-based byte ordering mode, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data and restores the order if necessary when it detects a rising edge on the rx_syncstatus signal. Whenever the byte ordering pattern is found, the rx_byteorderalignstatus signal is asserted regardless if the pad byte insertion is necessary. If the byte ordering block detects another rising edge on the rx_syncstatus signal from the word aligner, it deasserts the rx_byteorderalignstatus signal and repeats the byte ordering operation.
In user-controlled byte ordering mode, the byte ordering operation is user-triggered using rx_enabyteord port. A rising edge on rx_enabyteord port triggers the byte ordering block to start looking for the byte ordering pattern in the byte-deserialized data and restores the order if necessary. When the byte ordering pattern is found, the rx_byteorderalignstatus signal is asserted regardless if a pad byte insertion is necessary.
RX Phase Compensation FIFO The RX phase compensation FIFO compensates for the phase difference between the parallel receiver clock and the FPGA fabric interface clock, when interfacing the receiver channel to the FPGA fabric (directly or through the PIPE and PCIe hard IP blocks). The FIFO is four words deep, with latency between two to three parallel clock cycles.
Figure 1–24 shows the RX phase compensation FIFO block diagram.
1 The FIFO can operate in registered mode, contributing to only one parallel clock cycle of latency in the Deterministic Latency functional mode. For more information, refer to “Deterministic Latency Mode” on page 1–73. For more information about FIFO clocking, refer to “FPGA Fabric-Transceiver Interface Clocking” on page 1–43.
Miscellaneous Receiver PCS Feature The receiver PCS supports the following additional feature:
Output bit-flip—reverses the bit order at a byte level at the output of the receiver phase compensation FIFO. For example, if the 16-bit parallel receiver data at the output of the receiver phase compensation FIFO is '10111100 10101101' (16'hBCAD), enabling this option reverses the data on rx_dataout port to '00111101 10110101' (16'h3DB5).
Figure 1–24. RX Phase Compensation FIFO Block Diagram
Note to Figure 1–24:
(1) Parameter x refers to the transceiver channel width, where 8, 10, 16, or 20 bits are supported.
RX Phase Compensation
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Transceiver Clocking Architecture The multipurpose PLLs and general-purpose PLLs located on the left side of the device generate the clocks required for the transceiver operation. The following sections describe the Cyclone IV GX transceiver clocking architecture:
“Input Reference Clocking” on page 1–27
“Transceiver Channel Datapath Clocking” on page 1–29
“FPGA Fabric-Transceiver Interface Clocking” on page 1–43
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Input Reference Clocking When used for transceiver, the left PLLs synthesize the input reference clock to generate the required clocks for the transceiver channels. Figure 1–25 and Figure 1–26 show the sources of input reference clocks for PLLs used in the transceiver operation.
1 Clock output from PLLs in the FPGA core cannot feed into PLLs used by the transceiver as input reference clock.
Figure 1–25. PLL Input Reference Clocks in Transceiver Operation for F324 and Smaller Packages (1), (2)
Notes to Figure 1–25:
(1) The REFCLK0 and REFCLK1 pins are dual-purpose CLK, REFCLK, or DIFFCLK pins that reside in banks 3A and 8A respectively.
(2) Using any clock input pins other than the designated REFCLK pins as shown here to drive the MPLLs may have reduced jitter performance.
Transceiver Block
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The input reference clocks reside in banks 3A, 3B, 8A, and 8B have dedicated VCC_CLKIN3A, VCC_CLKIN3B, VCC_CLKIN8A, and VCC_CLKIN8B power supplies separately in their respective I/O banks to avoid the different power level requirements in the same bank for general purpose I/Os (GPIOs). Table 1–6 lists the supported I/O standard for the REFCLK pins.
Figure 1–26. PLL Input Reference Clocks in Transceiver Operation for F484 and Larger Packages (1), (2), (3)
Notes to Figure 1–26:
(1) The REFCLK2 and REFCLK3 pins are dual-purpose CLKIO, REFCLK, or DIFFCLK pins that reside in banks 3A and 8A respectively.
(2) The REFCLK[1..0] and REFCLK[5..4] pins are dual-purpose differential REFCLK or DIFFCLK pins that reside in banks 3B and 8B respectively. These clock input pins do not have access to the clock control blocks and GCLK networks. For more details, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter.
(3) Using any clock input pins other than the designated REFCLK pins as shown here to drive the MPLLs and GPLLs may have reduced jitter performance.
Transceiver Block
Table 1–6. REFCLK I/O Standard Support
I/O Standard HSSI Protocol Coupling Terminatio
n
Input Output Column I/O Row I/O Supported Banks
LVDS ALL Differential AC (Needs
off-chip resistor to
restore VCM)
Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
LVPECL ALL Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
1.2 V, 1.5 V, 3.3 V PCML
ALL Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
ALL Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
ALL Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
HCSL PCIe Differential DC Off-chip 2.5 V Not Supported Yes No 3A, 3B, 8A, 8B
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Figure 1–27 shows an example of the termination scheme for AC-coupled connections for REFCLK pins.
Figure 1–28 shows an example termination scheme for the REFCLK pin when configured as a HCSL input.
Transceiver Channel Datapath Clocking Channel datapath clocking varies with channel configuration options and PCS configurations. This section describes the clock distribution from the left PLLs for transceiver channels and the datapath clocking in various supported configurations.
Table 1–7 lists the clocks generated by the PLLs for transceiver datapath.
Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock
Note to Figure 1–27:
(1) For more information about the VICM value, refer to the Cyclone IV Device Datasheet chapter.
Figure 1–28. Termination Scheme for a Reference Clock When Configured as HCSL (1)
Notes to Figure 1–28:
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe specification.
(2) Select values as recommended by the PCIe clock source vendor.
Z0 = 50 Ω
Z0 = 50 Ω
50 Ω
Clock Usage
High-speed clock Transmitter serializer block in PMA
Low-speed clock Transmitter PCS blocks
Receiver PCS blocks when rate match FIFO enabled
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The CDR unit in each receiver channel gets the CDR clocks from one of the two multipurpose PLLs directly adjacent to the transceiver block. The CDR clocks distribution network is segmented by bidirectional tri-state buffers as shown in Figure 1–29 and Figure 1–30. This requires the CDR clocks from either one of the two multipurpose PLLs to drive a number of contiguous segmented paths to reach the intended receiver channel. Interleaving the CDR clocks from the two multipurpose PLLs is not supported.
For example, based on Figure 1–29, a combination of MPLL_1 driving receiver channels 0, 1, and 3, while MPLL_2 driving receiver channel 2 is not supported. In this case, only one multipurpose PLL can be used for the receiver channels.
Figure 1–29. CDR Clocking for Transceiver Channels in F324 and Smaller Packages
Note to Figure 1–29:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
Figure 1–30. CDR Clocking for Transceiver Channels in F484 and Larger Packages
Transceiver Block
Transceiver Block
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1 In any configuration, a receiver channel cannot source CDR clocks from other PLLs beyond the two multipurpose PLLs directly adjacent to transceiver block where the channel resides.
The Cyclone IV GX transceivers support non-bonded (×1) and bonded (×2 and ×4) channel configurations. The two configurations differ in regards to clocking and phase compensation FIFO control. Bonded configuration provides a relatively lower channel-to-channel skew between the bonded channels than in non-bonded configuration. Table 1–8 lists the supported conditions in non-bonded and bonded channel configurations.
Non-Bonded Channel Configuration In non-bonded channel configuration, the high- and low-speed clocks for each channel are sourced independently. The phase compensation FIFOs in each channel has its own pointers and control logic. When implementing multi-channel serial interface in non-bonded channel configuration, the clock skew and unequal latency results in larger channel-to-channel skew.
1 Altera recommends using bonded channel configuration (×2 or ×4) when implementing multi-channel serial interface for a lower channel-to-channel skew.
In a transceiver block, the high- and low-speed clocks for each channel are distributed primarily from one of the two multipurpose PLLs directly adjacent to the block. Transceiver channels for devices in F484 and larger packages support additional clocking flexibility. In these packages, some channels support high-speed and low- speed clock distribution from PLLs beyond the two multipurpose PLLs directly adjacent to the block.
Table 1–8. Supported Conditions in Non-Bonded and Bonded Channel Configurations
Channel Configuration Description Supported Channel
Operation Mode
Non-bonded (×1)
Low-speed clock in each channel is sourced independently
Phase compensation FIFO in each channel has its own pointers and control logic
Transmitter Only
Receiver Only
Bonded (×2 and ×4)
Low-speed clock in each bonded channel is sourced from a common bonded clock path for lower channel-to-channel skew
Phase compensation FIFOs in bonded channels share common pointers and control logic for equal latency through the FIFOs in all bonded channels
×2 bonded configuration is supported with channel 0 and channel 1 in a transceiver block
×4 bonded configuration is supported with all four channels in a transceiver block
Transmitter Only
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Table 1–9 lists the high- and low-speed clock sources for each channel.
Table 1–9. High- and Low-Speed Clock Sources for Each Channel in Non-Bonded Channel Configuration
Package Transceiver Block Transceiver Channel High- and Low-Speed Clocks Sources
Option 1 Option 2
F484 and larger
GXBL1 (1) Channels 0, 1 MPLL_7/MPLL_6 MPLL_8
Channels 2, 3 MPLL_7 MPLL_8/GPLL_2
Note to Table 1–9:
(1) MPLL_7 and GXBL1 are not applicable for transceivers in F484 package
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Figure 1–31 and Figure 1–32 show the high- and low-speed clock distribution for transceivers in F324 and smaller packages, and in F484 and larger packages in non-bonded channel configuration.
Figure 1–31. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F324 and Smaller Packages
Notes to Figure 1–31:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages. (2) High-speed clock. (3) Low-speed clock.
Transceiver Block
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The transceiver datapath clocking varies in non-bonded channel configuration depending on the PCS configuration.
Figure 1–33 shows the datapath clocking in transmitter only operation. In this mode, each channel selects the high- and low-speed clock from one of the supported PLLs. The high-speed clock feeds to the serializer for parallel to serial operation. The low-speed clock feeds to the following blocks in the transmitter PCS:
8B/10B encoder
read clock of the TX phase compensation FIFO
Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484 and Larger Packages
Notes to Figure 1–32:
(1) High-speed clock. (2) Low-speed clock. (3) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
Table 1–9.
Transceiver Block
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When the byte serializer is enabled, the low-speed clock frequency is halved before feeding into the read clock of TX phase compensation FIFO. The low-speed clock is available in the FPGA fabric as tx_clkout port, which can be used in the FPGA fabric to send transmitter data and control signals.
Figure 1–34 shows the datapath clocking in receiver only operation. In this mode, the receiver PCS supports configuration without the rate match FIFO. The CDR unit in the channel recovers the clock from the received serial data and generates the high- speed recovered clock for the deserializer, and low-speed recovered clock for forwarding to the receiver PCS. The low-speed recovered clock feeds to the following blocks in the receiver PCS:
word aligner
8B/10B decoder
byte ordering
write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the low-speed recovered clock frequency is halved before feeding into the write clock of the RX phase compensation FIFO. The low-speed recovered clock is available in the FPGA fabric as rx_clkout port, which can be used in the FPGA fabric to capture receiver data and status signals.
When the transceiver is configured for transmitter and receiver operation in non-bonded channel configuration, the receiver PCS supports configuration with and without the rate match FIFO. The difference is only at the receiver datapath clocking. The transmitter datapath clocking is identical to transmitter only operation mode as shown in Figure 1–33.
Figure 1–33. Transmitter Only Datapath Clocking in Non-Bonded Channel Configuration
Byte Serializer 8B/10B Encoder
Serializer
low-speed clock
tx_clkout /2
Figure 1–34. Receiver Only Datapath Clocking without Rate Match FIFO in Non-Bonded Channel Configuration
Note to Figure 1–34:
(1) High-speed recovered clock.
rx_dataout
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Figure 1–35 shows the datapath clocking in the transmitter and receiver operation mode with the rate match FIFO. The receiver datapath clocking in configuration without the rate match FIFO is identical to Figure 1–34.
In configuration with the rate match FIFO, the CDR unit in the receiver channel recovers the clock from received serial data and generates the high-speed recovered clock for the deserializer, and low-speed recovered clock for forwarding to the receiver PCS. The low-speed recovered clock feeds to the following blocks in the receiver PCS:
word aligner
write clock of rate match FIFO
The low-speed clock that is used in the transmitter PCS datapath feeds the following blocks in the receiver PCS:
read clock of rate match FIFO
8B/10B decoder
byte ordering
write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the low-speed clock frequency is halved before feeding into the write clock of RX phase compensation FIFO. The low-speed clock is available in the FPGA fabric as tx_clkout port, which can be used in the FPGA fabric to send transmitter data and control signals, and capture receiver data and status signals.
Figure 1–35. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Non-Bonded Channel Configuration
Notes to Figure 1–35:
(1) Low-speed recovered clock. (2) High-speed recovered clock.
(1)
Serializer
low-speed clocktx _c
rx _d
at ao
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Bonded Channel Configuration In bonded channel configuration, the low-speed clock for the bonded channels share a common bonded clock path that reduces clock skew between the bonded channels. The phase compensation FIFOs in bonded channels share a set of pointers and control logic that results in equal FIFO latency between the bonded channels. These features collectively result in lower channel-to-channel skew when implementing multi-channel serial interface in bonded channel configuration.
In a transceiver block, the high-speed clock for each bonded channels is distributed independently from one of the two multipurpose PLLs directly adjacent to the block. The low-speed clock for bonded channels is distributed from a common bonded clock path that selects from one of the two multipurpose PLLs directly adjacent to the block. Transceiver channels for devices in F484 and larger packages support additional clocking flexibility for ×2 bonded channels. In these packages, the ×2 bonded channels support high-speed and low-speed bonded clock distribution from PLLs beyond the two multipurpose PLLs directly adjacent to the block. Table 1–10 lists the high- and low-speed clock sources for the bonded channels.
1 When implementing ×2 bonded channel configuration in a transceiver block, remaining channels 2 and 3 are available to implement other non-bonded channel configuration.
Table 1–10. High- and Low-Speed Clock Sources for Bonded Channels in Bonded Channel Configuration
Package Transceiver Block Bonded Channels
High- and Low-Speed Clocks Source
Option 1 Option 2
F324 and smaller GXBL0 ×2 in channels 0, 1 ×4 in all channels MPLL_1 MPLL_2
F484 and larger
GPLL_1 MPLL_6
GXBL1 (1) ×2 in channels 0, 1 MPLL_7/
MPLL_6 MPLL_8
Note to Table 1–10:
(1) GXBL1 is not available for transceivers in F484 package.
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Figure 1–36 and Figure 1–37 show the independent high-speed clock and bonded low-speed clock distributions for transceivers in F324 and smaller packages, and in F484 and larger packages in bonded (×2 and ×4) channel configuration.
Figure 1–36. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in F324 and Smaller Packages.
Notes to Figure 1–36:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages. (2) High-speed clock. (3) Low-speed clock. (4) Bonded common low-speed clock path.
Transceiver Block
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The channel datapath clocking is similar between bonded channels in ×2 and ×4 configurations.
Figure 1–38 shows the datapath clocking in Transmitter Only operation for ×2 and ×4 bonded configurations. In these configurations, each bonded channel selects the high-speed clock from one the supported PLLs. The high-speed clock in each bonded channel feeds the respective serializer for parallel to serial operation. The common bonded low-speed clock feeds to each bonded channel that is used for the following blocks in each transmitter PCS channel:
8B/10B encoder
read clock of TX phase compensation FIFO
Figure 1–37. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in F484 and Larger Packages
Notes to Figure 1–37:
(1) High-speed clock. (2) Low-speed clock. (3) Bonded common low-speed clock path. (4) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to Table 1–10.
(3)
Transceiver Block
TX PMA
TX PMA
TX PMA
TX PMA
Transceiver Block
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When the byte serializer is enabled, the common bonded low-speed clock frequency is halved before feeding to the read clock of TX phase compensation FIFO. The common bonded low-speed clock is available in FPGA fabric as coreclkout port, which can be used in FPGA fabric to send transmitter data and control signals to the bonded channels.
1 Bonded channel configuration is not available for Receiver Only channel operation because each of the channels are individually clocked by its recovered clock.
Figure 1–38. Transmitter Only Datapath Clocking in Bonded Channel Configuration
Byte Serializer 8B/10B Encoder
Serializer
tx _d
at ao
ut [3
tx_coreclk[3]
Serializer Tx Phase
/2
/2
Serializer Tx Phase
/2
Serializer Tx Phase
/2
/2
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For Transmitter and Receiver operation in bonded channel configuration, the receiver PCS supports configuration with rate match FIFO, and configuration without rate match FIFO. Figure 1–39 shows the datapath clocking in Transmitter and Receiver operation with rate match FIFO in ×2 and ×4 bonded channel configurations. For Transmitter and Receiver operation in bonded channel configuration without rate match FIFO, the datapath clocking is identical to Figure 1–38 for the bonded transmitter channels, and Figure 1–34 on page 1–35 for the receiver channels.
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Figure 1–39. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Bonded Channel Configuration
Notes to Figure 1–39:
(1) Low-speed recovered clock. (2) High-speed recovered clock.
In 2 Bonded Channel Configuration+
(1)
Serializer
low-speed clock
tx _c
or ec
lk [3
rx _d
at ai
n[ 3]
Deserial- izer
Serializer Tx Phase
tx _c
or ec
lk [2
rx _d
at ai
n[ 2]
Deserial- izer
Serializer Tx Phase
tx _c
or ec
lk [1
rx _d
at ai
n[ 1]
Deserial- izer
Serializer Tx Phase
tx _c
or ec
lk [0
rx _d
at ai
n[ 0]
Deserial- izer
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In configuration with rate match FIFO, the transmitter datapath clocking is identical to Transmitter Only operation as shown in Figure 1–38. In each bonded receiver channel, the CDR unit recovers the clock from serial received data and generates the high- and low-speed recovered clock for each bonded channel. The high-speed recovered clock feeds the channel's deserializer, and low-speed recovered clock is forwarded to receiver PCS. The individual low-speed recovered clock feeds to the following blocks in the receiver PCS:
word aligner
write clock of rate match FIFO
The common bonded low-speed clock that is used in all bonded transmitter PCS datapaths feeds the following blocks in each bonded receiver PCS:
read clock of rate match FIFO
8B/10B decoder
byte ordering
write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the common bonded low-speed clock frequency is halved before feeding to the write clock of RX phase compensation FIFO. The common bonded low-speed clock is available in FPGA fabric as coreclkout port, which can be used in FPGA fabric to send transmitter data and control signals, and capture receiver data and status signals from the bonded channels.
FPGA Fabric-Transceiver Interface Clocking The FPGA fabric-transceiver interface clocks consists of clock signals from the FPGA fabric to the transceiver blocks, and from the transceiver blocks to the FPGA fabric. These clock resources use the global clock networks (GCLK) in the FPGA core.
f For information about the GCLK resources in the Cyclone IV GX devices, refer to Clock Networks and PLLs in Cyclone IV Devices chapter.
Table 1–11 lists the FPGA fabric-transceiver interface clocks.
Table 1–11. FPGA Fabric-Transceiver Interface Clocks (Part 1 of 2)
Clock Name Clock Description Interface Direction
tx_clkout Phase compensation FIFO clock Transceiver to FPGA fabric
rx_clkout Phase compensation FIFO clock Transceiver to FPGA fabric
coreclkout Phase compensation FIFO clock Transceiver to FPGA fabric
fixed_clk 125MHz receiver detect clock in PIPE mode FPGA fabric to transceiver
reconfig_clk (1), (2) Transceiver dynamic reconfiguration and offset cancellation clock FPGA fabric to transceiver
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In the transmitter datapath, TX phase compensation FIFO forms the FPGA fabric-transmitter interface. Data and control signals for the transmitter are clocked with the FIFO write clock. The FIFO write clock supports automatic clock selection by the Quartus II software (depending on channel configuration), or user-specified clock from tx_coreclk port. Table 1–12 details the automatic TX phase compensation FIFO write clock selection by the Quartus II software.
1 The Quartus II software assumes automatic clock selection for TX phase compensation FIFO write clock if you do not enable the tx_coreclk port.
When using user-specified clock option, ensure that the clock feeding tx_coreclk port has 0 ppm difference with the TX phase compensation FIFO read clock.
In the receiver datapath, RX phase compensation FIFO forms the receiver-FPGA fabric interface. Data and status signals from the receiver are clocked with the FIFO read clock. The FIFO read clock supports automatic clock selection by the Quartus II software (depending on channel configuration), or user-specified clock from rx_coreclk port. Table 1–13 details the automatic RX phase compensation FIFO read clock selection by the Quartus II software.
1 The Quartus II software assumes automatic clock selection for RX phase compensation FIFO read clock if you do not enable the rx_coreclk port.
cal_blk_clk (2) Transceiver calibration block clock FPGA fabric to transceiver
Notes to Table 1–11:
(1) Offset cancellation process that is executed after power cycle requires reconfig_clk clock. The reconfig_clk must be driven with a free-running clock and not derived from the transceiver blocks.
(2) For the supported clock frequency range, refer to the Cyclone IV Device Data Sheet.
Table 1–11. FPGA Fabric-Transceiver Interface Clocks (Part 2 of 2)
Clock Name Clock Description Interface Direction
Table 1–12. Automatic TX Phase Compensation FIFO Write Clock Selection
Channel Configuration Quartus II Selection
Non-bonded tx_clkout clock feeds the FIFO write clock. tx_clkout is forwarded through the transmitter channel from low-speed clock, which also feeds the FIFO read clock.
Bonded coreclkout clock feeds the FIFO write clock for the bonded channels. coreclkout clock is the common bonded low-speed clock, which also feeds the FIFO read clock in the bonded channels.
Table 1–13. Automatic RX Phase Compensation FIFO Read Clock Selection (Part 1 of 2)
Channel Configuration Quartus II Selection
Non-bonded
With rate match FIFO (1) tx_clkout clock feeds the FIFO read clock. tx_clkout is forwarded through the receiver channel from low-speed clock, which also feeds the FIFO write clock and transmitter PCS.
Without rate match FIFO rx_clkout clock feeds the FIFO read clock. rx_clkout is forwarded through the receiver channel from low-speed recovered clock, which also feeds the FIFO write clock.
When using user-specified clock option, ensure that the clock feeding rx_coreclk port has 0 ppm difference with the RX phase compensation FIFO write clock.
Calibration Block This block calibrates the OCT resistors and the analog portions of the transceiver blocks to ensure that the functionality is independent of process, voltage, and temperature (PVT) variations.
Figure 1–40 shows the location of the calibration block and how it is connected to the transceiver blocks.
Bonded
With rate match FIFO (1) coreclkout clock feeds the FIFO read clock for the bonded channels. coreclkout clock is the common bonded low-speed clock, which also feeds the FIFO read clock and transmitter PCS in the bonded channels.
Without rate match FIFO rx_clkout clock feeds the FIFO read clock. rx_clkout is forwarded through the receiver channel from low-speed recovered clock, which also feeds the FIFO write clock.
Note to Table 1–13:
(1) Configuration with rate match FIFO is supported in transmitter and receiver operation.
Table 1–13. Automatic RX Phase Compensation FIFO Read Clock Selection (Part 2 of 2)
Channel Configuration Quartus II Selection
Figure 1–40. Transceiver Calibration Blocks Location and Connection
Note to Figure 1–40:
(1) Transceiver block GXBL1 is only available for devices in F484 and larger packages.
GXBL1 (1)
Cyclone IV GX Device
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The calibration block internally generates a constant internal reference voltage, independent of PVT variations and uses this voltage and the external reference resistor on the RREF pin to generate constant reference currents. The OCT calibration circuit calibrates the OCT resistors present in the transceiver channels. Figure 1–41 shows the calibration block diagram.
PCI-Express Hard IP Block Figure 1–42 shows the block diagram of the PCIe hard IP block implementing the PHY MAC, Data Link Layer, and Transaction Layer for PCIe interfaces. The PIPE interface is used as the interface between the transceiver and the hard IP block.
Figure 1–41. Input Signals to the Calibration Blocks (1)
Notes to Figure 1–41:
(1) All transceiver channels use the same calibration block clock and power down signals. (2) Connect a 2 k (tolerance max ± 1%) external resistor to the RREF pin to ground. The RREF resistor connection in
the board must be free from any external noise. (3) Supports up to 125 MHz clock frequency. Use either dedicated global clock or divide-down logic from the FPGA fabric
to generate a slow clock on the local clock routing. (4) The calibration block restarts the calibration process following deassertion of the cal_blk_powerdown signal.
RREF pin (2)
Figure 1–42. PCI Express Hard IP High-Level Block Diagram
Clock & Reset Selection
PCIe Hard IP
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The hard IP block supports 1, 2, or 4 initial lane configurations with a maximum payload of 256 bytes at Gen1 frequency. The application interface is 64 bits with a data width of 16 bits per channel running at up to 125 MHz. As a hard macro and a verified block, it uses very few FPGA resources, while significantly reducing design risk and the time required to achieve timing closure. It is compliant with the PCI Express Base Specification 1.1. You do not have to pay a licensing fee to use this module. Configuring the hard IP block requires using the PCI Express Compiler.
f For more information about the hard IP block, refer to the PCI Express Compiler User Guide.
Figure 1–43 shows the lane placement requirements when implementing PCIe with hard IP block.
Transceiver Functional Modes The Cyclone IV GX transceiver supports the functional modes as listed in Table 1–14 for protocol implementation.
Figure 1–43. PCIe with Hard IP Block Lane Placement Requirements (1)
Note to Figure 1–43:
(1) Applicable for PCIe ×1, ×2, and ×4 implementations with hard IP blocks only.
Channel 3
Channel 2
Channel 1
Channel 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe hard IP
Transceiver Block GXBL0
Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 1 of 2)
Functional Mode Protocol Key Feature Reference
Basic Proprietary, SATA, V- by-One, Display Port
Low latency PCS, transmitter in electrical idle, signal detect at receiver, wider spread asynchronous SSC
“Basic Mode” on page 1–48
PCI Express (PIPE)
PIPE ports, receiver detect, transmitter in electrical idle, electrical idle inference, signal detect at receiver, fast recovery, protocol-compliant word aligner and rate match FIFO, synchronous SSC
“PCI Express (PIPE) Mode” on page 1–52
GIGE GbE Running disparity preservation, protocol-compliant word aligner, recovered clock port for applications such as Synchronous Ethernet
“GIGE Mode” on page 1–59
Serial RapidIO SRIO Protocol-compliant word aligner “Serial RapidIO Mode” on page 1–64
XAUI XAUI Deskew FIFO, protocol-compliant word aligner and rate match FIFO
“XAUI Mode” on page 1–67
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Basic Mode The Cyclone IV GX transceiver channel datapath is highly flexible in Basic mode to implement proprietary protocols. SATA, V-by-One, and Display Port protocol implementations in Cyclone IV GX transceiver are supported with Basic mode. Figure 1–44 shows the transceiver channel datapath supported in Basic mode.
Deterministic Latency
Proprietary, CPRI, OBSAI
TX PLL phase frequency detector (PFD) feedback, registered mode FIFO, TX bit-slip control
“Deterministic Latency Mode” on page 1–73
SDI SDI High-speed SERDES, CDR “SDI Mode” on page 1–76
Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 2 of 2)
Functional Mode Protocol Key Feature Reference
Figure 1–44. Transceiver Channel Datapath in Basic Mode
Byte Serializer 8B/10B Encoder
Serializer
rx _
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Figure 1–45 and Figure 1–46 show the supported transceiver configurations in Basic mode with the 8-bit and 10-bit PMA-PCS interface width respectively.
Figure 1–45. Supported Transceiver Configurations in Basic Mode with the 8-bit PMA-PCS Interface Width
Functional Mode
Channel Bonding
Low-Latency PCS
8-Bit
×1, ×2, ×4
Disabled
Disabled
Data Rate (Gbps)
75- 125 75-
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Rate Match FIFO Operation in Basic Mode In Basic mode, the rate match FIFO performs the following operations:
Deletes a maximum of four skip patterns from a cluster, if there is one skip pattern left in the cluster after deletion
Insert a maximum of four skip patterns in a cluster, if there are less than five skip patterns in the cluster after deletion
Automatically deletes the data byte that causes the FIFO to go full and asserts the rx_rmfifofull flag synchronous to the subsequent data byte
Automatically inserts /K30.7/ (9’h1FE) after the data byte that causes the FIFO to go empty and asserts the rx-fifoempty flag synchronous to the inserted /K30.7/ (9’h1FE)
Additional Options in Basic Mode In Basic mode, the transceiver supports the following additional options:
low-latency PCS operation
Figure 1–46. Transceiver Configurations in Basic Mode with a 10-Bit Wide PMA-to-PCS Interface
Functional Mode
Channel Bonding
Low-Latency PCS
FPGA Fabric-to- Transceiver Interface Fredquency (MHz)
Disabled Enabled
×1, ×2, ×4
Disabled Enabled
0.6- 1.25 0.6-
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transmitter in electrical idle
Low-Latency PCS Operation
When configured in low-latency PCS operation, the following blocks in the transceiver PCS are bypassed, resulting in a lower latency PCS datapath:
8B/10B encoder and decoder
byte ordering
Figure 1–47 shows the transceiver channel datapath in Basic mode with low-latency PCS operation. .
Transmitter in Electrical Idle
The transmitter buffer supports electrical idle state, where when enabled, the differential output buffer driver is tri-stated. During electrical idle, the output buffer assumes the common mode output voltage levels. For details about the electrical idle features, refer to “PCI Express (PIPE) Mode” on page 1–52.
1 The transmitter in electrical idle feature is required for compliance to the version 2.00 of PHY Interface for the PCI Express (PIPE) Architecture specification for PCIe protocol implementation.
Signal Detect at Receiver
Signal detect at receiver is only supported when 8B/10B encoder/decoder block is enabled.
Figure 1–47. Transceiver Channel Datapath in Basic Mode with Low-Latency PCS Operation
Byte Serializer
Serializer
rx _d
at ai
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Receiver Spread Spectrum Clocking
Asynchronous SSC is not supported in Cyclone IV devices. You can implement only synchronous SSC for SATA, V-by-One, and Display Port protocols in Basic mode.
PCI Express (PIPE) Mode PIPE mode provides the transceiver channel datapath configuration that supports ×1, ×2, and ×4 initial lane width for PCIe Gen1 signaling rate with PIPE interface implementation. The Cyclone IV GX transceiver provides following features in PIPE mode:
PIPE interface
clock rate compensation with rate match FIFO
Low-Latency Synchronous PCIe
electrical idle inference
compliance pattern transmission
reset requirement
Figure 1–48 shows the transceiver channel datapath and clocking when configured in PIPE mode with ×1 channel configuration. .
Figure 1–48. Transceiver Channel Datapath and Clocking when Configured in PIPE Mode with ×1 Channel Configuration
Notes to Figure 1–48:
(1) Low-speed recovered clock. (2) High-speed recovered clock.
Byte Serializer 8B/10B Encoder
Serializer
low-speed clocktx _c
rx _d
at ao
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Configuring the hard IP module requires using the PCI Express Compiler. When configuring the transceiver for PCIe implementation with hard IP module, the byte serializer and deserializer are not enabled, providing an 8-bit transceiver-PIPE-hard IP data interface width running at 250 MHz clock frequency.
f For more information about PCIe implementation with hard IP module, refer to the PCI Express Compiler User Guide.
Figure 1–49 shows the transceiver configuration in PIPE mode.
1 When configuring the transceiver into PIPE mode using ALTGX megafunction for PCIe implementation, the PHY-MAC, data link and transaction layers must be implemented in user logics. The PCIe hard IP block is bypassed in this configuration.
Figure 1–49. Transceiver Configuration in PIPE Mode
Functional Mode
Channel Bonding
Low-Latency PCS
2.5
Disabled
16-Bit
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