D8 MLB - InformaticaNapoli...Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY...

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DRAWING


TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISIONCKAPPD

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THE INFORMATION CONTAINED HEREIN IS THE

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THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

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II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

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D8 MLB

1 OF 117

2012-08-28ENGINEERING RELEASED

1 OF 143

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D8_DIRKAUDIO: Jack, Mikey, CHS Switch06/29/2012

TITLE=K22

ABBREV=DRAWING

LAST_MODIFIED=Mon Aug 27 13:24:34 2012

LAST_MODIFIED=Mon Aug 27 13:24:34 2012

N/A1

1 MASTERTable of ContentsContents

Date(.csa)

SyncPage SyncDate

Page(.csa)

Contents

SCH,D8,MLB

6166

D8_DAVIDAudio: Spkr/Mic Conn.06/13/2012

6267

D8_DAVIDAUDIO: Detects/Grounding06/13/2012

6368

D8_DAVIDAUDIO: Speaker ID06/13/2012

6469

D8_MARKPM Regulator Enables04/23/2012

6570

D8_MARKPM Power Good04/23/2012

6671

D8_MLBVReg CPU Core/AXG Cntl02/28/2012

67 72 D8_MLBVReg CPU Core Phases 02/28/2012

68 73 D8_MLBVReg CPU AXG Phases 02/28/2012

69 74 D8_KOSECOFFVReg CPU 1.05V S0 02/25/2012

70 75 D8_KOSECOFFVReg CPU VccSA S0 02/25/2012

71 76 D8_MLBVReg 3.3V S5/5V S4 02/28/2012

72 77 D8_KOSECOFFVReg VDDQ and 1.8V S0 02/25/2012

73 78 D8_MLBVREG 3.42V G3HOT 04/11/2012

74 79 D8_MLBFET-Controlled S0 and S4 05/14/2012

75 80 D8_AARONKEPLER PCI-E 03/13/2012

76 81 D8_YANKEPLER CORE/FB POWER 04/09/2012

77 82 D8_YANKEPLER FRAME BUFFER I/F 05/15/2012

7883

D8_YANGPU SIGNAL & POWER ALIASES04/09/2012

7984

D8_YANGDDR5 Frame Buffer A04/09/2012

8085

D8_YANGDDR5 Frame Buffer B04/09/2012

8186

D8_YANKEPLER EDP/DP/GPIO04/09/2012

8287

D8_YANKEPLER GPIOS,CLK & STRAPS07/27/2012

8388

D8_YANKEPLER PEX PWR/GNDS04/09/2012

8492

D8_AARONInternal DP MUXing03/13/2012

8593

D7_MLBTBT DDC Crossbar03/15/2012

8694

D8_AARONThunderbolt Connector A03/13/2012

8795

D8_MLBInternal DP Support03/21/2012

8896

D8_AARONThunderbolt Connector B03/13/2012

89 97 D8_MLBBacklight Controller MCU 04/23/2012

90 98 D8_MLBBacklight LED Driver 04/23/2012

91 99 D8_MLBBacklight Controller 04/23/2012

92 114 D8_MLBVReg GPU Core Phases 02/28/2012

93 115 D8_MLBVReg GPU Core Phases 02/25/2012

94 116 D8_MLBVREG GPU CORE PHASE 4 02/06/2012

95 117 D8_MLBGPU VDDQ AND 1V05 GPU/PCH/TBT VREGS 04/18/2012

96 120 D8_KOSECOFFD8 RULE DEFINITIONS 03/19/2012

97 121 D8_KOSECOFFDDR3 Constraints 03/19/2012

98 122 D8_AARONCPU PCIe Constraints 03/13/2012

99 123 D8_ROSITACPU MISC/DMI/FDI/XDP Constraints 03/23/2012

100124

D8_MARKSATA/FDI/XDP Constraints02/10/2012

101125

D8_MARKPCH and BR Constraints02/10/2012

102126

D8_KOSECOFFUSB/Camera Constraints06/22/2012

103127

D8_MARKSMBus/Sensor Constraints04/23/2012

104128

D8_MARKVReg Constraints02/10/2012

105129

D8_MARKCPU VReg Constraints02/10/2012

106130

D8_MARKPlatform VReg Constraints02/10/2012

107131

D8_AARONTBT/DP Constraints03/13/2012

108132

D8_AARONGDDR5/GPU Constraints03/13/2012

109134

D8_MLBBLC Constraints12/19/2011

110135

D8_MARKGPU VREG CONSTRAINTS02/10/2012

111 136 D8_FIYINETHERNET/SD CONSTRAINTS 07/02/2012

112 138 D8_MARKAUTO-CONSTRAINTS 1 04/23/2012






01/05/20122

2 D8_MLBSystem Block Diagram04/23/20123

3 D8_MARKPower Block Diagram12/19/20114

4 D8_MLBBOM Configuration06/22/20125

5 D8_TAVYSDEBUG LEDS06/20/20126

6 D8_DOUGPower Connectors/Aliases03/25/20127

7 D8_MLBHoles/PD parts04/02/201288 D8_MLB_ULTIMATEUnused Signal Aliases08/23/201199 K70_MLBSignal Aliases03/23/20121010 D8_ROSITACPU DMI/PEG/FDI/RSVD03/15/20121111 D7_MLBCPU CLOCK/MISC/JTAG03/15/20121212 D7_MLBCPU DDR3 INTERFACES03/15/20121313 D7_MLBCPU POWER03/15/20121414 D7_MLBCPU GROUNDS03/29/20121515 D8_MLBSTRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU12/20/20111616 D7_MLBCPU NON-GFX DECOUPLING01/26/20121717 D8_KOSECOFFGFX DECOUPLING & PCH PWR ALIASN/A1818 D8_MLBPCH SATA/PCIE/CLK/LPC/SPI03/15/201219

19 D7_MLBPCH DMI/FDI/GRAPHICS03/15/201220

20 D7_MLBPCH PCI/USBN/A21

21 D8_MLBPCH MISCN/A22

22 D8_MLBPCH POWER03/15/201223

23 D7_MLBPCH GROUNDSN/A24

24 D8_MLBPCH DECOUPLING01/26/201225

25 D7_MLBCPU and PCH XDPN/A26

26 D8_MLBCHIPSET SUPPORT03/23/201227

27 D8_ROSITAUSB 2.0 HUB (BT/SMC)04/23/201228

28 D8_MARKCPU Memory S3 Support03/19/201229

29 D8_KOSECOFFDDR3 SO-DIMM Connector A Slot003/19/20123030 D8_KOSECOFFDDR3 SO-DIMM Connector A Slot103/19/20123131 D8_KOSECOFFDDR3 SO-DIMM CONNECTOR B SLOT003/19/20123232 D8_KOSECOFFDDR3 SO-DIMM CONNECTOR B SLOT103/19/20123333 D8_KOSECOFFDDR3 ALIASES AND BITSWAPS03/19/20123434 D8_KOSECOFFDDR3/FRAMEBUF VREF MARGINING07/02/20123535 D8_FIYINAIRPORT/BTN/A3636 D8_MLBThunderbolt Host (1 of 2)03/15/20123737 D7_MLBThunderbolt Host (2 of 2)03/15/20123838 D7_MLBThunderbolt Power Support07/02/20123939 D8_FIYINETHERNET PHY (CAESAR IV+)07/02/20124040 D8_FIYINEthernet Support & Connector07/02/201241

41 D8_FIYINSD READER CONNECTOR03/23/201242

42 D8_ROSITACamera Controller03/15/201243

43 D7_MLBCamera Controller Support01/31/201245

44 D8_JERRYSATA Connectors03/23/201246

45 D8_ROSITAEXTERNAL USB PORTS A & B03/23/201247

46 D8_ROSITAEXTERNAL USB PORTS C & D03/22/201249

47 D8_MARKSMC07/19/201250

48 D8_DOUGSMC SupportN/A51

49 D8_MLBSPI and Debug Connector06/22/201252

50 D8_TAVYSSMBus Connections06/20/201253

51 D8_DOUGI and V Sense 102/25/20125452 D8_JERRYHDD/SSD Temp Sense06/07/20125553 D8_DOUGTemperature Sensors07/19/20125654 D8_DOUGSystem Fan04/23/20125955 D8_MARKI and V Sense 206/13/20126156 D8_DAVIDAUDIO: CODEC/REGULATORS06/13/20126257 D8_DAVIDAUDIO: HEADPHONE AMP06/13/20126358 D8_DAVIDAUDIO: LEFT SPKR AMP06/13/20126459 D8_DAVIDAUDIO: RIGHT SPKR AMP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

System Block diagram can be found on KismetPATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram

D8_MLB 01/05/2012

System Block Diagram

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RegulatorU7600

PP3V42_G3H

IW0R

Fan

TBT IOSpeaker ampsGPULCD

PPVCCSA_S0

PP1V05_S0_CPU

PPVCORE_S0_CPU

PPVAXG_S0

PPFBVDDQ_S0_GPU

PPVCORE_S0_GPU GPU (Core)

GPU (FB)

CPU (AXG)

CPU

CPU (Core)

CPU (VccIO)

PP1V05_TBTCIO

PP1V05_TBTLC

P1V05_S0_PCH

P1V05_S0

TBT Router

TBT Router

GPU (IOVDD, PLLVDD)

PCH (VCC, VccIO)

PP12V_S0_HDD HDD (12V)

PH0R

PGTR

=

=

PH02 + PH05

=PCTR

SMC, RTC, MojoMux

PP12V_G3H

en

Regulator

VD2R

PR1RIR1R RegS0

Vin

UB700

en S0 1V05

SD Card, DP Mux, DP X-bar

VD2R

PG0FVD2R

IG0F

PC0S

Regulator

S0

FBVDDQ

GPU

3.3V

PCH, PwrCtl

RegulatorU7801

Reg

VinG3H G3H3V42

VccIOS0S0 RegVinen

RegulatorU7400

Bootrom, PCH, SMC, XDP,

Audio, LCD TCON, SnsCtl, VRD, PCH

PP5V_S0

VRegCtl, SnsCtlAudio, PCH

PP5V_S0_HDD HDD (5V)

PP5V_S4 CAM, USB Ports, VRegCtl

PH05IH05

VH05

SSD PP3V3_S0_SSDPH1R

IW1R

V3V3

PP3V3_S0

VG0C

VC0C

USB Hub, SMC, TBT I/O

PP3V3_S4_ENET

PP3V3_S4

WIFI PP3V3_S4_APPW0R

V3V3

SD Card, USB Mux, VRD, PwrCtl

PP3V3_TBTLC TBT Router

Ethernet

IC0S

S4RegS4en 5V

S0LDOS0en VTT

VTTLDO S3

S3Regen S3

RegulatorU7700

VinVDDQ IM0R

VM0RPM0R

PPDDRVTT_S0 DIMM (VTT)

DIMM VREF Margining CA

IC0M

VC0MPC0M

PPDDRVTT_S3

PP1V5_S0

PPVDDQ_S3_DDR

PP1V5_S0_CPU_MEM CPU (Mem)

Audio

DIMM (1V5)

Vin

PH02IH02

VD2R

UB750Regulator

Loads

IN1R

VN1RPN1R

en S0 Reg GPUS0

UB400

Vinen S0Reg IG0C PG0C

U7100

VinS0

Regulator

AXG

VC0G

IC0GPC0G

S0Reg Core IC0CPC0C

en Reg VccSAS0VD2R

VD2R

IC0IPC0I

RegulatorU7500

Vin

PPHV_SW_TBTAPWR

PPHV_SW_TBTBPWR

TBT Port A

TBT Port B

PD2RID2R

Supply Module

PP5V_S0

enVin

S0

U7750Regulator

Reg S0 1.8V PP1V8_S0_REG CPU PLL

en

PP12V_S5

S5Reg

VinPP5V_S5

PP12V_S0_BLC

S5 LDO 5VS5

PP12V_ACDC12VG3H

AC/DC

Reg

ALS, CAM, BT

en

PP3V3_S5

S0

PP12V_S0

S0Reg

PC0I+PC0S+)PC0MPC0G+PC0C( +5.7 (GK104/GK107_BLENDED_CONSTANT)+PG0F+PG0C

1.176 *

1.176 *

High-side Component Total Power Keys

SYNC_DATE=04/23/2012SYNC_MASTER=D8_MARK

Power Block Diagram

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TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM

TABLE_5_ITEM

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TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM



TABLE_5_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM


PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

TABLE_5_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



BOM Groups

CPUs

Programmable Parts

ALTERNATE:335S0854

ASICs

ALTERNATE:335S0812

BOM Variants

CPU SOCKET ALTERNATES

D8 SCHEMATIC / PCB #’S

CPU SOCKET

D8 ALTERNATES

VRAM MODULE PARTS

Bar Code Labels / EEEE #’s

D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F49T639-3952 PCBA,MLB,3.1G,4C,GK107,SAM,D8

D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F653639-4092 PCBA,MLB,2.9G,4C,GK107,HYN.D8

639-4093 D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F654PCBA,MLB,3.1G,4C,GK107,HYN.D8

PCBA,MLB,DEV,D8085-4433 DEVELOPMENT,D8_DEVEL

IC, GPU, NV GK107-GE-PS-A2337S4280 U8000 CRITICAL GPU:107EGE1

825-7896 LABEL,MLB,2D EEEE_DHNM CRITICAL1 EEEE:DHNM

CRITICAL FB:BOTH_SAMSUNG333S0619 IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF U8400,U8450,U8500,U85504

333S0620 4 IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE FB:BOTH_HYNIXU8400,U8450,U8500,U8550 CRITICAL

377S0147 ALL USB diodes377S0126

U3990 CRITICAL CIVROM:PROG1341S3645 IC,ENET 1MBIT, SPI,ROM, V1.13 D8

CAMROM:BLANKCRITICAL1 U4202335S0852 IC,FLASH,SPI,1MBIT,3V3

338S1098 U4900 SMC:BLANKIC,SMC,LX4FS1AH5BBCIGA31 CRITICAL

SMC:PROGCRITICAL1 U4900341S3394 IC,PROGRMD,SMC,A3,V2.2A32,D8

CRITICALU4202 CAMROM:PROG1341S3675 IC,CAMERA FLASH,V7228,D7/D8

511S0071 ALL511S0073 TYCO SOCKET

511S0073 ALL511S0072 FOXCONN SOCKET

U1000511S0073 CRITICAL1 SOCKET,MOLEX,LGA1155,CPU-LF

D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F2FR639-3816 PCBA,MLB,2.9G,4C,GK107,SAM,D8

157S0084 Enet MagneticsALL157S0058

IC,BCM57766A1,ENET&SD,8X8343S0616 1 U3900 CRITICAL

IC,TBT,CR-4C,B1,PRQ,288 FCBGA,12X12MM338S1113 U3600 CRITICAL1

IC,PANTHER POINT,C1,SLJC7,PRQ,BD82Z77337S4277 U1800 CRITICAL1

1337S3978 CRITICAL BLCMCU:BLANKU9700IC,BLC MCU LPC2132FBD64/01, LQFP64

TBTROM:PROGCRITICAL1 U3690341S3672 IC,EEPROM,CR,V14.1 (B1),D8

1 CRITICALU3690 TBTROM:BLANKIC,EEPROM,SERIAL,8KB,MLP8335S0865

U9700 BLCMCU:PROGCRITICAL341S3674 IC,BLC,MCU, PRPOGRAMMED, V0204, D81

1 U3990 CRITICAL CIVROM:BLANK335S0862 IC,SERIAL FLASH,2MBIT, 2.7V, REF F

335S0807 1 BOOTROM:BLANKCRITICALU5110IC,64 MBIT SPI SERIAL FLASH

CRITICAL BOOTROM:PROG1 U5110IC,PROGRMD,EFI ROM,V00FC,D7/D8341S3673

376S0975 ALL376S1081 P/NCH DUAL FET

PCBF,MLB,D8 CRITICALPCB11 D8820-3298

1 CRITICALSCH1 D8SCH,MLB,D8051-9504

341S3644 U3990 CIVROM341S3645

150UF CAPS BLK128S0368128S0365 ALL

102S0880 0.010 OHM,1%,1206102S0879 ALL

ALL138S0804 2.2UF CAPS SOFT138S0803

825-7896 LABEL,MLB,2D EEEE_F2FR1 CRITICAL EEEE:F2FR

LABEL,MLB,2D CRITICAL1 EEEE:F49VEEEE_F49V825-7896

337S4372 CRITICAL1 CPUIVB,SR0T9,PRQ,N0,3.1,65W,4+1,1.1,6M,LGA CPU:4C_3P1GHZ

BOM ConfigurationSYNC_MASTER=D8_MLB SYNC_DATE=12/19/2011

1 LABEL,MLB,2D CRITICAL EEEE:F653EEEE_F653825-7896

337S4355 CPU1 CRITICALIVB,SR0TA,PRQ,N1,2.9,65W,4+1,1.1,6M,LGA CPU:4C_2P9GHZ

D8_DEVEL XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV

SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROGD8_PROGPARTS

XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V,FBA,FBBD8_COMMON1

D8_PRODUCTION VREFMRGN:N,PRODUCTION

D8_COMMON COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION

825-7896 EEEE:F654EEEE_F654 CRITICALLABEL,MLB,2D1

825-7896 LABEL,MLB,2D EEEE_F49T CRITICAL1 EEEE:F49T

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SIN

G

D

SING

D

SIN

G

D

S

G

D

SIN

IN

G

D

SIN G

D

SING

D

SIN G

D

SIN

G

D

SING

D

SING

D

S

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MEM 1V5_S3 LED

LED GND ISOLATION SWITCH

ALL_SYS_PWRGD LED

S5 LED

CPU 1V05_S0 LED

S4 (SLEEP) LED

GPU FBVDD LED

CPU VCORE LED

BLC_EN LED

CPU AXG LEDPCH/GPU 1V05 LED

GPU_GOOD LED VIDEO_ON LED

GPU VCORE LEDSLP_S3 LED

APN: 705S0137

64 69 115

5%1/16W

1K

402

R507DEVELOPMENT

MF-LF

2.0X1.25MM-SMGREEN-3.6MCD

LED507DEVELOPMENT

SOT-363

Q5072N7002DW-X-G

DEVELOPMENT

64 95 115

402MF-LF

5%1/16W

1KR502DEVELOPMENT


LED502DEVELOPMENT

1/16WMF-LF

5%

402

1KR512

LED512GREEN-3.6MCD

SILK_PART=3

2.0X1.25MM-SM

PLACE_SIDE=BOTTOM

2N7002DW-X-GSOT-363

Q511

1/16W

1K5%

402

R511

MF-LF

SILK_PART=2 LED511PLACE_SIDE=BOTTOM

GREEN-3.6MCD2.0X1.25MM-SM

21 99

Q511SOT-3632N7002DW-X-G

47 65 112

MF-LF402

1K5%1/16W

R501

2.0X1.25MM-SM

SILK_PART=1 LED501PLACE_SIDE=BOTTOM

GREEN-3.6MCD

5%1/16W

R5131K

MF-LF402


LED513SILK_PART=4PLACE_SIDE=BOTTOM

SOT-3632N7002DW-X-GQ513

1/16WMF-LF

5%1K

402

R514DEVELOPMENT


LED514DEVELOPMENT

SOT-3632N7002DW-X-GQ513DEVELOPMENT

89

87 107

SM

SW500KMT221GLHS

DEVELOPMENT

1/16W

1K5%

R505

402MF-LF

DEVELOPMENT


LED505DEVELOPMENT

SOT-363

Q5052N7002DW-X-G

DEVELOPMENT

64 92 110

402MF-LF1/16W5%

R5061K

DEVELOPMENT


LED506DEVELOPMENT

Q505SOT-3632N7002DW-X-G

DEVELOPMENT

64 95 115

402

5%1K1/16WMF-LF

R503DEVELOPMENT

LED5032.0X1.25MM-SMGREEN-3.6MCD

DEVELOPMENT

SOT-363

Q5032N7002DW-X-G

DEVELOPMENT

64 72 115

1/16WMF-LF

5%1K

402

R504DEVELOPMENT

GREEN-3.6MCD

LED504DEVELOPMENT

2.0X1.25MM-SM

2N7002DW-X-GQ503SOT-363

DEVELOPMENT

15 19 28 40 47 48 64 115

5%1K

MF-LF1/16W

402

R510DEVELOPMENT


LED510DEVELOPMENT

GREEN-3.6MCD

LED5092.0X1.25MM-SM

DEVELOPMENT

402

1K5%1/16WMF-LF

R509DEVELOPMENT

SOT-3632N7002DW-X-GQ509DEVELOPMENT

25 65 66 115

Q509SOT-3632N7002DW-X-G

DEVELOPMENT

1/16WMF-LF

5%1K

402

R508DEVELOPMENT

GREEN-3.6MCD

LED508DEVELOPMENT

2.0X1.25MM-SM

66 116 2N7002DW-X-GQ507DEVELOPMENT

SOT-363

SYNC_MASTER=D8_TAVYS

DEBUG LEDSSYNC_DATE=06/22/2012

ALL_SYS_PWRGD

PM_LED_A_PGOOD_REG_GPUCORE_S0

=PP3V3_S5_LED

GPU_GOOD

PM_LED_K_ALL_SYS_PWRGD PM_LED_K_GPU_GOOD

=PP3V3_S4_LED =PP3V3_S0_LED =PP3V3_S0_LED

PM_LED_A_VIDEO_ON

VIDEO_ON_L

NO_TEST=TRUENC_Q513_1

NO_TEST=TRUENC_Q513_6

NC_Q513_2NO_TEST=TRUE

PM_PGOOD_REG_P1V05_S0

=PP3V3_S0_LED

PM_PGOOD_REG_VDDQ_S3

=PP3V3_S5_LED

PM_LED_A_PGOOD_REG_VDDQ_S3

PM_LED_K_PGOOD_REG_VDDQ_S3

LED_GND

PM_LED_K_PGOOD_REG_P1V05

LED_GND

PM_LED_A_PGOOD_REG_P1V05

PM_PGOOD_REG_CPU_P1V05_S0

LED_GND

PM_SLP_S3_L

=PP3V3_S0_LED

PM_LED_K_PGOOD_CPU_P1V05_S0

LED_GND

PM_LED_K_SLP_S3

PM_LED_A_SLP_S3

REG_CPUAXG_PGOOD

LED_GND

PM_PGOOD_REG_GPUCORE_S0

PM_LED_A_CPUAXG_PGOOD

PM_LED_K_CPUAXG_PGOOD

=PP3V3_S0_LED

LED_GND

PM_LED_K_PGOOD_REG_GPUCORE_S0

=PP3V3_S5_LED

PM_PGOOD_REG_CPUCORE_S0

PM_PGOOD_REG_FBVDDQ_S0

BLC_GOOD

LED_GND

=PP3V3_S0_LED

LED_GND

PM_LED_K_BLC_GOOD

PM_LED_A_BLC_GOOD

PM_LED_K_PGOOD_CPUCORE_S0

PM_LED_A_PGOOD_CPUCORE_S0

=PP3V3_S0_LED

LED_GND

PM_LED_K_PGOOD_REG_FBVDDQ_S0

=PP3V3_S5_LED

PM_LED_A_PGOOD_REG_FBVDDQ_S0

LED_GND

=PP3V3_S4_LED

PM_LED_A_S4

PM_LED_A_PGOOD_CPU_P1V05_S0

PM_LED_A_GPU_GOODPM_LED_A_ALL_SYS_PWRGD

PM_LED_A_S5

=PP3V3_S5_LED

MIN_NECK_WIDTH=0.2 MM

LED_GND

MIN_LINE_WIDTH=0.3 MM

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OUT

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FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712

MLB to AC-DC Supplemental Signal Connector

MLB to AC-DC Connector

S5 RailsOn when in S5

G3 Rails

518-0389

518S0863

Always on: Keeps the PCH RTC alive

THIS IS 1.5V RAIL

THIS IS 1.5V RAIL

THIS IS 1.5V RAIL

S3 RailsEnabled when system is in run or sleep

GPU Rails (S0)Enabled when system is in run

Ground/CommonS0 RailsEnabled when system is in run

Enabled when Thunderbolt cable is plugged inThunderbolt Rails (S0)

G3H RailsOn with AC/DC plugged in

Enabled when system has AC and is in run or sleepS4 Rails

J600.5:10MMEMC

25V5%

402NP0-C0G

1000PFC603

J600.5:10MMEMC

402

25V5%

C6021000PF

NP0-C0G

C60110%

805X5R25V

10UF

J600.4:10MM

53 117

J601504050-0791

M-RT-SM

SILK_PART=PWRSIG

PLACE_NEAR=J601.3:30MM

R603

402

1/16WMF-LF

10K5%

53 117

5%

R606PLACE_NEAR=J601.1:3MM

1/16W

402MF-LF

1K

6.8V-100PF402

D600PLACE_NEAR=J601.1:3MM

48 116

MF-LF


1K

402

R604

1/16W5%

PLACE_NEAR=R604.2:3MM

C60420%

X7R-CERM0402

0.01UF16V


4026.8V-100PF

D60148 71

112

PLACE_NEAR=J601.7:3MMR600

5%

402

1/16W

1K

MF-LF


D6026.8V-100PF

402

43045-1201

CRITICAL

M-RT-TH-1

J600

PLACE_NEAR=R606.1:3MM

X7R-CERM16V10%

C6000.1UF

0402

PLACE_NEAR=R600.1:3MM 16V

0402X7R-CERM

0.1UF10%

C605

SYNC_MASTER=D8_DOUG

Power Connectors/AliasesSYNC_DATE=06/20/2012

PP1V8_S0MAKE_BASE=TRUE

=PP1V8_S0_PCH_VCC_VRM=PP1V8_S0_PCH_CLK

PP1V8_S0_REG

=PP1V8_S0_CPU_PLL=PP1V8_S0_PCH=PP1V8_S0_PCH_VCC_DFTERM

=PP1V5_S0_DP

PP1V5_S0_CPU_MEM_SNS=PP1V5_S0_CPU_MEM

=PP12V_S0_FAN

=PP12V_S0_HDD_PWR

=PP12V_S0_REG_CPU_P1V05_PWRSMC_ACDC_ID

PP12V_S0MAKE_BASE=TRUE

=PP12V_S0_PWRCTL

=PP12V_S0_REG_P1V05_PWR=PP12V_S0_REG_CPU_VCCSA_PWR

=PP5V_S0_VRD

MAKE_BASE=TRUEPP5V_S0

=PP12V_S0_REG_CPUCORE=PP12V_S0_LCD

=PP12V_S0_REG_GPUCORE=PP12V_S0_FBVDDQ_PWR

PP12V_S0_FET=PP12V_S0_AUDIO_SPKRAMP

PP5V_S4_REG=PP5V_S4_REG_VDDQ_S3

=PP3V3_S0_VRD

TSNS_ACDC_NTSNS_ACDC_P

PWR_BTN_R

MAKE_BASE=TRUEPP3V3_G3

MAKE_BASE=TRUEPP12V_G3H

MAKE_BASE=TRUEPP3V42_G3H

SMC_ACDC_ID_R

SMC_ACDC_ID_R

=PP3V3_G3H_LPCPLUS

=PPVIN_G3H_SMCVREF

PP3V42_G3H_REG=PP3V3_G3H_BT

=PP12V_G3H_FET_P12V_S5

=PP3V3_G3_PCH

PP12V_ACDCMAKE_BASE=TRUE

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_VCC_GPIO=PP3V3_S0_PCH_VCC_ADAC

=PP3V3_S0_PCH_STRAPS

PP12V_S5_FET =PP3V3_TBT_CLK

PPVCCSA_S0_REG

PPCPUAXG_S0_REG

PPCPUCORE_S0_REG

=PP3V3_S0_SMBUS_TCON

PP3V3_S0_SSD_SNS

=PP3V3_S0_TBTPWRCTL=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC

=PP5V_S0_HDD_PWR

=PP3V3_S0_DP=PP3V3_S0_ENET=PP3V3_S0_FAN=PP3V3_S0_GPU=PP3V3_S0_INTDPMUX=PP3V3_S0_LED

=PP3V3_S0_MEM_A_SPD

=PP3V3_S0_PCH

=PP3V3_S0_PCH_VCC

PP5V_S0_HDD_SNS=PP5V_S0_HDD

=PP3V3_S0_GPU_IFPX_PLLVDDPP3V3_S0_FET

=PP1V05_S0_GPU_IFPEF_IOVDD=PP1V05_S0_GPU_PEX_PLLVDD

=PP1V05_S0_GPU_PEX_IOVDD

=PP1V05_S0_GPU_IFPCD_IOVDD

=PP1V05_S0_PCH_PWR=PP1V05_S0_P1V05TBTFET

PP1V05_S0_REG

=PPVCCIO_S0_CPU=PPVCCIO_S0_SMC=PPVCCIO_S0_XDP

PP1V05_S0_CPU_REG

=PPVAXG_S0_CPU

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

PPDDRVREF_DQ_MEM_B=PPDDRVREF_DQ_MEM_B

PPDDRVREF_CA_MEM_B

=PP3V3_TBTLC_RTR

PP12V_S0_REG_CPU_P1V05_SNS =PP1V05_S0_PCH_VCCIO_DMI

=PPDDRVREF_CA_MEM_B

PP5V_S0_FET

=PP12V_S0_REG_P1V05

=PP12V_S0_REG_VCCSA

=PPDDRVTT_S0_MEM_A=PPDDRVTT_S0_MEM_B

=PP1V5_S0_CPU_MEM_PWR

=PPVCORE_S0_GPU

=PP1V05_S0_PCH_VCCIO_USB

PPDDRVREF_DQ_MEM_A

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_AUDIO=PP3V3_S0_AUDIO_DIG

PP12V_S0_REG_CPU_VCCSA_SNS

=PP5V_S0_REG_P1V05

PP12V_S0_REG_P1V05_SNS

=PPDDRVREF_CA_MEM_A

PP1V05_S0_PCH_SNS=PP1V05_S0_PCH=PPDDRVREF_DQ_MEM_A

=PP1V05_S0_PCH_VCC_DMI=PP1V05_S0_PCH_VCC_DIFFCLK

=PP1V05_S0_PCH_VCC_ADPLL

=PP1V05_S0_PCH_VCCIO_SATA=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCCLKDMI

=PP1V05_S0_PCH_VCC_SSC=PP1V05_S0_PCH_V_PROC_IO

=PP1V35_S0_GPU_FBVDDQ

PPGPUCORE_S0_REG

=PP3V3_S0_PCH_PM

=PP3V3_S0_P3V3TBTFET

PP1V5R1V35_S0_GPU_REG

=PP5V_S0_REG_FBVDDQ

=PP1V05_S0_PCH_VCC_CORE=PP1V05_S0_PCH_VCC_ASW

PP1V5_S0_FET=PP1V5_S0_AUD_DIG

=PP3V3_S0_GPU_MISC=PP3V3_S0_GPU_VDD33

PP12V_S0_FBVDDQ_SNS

=PP3V3_S0_PCH_VCC_PCI

=PP3V3_S0_SDCARD=PP3V3_S0_RSTBUF

=PP3V3_S0_SSD_PWR

=PPDDRVTT_S0_CLAMP

=PP12V_S0_REG_FBVDDQ

=PP12V_S0_BLC

=PP12V_S0_HDD

PP12V_S0_BLC_FET

PPDDRVTT_S0_LDOPP12V_S0_HDD_SNS

=PP12V_S0_REG_CPU_P1V05

=PP3V3_S0_PWRCTL

=PP3V3_S0_PCH_VCC_HVCMOS

=PP3V3_S0_LED_SATA

PP5V_S0_HDDMAKE_BASE=TRUE

MAKE_BASE=TRUEPPDDRVTT_S0

PPDDRVREF_DQ_MEM_A_S3MAKE_BASE=TRUE


PPVCORE_S0_GPUMAKE_BASE=TRUE

PP12V_S0_FBVDDQMAKE_BASE=TRUE

PP1V05_TBTLCMAKE_BASE=TRUE

MAKE_BASE=TRUEPPFBVDDQ_S0_GPU

MAKE_BASE=TRUEPP12V_S0_CPU_P1V05

PP12V_S0_VCCSAMAKE_BASE=TRUE

MAKE_BASE=TRUEPPDDRVREF_CA_MEM_A_S3

MAKE_BASE=TRUEPP3V3_S0_SSD

MAKE_BASE=TRUEPP12V_S0_BLC

MAKE_BASE=TRUEPP12V_S0_HDD

PPDDRVREF_CA_MEM_B_S3MAKE_BASE=TRUE

MAKE_BASE=TRUEPPVAXG_S0

MAKE_BASE=TRUEPPVCCSA_S0

PPVCORE_S0_CPUMAKE_BASE=TRUE

PP1V05_S0_CPUMAKE_BASE=TRUE

PP1V05_S0_PCHMAKE_BASE=TRUE

PPDDRVREF_DQ_MEM_B_S3MAKE_BASE=TRUE


PP1V5_S0_CPU_MEMMAKE_BASE=TRUE

PP12V_S0_P1V05MAKE_BASE=TRUE

PP3V3_TBTLCMAKE_BASE=TRUE

=PP3V3_TBT_PCH_GPIO

=PP3V3_S0_SENSE=PP3V3_S0_SMBUS

=PP3V3_TBTLC_FET

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP1V05_TBTLC_FET

=PP3V3_S0_BLC

=PP1V05_TBTCIO_FETPP1V05_TBTCIOMAKE_BASE=TRUE

PPVDDQ_S3MAKE_BASE=TRUE

PPVDDQ_S3_DDRMAKE_BASE=TRUE

MAKE_BASE=TRUEPPDDRVTT_S3

=PP5V_S4_MEMRESET

PP3V3_S4_FET=PP3V3_S4_ALS=PP3V3_S4_AP_PWR

=PP3V3_S4_ENET=PP3V3_S4_LED=PP3V3_S4_MEMRESET

=PP3V3_S4_PWRCTL=PP3V3_S4_PM

=PP3V3_S4_SENSE

=PP3V3_S4_SMBUS_SMC=PP3V3_S4_SMC=PP3V3_S4_TBT

PP3V3_S4_AP_SNS=PP3V3_S4_AP

PP3V3_S4_ENET_FET

=PP3V3_S4_ENET_SYSCLK=PP3V3_S4_ENET_FET

=PP3V3_S4_ENET_CLK

PPVDDQ_S3_REG

=PPVDDQ_S3_FET_VDDQ_S0=PPVDDQ_S3_DDR_PWR

=PPVDDQ_S3_LDO_DDRVTT

PPVDDQ_S3_DDR_SNS=PPVDDQ_S3_DDR_VREF=PPVDDQ_S3_MEM_A=PPVDDQ_S3_MEM_B=PPVDDQ_S3_MEMRESET

PPDDRVTT_S3_LDO=PPDDRVTT_S3_VREFCA

PP3V3_G3_RTC=PP3V3_G3_PCH_RTC

=PP12V_G3H_PWR

PP12V_G3H_SNS=PP12V_G3H_P3V42

=PP12V_S5_REG_P3V3P5V_S5=PP12V_S5_REG_VDDQ_S3

=PP5V_S0_REG_CPU_P1V05=PP5V_S0_REG_CPUCORE

=PP5V_S0_LPCPLUS=PP5V_S0_ISENSE

=PP5V_S0_PCH

=PP5V_S0_REG_P1V8=PP5V_S0_REG_VCCSA

=PP5V_S0_AUDIO=PP5V_S0_BLC

BURSTMODE_EN_R_L

PPDDRVREF_CA_MEM_A

=PP3V3_S0_SSD

=PP3V3_S0_VRD



PP12V_G3H_ACDC

MAKE_BASE=TRUEPP3V3_S4_ENET

=PP3V3_S4_CAMERA

=PP5V_S4_USB

=PP5V_S4_FET_P5V_S0

=PP5V_S4_CAMERA

PP3V3_S4_APMAKE_BASE=TRUE

PP12V_G3H_ACDC

=PP12V_S5_PWRCTL=PPHV_SW_TBTAPWRSW

MAKE_BASE=TRUEPP3V3_S5

=PP5V_S5_PWRCTLPP5V_S5_LDO

=PP5V_S5_PCH

PP3V3_S5_REG=PP3V3_S5_FET_P3V3_S0=PP3V3_S5_FET_P3V3_S4=PP3V3_S5_SMC=PP3V3_S5_LED

=PP3V3_S5_PCH_STRAPS=PP3V3_S5_PCH

=PP3V3_S5_PCH_VCCSUS_HDA

=PP3V3_S5_PCH_VCC_DSW=PP3V3_S5_PCH_VCCSUS_USB

=PP3V3_S5_PWRCTL=PP3V3_S5_ROM

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S5_VRD=PP3V3_S5_XDP=PP3V3_S5_SMC_USBMUX

=PP3V3_S5_SDCARD=PP3V3_S5_SENSE

=PPHV_SW_TBTBPWRSW=PP12V_S5_SNS

PP12V_S5MAKE_BASE=TRUE

=PP3V3_G3H_SMC_USBMUX=PP3V3_G3H_SMC


=PP3V3_G3H_RTC_D

=PP12V_G3H_FET_P12V_S0

PP12V_G3H_ACDC

PWR_BTN

BURSTMODE_EN_L

=PP3V3_S4_SMBUS

=PP3V3_S4_USB_HUB

=PP3V3_S4_TBTAPWRSW=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_VREFMRGN

=PP3V3_S4_AUDIO_DIG

MAKE_BASE=TRUEPP3V3_S4

GNDMAKE_BASE=TRUE

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86

106

71

71

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71

74

74

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15

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22 24

22 24

22 24

64 65

49

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71

25

45 46

41

51

88

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45

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48 88

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GPU HEATSINK MOUNTING FEATURES(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)

998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD)HEATPIPE MTG HOLES

WIRELESS CARD MTG HOLES998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD)

APN: 860-1461

860-1487 (PCB STANDOFF)

SSD STANDOFF

Rear Cover

Rear Cover998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)

4MM PLATED HOLES (998-4158)CPU Heatsink

ZH07008P5R5-NSP

OMIT

8P5R5-NSP

OMITZH0701 ZH0702

8P5R5-NSP

OMIT

8P5R5-NSP

OMITZH0703

STDOFF-4.5OD2.2ID-5.6H-SMNUT0713CRITICAL

ZH0715STDOFF-7.14OD16.45H-TH-1.5-5.2

CRITICAL

STDOFF-7.14OD16.45H-TH-1.5-5.2

CRITICAL

ZH0718

ZH0722CRITICAL

5P5R1P9-4P3B-NSP

CRITICAL

5P5R1P9-4P3B-NSPZH0721

10R12ZH0726

6P0R3P2-NSP

CRITICAL

ZH0725CRITICAL

6P0R3P2-NSPZH0724

6P0R3P2-NSP

CRITICAL

ZH0723

ZH07178P5R4P0-8P0B-NSP

CRITICAL

ZH07168P5R4P0-8P0B-NSP

CRITICAL

CRITICAL


CRITICAL


CRITICAL

ZH07206P0R3P2-NSP

SYNC_MASTER=D8_MLB

Holes/PD partsSYNC_DATE=03/25/2012

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PCH Clocks

PCH PCIe

PCH USB

CPU Memory

PCH PCI

PCH Unused Display PCH Test PointsPCH SATA

PCH and CPU FDI

PCH Miscellaneous

CPU Reserved

PCH Reserved

SYNC_DATE=04/02/2012

Unused Signal AliasesSYNC_MASTER=D8_MLB_ULTIMATE

TP_MEM_A_DQS_P

TP_MEM_A_DQ_CB

NC_DMI_MIDBUS_CLK100NXNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCIE2_R2D_CNXMAKE_BASE=TRUE NO_TEST=TRUE

TP_PCIE2_R2D_CN

TP_PCIE2_R2D_CP

TP_PCI_CLK33M_OUT2

TP_PCI_CLK33M_OUT3

TP_PCH_PWM3

TP_PCH_SST

TP_PCH_RESERVE_0

MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_C_AUXNX

DP_IG_C_MLPNC_PCIE_CLK100M_PE5NX

NO_TEST=TRUEMAKE_BASE=TRUETP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P

DMI_MIDBUS_CLK100M_N

NC_DMI_MIDBUS_CLK100PXMAKE_BASE=TRUE NO_TEST=TRUE

DMI_MIDBUS_CLK100M_P

TP_PCIE_CLK100M_PE0N

TP_PCIE2_D2RP

NO_TEST=TRUEMAKE_BASE=TRUENC_PE_TNX

DP_IG_D_CTRL_DATA

DP_IG_D_HPD

TP_PCIE1_D2RN

TP_PCIE1_R2D_CN

TP_MEM_B_DQ_CB

CPU_CFG

TP_CPU_RSVD

TP_CPU_RSVD

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_D_D2RN

TP_SATA_E_D2RN

TP_SATA_F_R2D_CN

TP_MEM_A_DQS_N

TP_PCH_PWM0

TP_HDA_SDIN2

PCH_FDI_FSYNC

PCH_FDI_LSYNC

PCH_FDI_INT

PCH_FDI_RX_N

PCH_FDI_RX_P

TP_CPU_FDI_TX_N

TP_CPU_FDI_TX_P

TP_SDVO_STALLP

TP_SDVO_INTN

TP_CPU_FDI_FSYNC

TP_CPU_FDI_LSYNC

TP_CPU_FDI_INT

TP_PCH_CL_DATA1

TP_PCH_CL_CLK1

TP_HDA_SDIN3

TP_PCH_RESERVE_8

TP_PCH_L_VDD_EN

TP_PCH_L_BKLTEN

TP_PCH_RESERVE_27

TP_PCH_RESERVE_25

DP_IG_C_MLN

DP_IG_B_DDC_DATA

DP_IG_C_AUX_N

TP_SDVO_INTP

TP_PCH_CL_RST1

TP_PCH_PWM2

TP_PCH_PWM1

TP_PCH_RESERVE_20

TP_PCH_RESERVE_23

TP_PCH_RESERVE_7

TP_PCH_RESERVE_19

TP_PCH_RESERVE_21

TP_PCH_RESERVE_28

TP_PCH_RESERVE_24

TP_PCH_RESERVE_17

TP_PCH_RESERVE_18

TP_PCH_RESERVE_15

TP_PCH_RESERVE_16

TP_PCH_RESERVE_14

TP_PCH_RESERVE_13

TP_PCH_RESERVE_12

TP_PCH_RESERVE_10

TP_PCH_RESERVE_11

TP_PCH_RESERVE_9

TP_PCH_RESERVE_5

TP_PCH_RESERVE_6

TP_PCH_RESERVE_3

TP_PCH_RESERVE_4

TP_SDVO_TVCLKINP

DP_IG_C_AUX_P

DP_IG_C_CTRL_CLK

TP_PCH_L_BKLTCTL

TP_SDVO_STALLN

DP_IG_D_MLP

TP_SDVO_TVCLKINN

DP_IG_D_AUXN

DP_IG_D_AUXP

DP_IG_D_MLN

TP_SATA_F_D2RP

TP_CRT_IG_DDC_DATA

TP_CRT_IG_VSYNC

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_SATA_E_R2D_CP

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_PCH_TP20

TP_PCH_TP19

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP12

TP_PCH_TP11

TP_PCH_TP10

TP_PCH_TP9

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP4

TP_PCH_TP3

TP_SATA_D_D2RP

TP_PCH_TP2TP_SATA_C_R2D_CP

TP_SATA_E_D2RP

DP_IG_C_HPD

DP_IG_D_CTRL_CLK

DP_IG_C_CTRL_DATA

TP_LPC_DREQ0_L

TP_PCH_INIT3V3_L

TP_HDA_SDIN1

TP_CRT_IG_HSYNC

TP_SATA_F_R2D_CP

TP_PCH_RESERVE_22

TP_PCH_RESERVE_26

TP_SATA_E_R2D_CN

TP_PCH_TP1

TP_SATA_F_D2RN

DP_IG_B_DDC_CLK

TP_PCI_AD

TP_PCI_C_BE_L

TP_PCI_PAR

TP_PCI_RESET_L

TP_PCH_PCI_GNT0_L

TP_PCH_RESERVE_2

TP_PCH_RESERVE_1

DP_IG_B_AUX_P

DP_IG_B_MLN

DP_IG_B_MLPTP_MEM_B_DQS_N

TP_MEM_B_DQS_P

DP_IG_B_HPD



TP_PE_TX_N

TP_PE_RX_N

TP_PE_TX_P

TP_PE_RX_P

USB_PCH_4_P

USB_PCH_6_N

USB_PCH_6_P

USB_PCH_11_P

USB_PCH_12_P

USB_PCH_12_N

USB_PCH_13_P

USB_PCH_13_N

TP_PCH_CLKOUT_DPP


TP_PCIE2_D2RN

TP_PCIE1_D2RP

TP_CRT_IG_DDC_CLK

TP_PCIE1_R2D_CP

DP_IG_B_AUX_N

MAKE_BASE=TRUENC_PCIE2_R2D_PNX

NO_TEST=TRUE

NO_TEST=TRUENC_PCIE1_D2RNXMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_B_DQSNX

MAKE_BASE=TRUENC_CPU_RSVD

NO_TEST=TRUE

NC_PCH_RESERVE_6NO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_SATA_C_R2D_CNXMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_D_R2D_CNX

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_PWM0

NC_HDA_SDIN3MAKE_BASE=TRUE NO_TEST=TRUE

NC_PCH_FDI_INTMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SDVO_TVCLKINNX

MAKE_BASE=TRUENC_PCH_FDI_FSYNC

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_D_AUXPX

MAKE_BASE=TRUE NO_TEST=TRUENC_CPU_FDI_LSYNC

NO_TEST=TRUEMAKE_BASE=TRUENC_CPU_FDI_FSYNC

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_FDI_RPX

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_FDI_RNX

NO_TEST=TRUEMAKE_BASE=TRUENC_CPU_FDI_TPX

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_L_BKLTEN

NC_PCH_L_VDD_ENMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_CLK33M_OUT2

MAKE_BASE=TRUENC_PCH_CL_CLK1

NO_TEST=TRUE

NC_PCH_L_BKLTCTLNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCI_CLK33M_OUT3

NO_TEST=TRUE

MAKE_BASE=TRUENC_PCH_CL_RST1

NO_TEST=TRUE

NO_TEST=TRUENC_PCH_CL_DATA1MAKE_BASE=TRUE

NO_TEST=TRUENC_PCH_SSTMAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCH_PWM3

NO_TEST=TRUE

NO_TEST=TRUENC_PCH_PWM2MAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_PWM1

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_D_AUXNX

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_D_MLPX

NC_PCH_FDI_LSYNCMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_CPU_FDI_INTMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_CPU_FDI_TNX

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_RESERVE_17

NO_TEST=TRUENC_PCH_RESERVE_18MAKE_BASE=TRUE


NC_PCH_RESERVE_13MAKE_BASE=TRUE NO_TEST=TRUE







MAKE_BASE=TRUENC_PCH_RESERVE_5

NO_TEST=TRUE


MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_RESERVE_4


NO_TEST=TRUE



MAKE_BASE=TRUE NO_TEST=TRUENC_SDVO_STALLNX

NC_DP_IG_C_HPDNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_DP_IG_D_CTRL_CLKMAKE_BASE=TRUE

NC_DP_IG_D_HPDNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_D_MLNX

NO_TEST=TRUENC_DP_IG_C_CTRL_CLKMAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATANO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_MLPX

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_MLNX

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_D2RPX

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_D2RNXMAKE_BASE=TRUE NO_TEST=TRUENC_SATA_F_R2D_CPX

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_CTRL_CLK

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_MLPXMAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_B_MLNX

NC_CRT_IG_DDC_CLKNO_TEST=TRUEMAKE_BASE=TRUE

NC_CRT_IG_VSYNCNO_TEST=TRUEMAKE_BASE=TRUE

NC_CRT_IG_BLUEMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_HSYNC

NC_CRT_IG_REDNO_TEST=TRUEMAKE_BASE=TRUE

NC_CRT_IG_GREENNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_E_D2RNXMAKE_BASE=TRUE NO_TEST=TRUENC_SATA_E_R2D_CPX

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_D_D2RPX

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_D_D2RNXMAKE_BASE=TRUE NO_TEST=TRUENC_SATA_D_R2D_CPX

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_C_D2RNX

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_C_D2RPX

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP19MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP18MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP17MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP16MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP15

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP13


MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP12MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP11MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP10MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP9MAKE_BASE=TRUENC_PCH_TP8

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP7MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP6MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_TP5MAKE_BASE=TRUENC_PCH_TP4

NO_TEST=TRUE

NO_TEST=TRUENC_PCH_TP1MAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCH_TP2

NO_TEST=TRUE


NC_CRT_IG_DDC_DATANO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_AUXPX

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_HPD

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_AUXPX

NC_PCI_ADNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCI_PARMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_PCI_C_BE_LMAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCI_RESET_L

NO_TEST=TRUE

NC_PCI_GNT0_LNO_TEST=TRUEMAKE_BASE=TRUE

NC_LPC_DREQ0_LNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_INIT3V3_L

NC_HDA_SDIN1MAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_HDA_SDIN2MAKE_BASE=TRUE

NC_CPU_RSVDMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE NO_TEST=TRUENC_SDVO_STALLPX

MAKE_BASE=TRUE NO_TEST=TRUENC_SDVO_INTNX

MAKE_BASE=TRUENC_MEM_A_DQ_CB

NO_TEST=TRUE

NC_MEM_B_DQ_CBMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SDVO_TVCLKINPX

MAKE_BASE=TRUENC_SDVO_INTPX

NO_TEST=TRUE




NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_E_D2RPX

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_R2D_CNX



NO_TEST=TRUE



NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_E_R2D_CNX







NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_CTRL_DATA

MAKE_BASE=TRUENC_MEM_A_DQSNX

NO_TEST=TRUE

NC_MEM_A_DQSPXMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_AUXNX

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_C_R2D_CPX

MAKE_BASE=TRUETP_CPU_CFG

MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_B_DQSPX

MAKE_BASE=TRUENC_PCIE_CLK100M_PE4PX

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4NXNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5PXNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6NXMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_PCIE_CLK100M_PE6PXMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7PXMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_PE7NX

MAKE_BASE=TRUE NO_TEST=TRUENC_PE_RNXMAKE_BASE=TRUE NO_TEST=TRUENC_PE_TPX

NO_TEST=TRUEMAKE_BASE=TRUENC_PE_RPX

NC_USB_PCH_4NXNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB_PCH_4PXNO_TEST=TRUEMAKE_BASE=TRUE


NC_USB_PCH_5NXMAKE_BASE=TRUE NO_TEST=TRUE



NO_TEST=TRUEMAKE_BASE=TRUENC_USB_PCH_11PX


NC_USB_PCH_12PXMAKE_BASE=TRUE NO_TEST=TRUE


NC_USB_PCH_13PXMAKE_BASE=TRUE NO_TEST=TRUE


NC_PCH_CLKOUT_DPNXNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE2_D2RNX

NO_TEST=TRUENC_PCIE2_D2RPXMAKE_BASE=TRUE

NC_PCIE1_D2RPXNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE1_R2D_CNX

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE1_R2D_CPX


NC_PCH_CLKOUT_DPPXNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCH_CLKOUT_DPN

USB_PCH_4_N

USB_PCH_5_N

USB_PCH_5_P

USB_PCH_11_N

NO_TEST=TRUENC_PCH_GPIO65_CLKOUTFLEX1MAKE_BASE=TRUE

NO_TEST=TRUENC_PCH_GPIO66_CLKOUTFLEX2MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCH_GPIO67_CLKOUTFLEX3TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1NO_TEST=TRUEMAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO64_CLKOUTFLEX0

PCH_CLK25M_XTALOUTNO_TEST=TRUE

NC_PCH_CLK25M_XTALOUTMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE0PXMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCIE_CLK100M_PE0NXNO_TEST=TRUEMAKE_BASE=TRUE




prefsb

051-9504

7.0.0

8 OF 143

8 OF 117

12

12

18

18

20

20

21

21

19

19

18

21

18

18

18

18

19

19

18

18

12

10

10

10

18

18

18

18

18

12

21

18

19

19

19

19

19

10

10

19

19

10

10

10

18

18

18

19

18

18

19

19

19

19

19

19

18

21

21

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

18

19

19

19

19

19

19

18

19

19

19

19

19

18

18

18

18

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

18

21 18

18

19

19

19

18

19

18

19

18

19

19

18

21

18

19

20

20

20

20

20

19

19

19

19

19 12

12

19

21

21

10

10

10

10

20

20

20

20

20

20

20

20

18

21

18

18

19

18

19

18

18

20

20

20

20

18

18

18

18

18

18

18

18

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



ALIASES (BLANK)

SYNC_MASTER=K70_MLB SYNC_DATE=08/23/2011

Signal Aliases

prefsb

051-9504

7.0.0

9 OF 143

9 OF 117

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DMI_TX_1*

PE_TX_3*

PE_TX_3

PE_TX_2*

PE_TX_2

PE_TX_1*

PE_TX_1

PE_TX_0*

PE_TX_0

PE_RX_3*

PE_RX_3

PE_RX_2*

PE_RX_2

PE_RX_1*

PE_RX_1

PE_RX_0*

PE_RX_0

PEG_TX_15*

PEG_TX_15

PEG_TX_14*

PEG_TX_14

PEG_TX_13*

PEG_TX_13

PEG_TX_12*

PEG_TX_12

PEG_TX_11*

PEG_TX_11

PEG_TX_10*

PEG_TX_10

PEG_TX_9*

PEG_TX_9

PEG_TX_8*

PEG_TX_8

PEG_TX_7*

PEG_TX_7PEG_TX_6

PEG_TX_5*

PEG_TX_5

PEG_TX_4*

PEG_TX_4

PEG_TX_3*

PEG_TX_3

PEG_TX_2*

PEG_TX_2

PEG_TX_1*

PEG_TX_1

PEG_TX_0*

PEG_TX_0

PEG_RX_15*

PEG_RX_15

PEG_RX_13*

PEG_RX_12

PEG_RX_11*

PEG_RX_11PEG_RX_10PEG_RX_9PEG_RX_8PEG_RX_7PEG_RX_6PEG_RX_5

PEG_RX_4*

PEG_RX_4

PEG_RX_3*

PEG_RX_3PEG_RX_2

PEG_RX_1*

PEG_RX_0

FDI_TX_7*

FDI_TX_7

FDI_TX_6*

FDI_TX_6

FDI_TX_5*

FDI_TX_5

FDI_TX_4*

FDI_TX_4

FDI_TX_3*

FDI_TX_3

FDI_TX_2*

FDI_TX_2

FDI_TX_1*

FDI_TX_1

FDI_TX_0*

FDI_TX_0

FDI_LSYNC_1FDI_LSYNC_0

FDI_FSYNC_1FDI_FSYNC_0

DMI_TX_3*

DMI_TX_3

DMI_TX_2*

DMI_TX_2DMI_TX_1

DMI_TX_0*

DMI_TX_0

DMI_RX_3*

DMI_RX_3

DMI_RX_2*

DMI_RX_2DMI_RX_1

DMI_RX_0*

FDI_COMPIOFDI_ICOMPO

FDI_INT

PEG_COMPIPEG_ICOMPO

PEG_RX_1

PEG_RX_14*

PEG_RX_12*

PEG_RX_6*

PEG_RX_13PEG_RX_14

PEG_RCOMPO

PEG_RX_10*PEG_RX_9*PEG_RX_8*PEG_RX_7*

PEG_RX_2*

PEG_RX_0*

PEG_RX_5*

PEG_TX_6*

DMI_RX_0

DMI_RX_1*

SYM 1 OF 10

FLEXIBLE DISPLAY INTERFACE

PCI EXPRESS -- GRAPHICS

DMI

PCI EXPRESS

RSVD_NCTF_AV1RSVD_NCTF_AW2RSVD_NCTF_AY3RSVD_NCTF_B39

NCTF_AW38NCTF_AU40NCTF_D1NCTF_C2NCTF_A38

CFG_8

RSVD_J34RSVD_J33RSVD_J31

CFG_0CFG_1CFG_2CFG_3CFG_4CFG_5CFG_6CFG_7

CFG_9CFG_10CFG_11CFG_12CFG_13CFG_14CFG_15CFG_16CFG_17

RSVD_K9RSVD_K31RSVD_K34RSVD_L9RSVD_L31RSVD_L33RSVD_L34RSVD_M34RSVD_N33RSVD_N34

RSVD_P35RSVD_P37RSVD_P39RSVD_R34RSVD_R36RSVD_R38RSVD_R40RSVD_AB6RSVD_AB7RSVD_AD34RSVD_AD35RSVD_AD37RSVD_AE6RSVD_AF4RSVD_AG4RSVD_AJ11RSVD_AJ29RSVD_AJ30RSVD_AJ31RSVD_AN20RSVD_AP20RSVD_AT11RSVD_AT14RSVD_AU10RSVD_AV34RSVD_AW34RSVD_AY10

RSVD_J9RSVD_H8RSVD_H7

RSVD_C38

RSVD_D38RSVD_C39

SYM 5 OF 10

RESERVED

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(Available for Workstation only)

CFG [6:5] PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = 1 X8, 2 X4

CFG [3] PCIE STATIC X4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [1:0] RESERVED CONFIGURATION LANE

( IVY BRIDGE EDS #473717 TABLE 6-5 )

CFG [17:7] RESERVED CONFIGURATION LANE

CFG [4] RESERVED CONFIGURATION LANE

INTEL SUGGESTS TO KEEP THESE TPS

ThermDA

ThermDC

(Unused)

ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE.

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1

CFG [2] PCIE STATIC X16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

19 99

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

75 98

402MF-LF

24.9

1%

PLACE_NEAR=U1000.B4:12.7MM

R1010

1/16W

25 99

25 99

8

8

8

8

25 99

25 99

25 99

25 99

25 99

15 25 99

15 25 99

25 99

15 25 99

15 25 99

25 99

25 99

BGA-SKT-K70IVY-BRIDGE

OMIT_TABLEU1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGEU1000

PLACE_NEAR=U1000.AE2:6.3MM

MF-LF1/16W

402

5%0

R1011

CPU DMI/PEG/FDI/RSVDSYNC_DATE=03/23/2012SYNC_MASTER=D8_ROSITA

CPU_FDI_COMPIO

TP_PE_TX_PTP_PE_TX_P

TP_CPU_FDI_TX_N

PEG_D2R_C_P

CPU_PEG_COMP

PEG_D2R_C_NPEG_D2R_C_NPEG_D2R_C_N

=PPVCCIO_S0_CPU

PEG_D2R_C_P

PEG_D2R_C_NPEG_D2R_C_N

PEG_D2R_C_N

CPU_CFG

TP_PE_RX_P

TP_CPU_FDI_TX_P

TP_CPU_FDI_TX_P

TP_PE_RX_N

TP_PE_RX_N

TP_PE_RX_P

PEG_R2D_P

TP_CPU_FDI_TX_P

PEG_D2R_C_P

TP_PE_TX_P

DMI_S2N_N

DMI_S2N_N

PEG_R2D_P

PEG_R2D_P

PEG_R2D_P

PEG_D2R_C_N

PEG_D2R_C_P

DMI_S2N_P

DMI_N2S_P

PEG_D2R_C_N

CPU_CFG

PEG_D2R_C_N

CPU_CFG

CPU_CFG

TP_CPU_RSVDPEG_D2R_C_N

PEG_D2R_C_P

PEG_D2R_C_N

DMI_S2N_P

TP_CPU_FDI_TX_N

PEG_R2D_P

DMI_N2S_N

TP_CPU_FDI_TX_N

TP_CPU_RSVD

DMI_N2S_N

PEG_D2R_C_N

TP_CPU_FDI_FSYNC

TP_PE_RX_P

TP_PE_TX_N

DMI_N2S_P

DMI_N2S_N

PEG_R2D_PPEG_R2D_PPEG_R2D_P

DMI_N2S_P

PEG_R2D_N

PEG_D2R_C_P

PEG_D2R_C_P

CPU_CFGCPU_CFG

CPU_CFG

DMI_S2N_N

DMI_S2N_P

TP_CPU_FDI_LSYNC

TP_CPU_FDI_TX_P

PEG_R2D_P

PEG_R2D_N

TP_CPU_FDI_TX_P

TP_PE_TX_N

CPU_CFG

CPU_CFG

CPU_CFG

TP_CPU_RSVD

PEG_D2R_C_P

PEG_R2D_P

PEG_R2D_P

PEG_R2D_N

TP_PE_TX_P

TP_CPU_RSVDTP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD

TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD


TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD

CPU_CFGCPU_CFG

CPU_CFG

TP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_NCTFTP_CPU_NCTF

TP_CPU_NCTF

CPU_CFG

CPU_CFG

TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD

TP_CPU_RSVD


TP_CPU_RSVD

TP_PE_TX_N

TP_CPU_FDI_TX_P

DMI_S2N_P

TP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_NCTF

TP_CPU_NCTF

TP_CPU_RSVD

PEG_R2D_PPEG_R2D_P

TP_CPU_RSVD

TP_CPU_RSVD

TP_CPU_RSVD_NCTFTP_CPU_RSVD_NCTFTP_CPU_RSVD_NCTFTP_CPU_RSVD_NCTF

TP_CPU_RSVD


CPU_CFGCPU_CFG

DMI_N2S_N

TP_CPU_FDI_TX_P

TP_CPU_FDI_TX_N

PEG_R2D_N

TP_PE_RX_P

TP_CPU_FDI_INT

TP_CPU_FDI_TX_NTP_CPU_FDI_TX_N

PEG_D2R_C_NPEG_D2R_C_N

PEG_R2D_N

PEG_R2D_N

PEG_R2D_P

TP_CPU_FDI_LSYNC

TP_CPU_FDI_FSYNC

TP_CPU_FDI_TX_P PEG_D2R_C_P

PEG_R2D_N

TP_CPU_RSVD

PEG_D2R_C_N

TP_CPU_FDI_TX_N

PEG_D2R_C_P

PEG_D2R_C_P

PEG_R2D_N

PEG_R2D_PTP_PE_TX_N

PEG_R2D_P

PEG_R2D_N

PEG_R2D_N

PEG_R2D_N

DMI_N2S_P

PEG_R2D_NPEG_R2D_N

PEG_R2D_N

PEG_D2R_C_P

PEG_D2R_C_PPEG_D2R_C_P

DMI_S2N_N

PEG_R2D_N

PEG_R2D_N

TP_CPU_FDI_TX_N

PEG_D2R_C_P

PEG_D2R_C_P

NC_SNS_CPU_THERMDPNO_TEST=TRUE

NC_SNS_CPU_THERMDNNO_TEST=TRUE

CPU_CFG

PEG_D2R_C_N

TP_PE_RX_NTP_PE_RX_N

prefsb

051-9504

7.0.0

10 OF 143

10 OF 117

1 2

W8

U6

U5

R5

R6

T8

T7

P7

P8

U1

U2

T3

T4

R1

R2

P4

P3

N6

N5

L5

L6

M7

M8

J6

J5

K8

K7

G6

G5

G9

G10

F7

F8

E5

E6D3

D7

D8

J13

J14

F11

F12

G13

G14

E13

E14

C14

C13

N2

N1

L2

K3

J2

J1H3G2F4E2A5C6

B7

B8

E9

E10C10

D11

B11

AG1

AG2

AF2

AF3

AE8

AE7

AD6

AD7

AD3

AD4

AD1

AD2

AC3

AC2

AC7

AC8

AE4AC4

AE5AC5

AA8

AA7

Y7

Y6W7

V6

V7

AA5

AA4

Y4

Y3V3

W4

AE2AE1

AG3

B4B5

D12

M4

K4

A6

L1M3

C4

H4G1F3E1

C9

B12

C5

C3

W5

V4

AV1AW2AY3B39

AW38AU40D1C2A38

J38

J34J33J31

H36J36J37K36L36N35L37M36

L35M38N36N38N39N37N40G37G36

K9K31K34L9L31L33L34M34N33N34

P35P37P39R34R36R38R40AB6AB7AD34AD35AD37AE6AF4AG4AJ11AJ29AJ30AJ31AN20AP20AT11AT14AU10AV34AW34AY10

J9H8H7

C38

D38C39

1

2

99

8

8

8

98

6 11 13 16 28 66

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

BI

SA_DIMM_VREFDQSB_DIMM_VREFDQ

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMSTRST*

TDITDO

DBR*

BPM[0]*BPM[1]*BPM[2]*BPM[3]*BPM[4]*BPM[5]*BPM[6]*BPM[7]*

TCK

PRDY*

BCLK_ITP

BCLK_0

BCLK_ITP*

BCLK_0*

UNCOREPWRGOOD

SKTOCC*

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

PROC_SEL

SYM 2 OF 10

CLOCKS

THERMAL

DDR3 MISC

PWR MGMT

JTAG & BPM

OUT

IN

OUT

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

OUT

BI

BI

BI

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



BASED ON INTEL MOBILE SOLUTION

FROM PCH

25 99

25 99

25 99

25 99

25 99

R11111/16W5%

402MF-LF

1K

19 28 99

21 25 28 99

34 106

34 106

28 99

15 99

15 99

19 99

48 99

47 48 66 99

21 47 48 99 R1124

1/16W5%

402

75

PLACE_NEAR=U1000.F36:50mm

MF-LF

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

R11411/16W1%1K

402MF-LF

R11401/16W1%

402MF-LF

1K

10%X7R-CERM16V0.1UFC1140

0402

48 99

R1102MF-LF 5%0 1/16W

402

R11011/16W

5%

402MF-LF

51

25 99

25 99

25 99

25 99

25 99

25 99

25 99

R11201/16W

1%

402MF-LF

200

R1121130

MF-LF402

1%1/16W

18 99

18 99

19 99

R1125

4021/16W5%

MF-LF

4326 99

64 99

25 99

25 99

25 99

25 99

SYNC_DATE=03/15/2012SYNC_MASTER=D7_MLB

CPU CLOCK/MISC/JTAG

CPU_DDR_VREF

=PP1V5_S0_CPU_MEM

DMI_CLK100M_CPU_N

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

ITPCPU_CLK100M_P

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_LXDP_BPM_L

XDP_DBRESET_L

XDP_CPU_TDOXDP_CPU_TDI

XDP_CPU_TRST_LXDP_CPU_TMS

XDP_CPU_PREQ_L

=PP1V5_S0_CPU_MEM

=PPVCCIO_S0_CPU

PM_MEM_PWRGD_R

CPU_DDR_VREF

PM_MEM_PWRGD

CPU_RESET_L

CPU_DIMM_VREF_DAC_ACPU_DIMM_VREF_DAC_B

CPU_MEM_RESET_L

PLT_RESET_LS1V05_L

PM_SYNC

CPU_PWRGD

CPU_THRMTRIP_L

CPU_PECI

CPU_CATERR_L

CPU_PROC_SEL

CPU_SKTOCC_L

CPU_PROCHOT_R_L

=PPVCCIO_S0_CPU

CPU_PROCHOT_L

prefsb

051-9504

7.0.0

11 OF 143

11 OF 117

1

2

1

2

AH4AH1

AJ22

AW18

AJ19

E38

K40

L38J39

L40L39

E39

H40H38G38G40G39F38E40F40

M40

K38

C40

W2

D40

W1

J40

AJ33

F36

G35

E37

J35

H34

K32

1

2

1

2

2

1

12

1

2

1

212

12

11 106

6 11 13 16

6 11 13 16

6 10 11 13 16 28 66

99

11 106

99

99

6 10 11 13 16 28 66

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT OUT

SA_DQ_32SA_DQ_33

SA_DQS_8*

SA_BS_2

SA_CAS*

SA_BS_1SA_BS_0

SA_DQ_63SA_DQ_62SA_DQ_61SA_DQ_60

SA_DQ_9

SA_CK_1

SA_ODT_2SA_ODT_1SA_ODT_0

SA_RAS*SA_WE*

SA_CK_0SA_CK_0*

SA_CK_1*

SA_CK_2SA_CK_2*

SA_CK_3SA_CK_3*

SA_CKE_0

SA_CKE_1

SA_CKE_2

SA_CKE_3

SA_CS_0*SA_CS_1*SA_CS_2*SA_CS_3*

SA_DQ_0SA_DQ_1

SA_DQ_10SA_DQ_11SA_DQ_12SA_DQ_13SA_DQ_14SA_DQ_15SA_DQ_16SA_DQ_17SA_DQ_18SA_DQ_19

SA_DQ_2


SA_DQ_3

SA_DQ_30SA_DQ_31

SA_DQ_34SA_DQ_35SA_DQ_36SA_DQ_37SA_DQ_38SA_DQ_39

SA_DQ_4


SA_DQ_5


SA_DQ_6SA_DQ_7SA_DQ_8

SA_DQS_0

SA_DQS_0*

SA_DQS_1

SA_DQS_1*

SA_DQS_2

SA_DQS_2*

SA_DQS_3

SA_DQS_3*

SA_DQS_4

SA_DQS_4*

SA_DQS_5

SA_DQS_5*

SA_DQS_6

SA_DQS_6*

SA_DQS_7

SA_DQS_7*

SA_DQS_8

SA_ECC_CB_0SA_ECC_CB_1SA_ECC_CB_2SA_ECC_CB_3SA_ECC_CB_4SA_ECC_CB_5SA_ECC_CB_6SA_ECC_CB_7

SA_MA_0SA_MA_1

SA_MA_10SA_MA_11SA_MA_12SA_MA_13SA_MA_14SA_MA_15

SA_MA_2SA_MA_3SA_MA_4SA_MA_5SA_MA_6SA_MA_7SA_MA_8SA_MA_9

SA_ODT_3

SYM 3 OF 10

DDR SYSTEM MEMORY A

SB_CK_1*

SB_DQS_3*

SB_DQ_33

SB_DQS_4

SB_DQS_2

SB_DQS_8*

SB_CKE_3

SB_CS_0*SB_CS_1*SB_CS_2*SB_CS_3*

SB_CAS*SB_RAS*SB_WE*

SB_BS_0SB_BS_1SB_BS_2

SB_CK_0SB_CK_0*

SB_CK_1

SB_CK_2SB_CK_2*

SB_CK_3SB_CK_3*

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_DQ_0SB_DQ_1

SB_DQ_10SB_DQ_11SB_DQ_12SB_DQ_13SB_DQ_14SB_DQ_15SB_DQ_16SB_DQ_17SB_DQ_18SB_DQ_19

SB_DQ_2


SB_DQ_3

SB_DQ_30SB_DQ_31SB_DQ_32

SB_DQ_34SB_DQ_35SB_DQ_36SB_DQ_37SB_DQ_38SB_DQ_39

SB_DQ_4


SB_DQ_5


SB_DQ_6

SB_DQ_60SB_DQ_61SB_DQ_62SB_DQ_63

SB_DQ_7SB_DQ_8SB_DQ_9

SB_DQS_0

SB_DQS_0*

SB_DQS_1

SB_DQS_1*SB_DQS_2*

SB_DQS_3

SB_DQS_4*

SB_DQS_5

SB_DQS_5*

SB_DQS_6

SB_DQS_6*

SB_DQS_7

SB_DQS_7*

SB_DQS_8

SB_ECC_CB_0SB_ECC_CB_1SB_ECC_CB_2SB_ECC_CB_3SB_ECC_CB_4SB_ECC_CB_5SB_ECC_CB_6SB_ECC_CB_7

SB_MA_0SB_MA_1

SB_MA_10SB_MA_11SB_MA_12SB_MA_13SB_MA_14SB_MA_15

SB_MA_2SB_MA_3SB_MA_4SB_MA_5SB_MA_6SB_MA_7SB_MA_8SB_MA_9

SB_ODT_0SB_ODT_1SB_ODT_2SB_ODT_3

SYM 4 OF 10

DDR SYSTEM MEMORY B

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 30 97

29 97

29 97

29 97

29 97

29 97

29 97

29 97

29 97

29 97

29 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 97

31 97

31 97

31 97

31 97

31 97

31 97

31 97

31 97

31 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

33 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

31 32 97

30 97

30 97

30 97

30 97

30 97

30 97

30 97

30 97

30 97

30 97

32 97

32 97

32 97

32 97

32 97

32 97

32 97

32 97

32 97

32 97

29 30 97 31 32 97

U1000BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGEU1000BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

SYNC_DATE=03/15/2012SYNC_MASTER=D7_MLB

CPU DDR3 INTERFACES

MEM_B_DQ

MEM_A_CLK_P

MEM_A_DQ

MEM_A_DQ

MEM_A_DQS_P

MEM_A_DQ MEM_B_DQMEM_B_DQ

MEM_A_DQ

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_DQ

MEM_A_ODT

MEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_A

MEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_AMEM_A_A

MEM_A_AMEM_A_A

TP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CBTP_MEM_A_DQ_CB

TP_MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_NMEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQS_N

MEM_A_DQS_P

MEM_A_DQ

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_DQMEM_A_DQ

MEM_A_CS_LMEM_A_CS_L

MEM_A_CS_L

MEM_A_CKE

MEM_A_CLK_P

MEM_A_CLK_N

MEM_A_WE_LMEM_A_RAS_L

MEM_A_ODTMEM_A_ODT

MEM_A_DQMEM_A_DQMEM_A_DQMEM_A_DQ

MEM_A_BAMEM_A_BA

MEM_A_CAS_L

MEM_A_BA

TP_MEM_A_DQS_NMEM_A_DQMEM_A_DQ

MEM_B_ODTMEM_B_ODTMEM_B_ODTMEM_B_ODT

MEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_A

MEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_AMEM_B_A

MEM_B_AMEM_B_A

TP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CBTP_MEM_B_DQ_CB

TP_MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQMEM_B_DQMEM_B_DQ


MEM_B_DQ

MEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQ


MEM_B_DQ

MEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQ

MEM_B_DQ

MEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQ


MEM_B_DQ

MEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQ

MEM_B_DQ

MEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQMEM_B_DQ

MEM_B_DQ

MEM_B_DQMEM_B_DQ

MEM_B_CKE

MEM_B_CLK_NMEM_B_CLK_P

MEM_B_BAMEM_B_BAMEM_B_BA

MEM_B_WE_LMEM_B_RAS_LMEM_B_CAS_L

TP_MEM_B_DQS_N

MEM_B_DQS_P

MEM_B_DQS_P

MEM_B_DQ

MEM_B_DQS_N

MEM_B_CLK_N

MEM_B_DQ

MEM_B_DQS_N

MEM_A_DQ

MEM_A_DQ

MEM_B_CLK_PMEM_A_CLK_NMEM_A_CLK_P

MEM_A_CKE

MEM_A_CLK_N

MEM_A_CKE

MEM_A_CLK_PMEM_A_CLK_N

MEM_A_CKE

MEM_A_CS_L

MEM_A_ODT

MEM_B_DQMEM_B_CS_LMEM_B_CS_LMEM_B_CS_L

MEM_B_CKE

MEM_B_CLK_N

MEM_B_CKE

MEM_B_CS_L

MEM_B_CLK_P

MEM_B_CKE

MEM_B_CLK_N

MEM_B_CLK_P

prefsb

051-9504

7.0.0

12 OF 143

12 OF 117

AU35AW37

AV12

AV20

AV30

AW28AY29

AE40AE39AG38AG39

AN4

AU24

AU30AU32AV31

AU28AW29

AY25AW25

AU25

AW27AY27

AV26AW26

AV19

AT19

AU18

AV18

AU29AV32AW30AU33

AJ3AJ4

AR3AR4AN2AN3AR2AR1AV2AW3AV5AW5

AL3

AU2AU3AU5AY5AY7AU7AV9AU9AV7AW7

AL4

AW9AY9

AU39AU36AW35AY36AU38AU37

AJ2

AR40AR37AN38AN37AR39AR38AN39AN40AL40AL37

AJ1

AJ38AJ37AL39AL38AJ39AJ40AG40AG37AE38AE37

AL2AL1AN1

AK3

AK2

AP3

AP2

AW4

AV4

AV8

AW8

AV37

AV36

AP38

AP39

AK38

AK39

AF38

AF39

AV13

AU12AU14AW13AY13AU13AU11AY12AW12

AV27AY24

AV28AU21AT21AW32AU20AT20

AW24AW23AV23AT24AT23AU22AV22AT22

AW33

AK20

AN12

AR29

AN29

AR8

AN15

AV15

AN25AN26AL25AT26

AK25AP24AR25

AP23AM24AW17

AL21AL22

AL20

AL23AM22

AP21AN21

AU16

AY15

AW15

AG7AG8

AM10AL10AL6AM6AL9AM9AP7AR7

AP10AR10

AJ9

AP6AR6AP9AR9

AM12AM13AR13AP13AL12AL13

AJ8

AR12AP12AR28

AL28AL29AP28AP29AM28AM29

AG5

AP32AP31AP35AP34AR32AR31AR35AR34AM32AM31

AG6

AL35AL32AM34AL31AM35AL34AH35AH34AE34AE35

AJ6

AJ35AJ34AF33AF35

AJ7AL7AM7

AH7

AH6

AM8

AL8AP8

AN13

AN28

AP33

AR33

AL33

AM33

AG35

AG34

AN16

AL16AM16AP16AR16AL15AM15AR15AP15

AK24AM20

AN23AU17AT18AR26AY16AV16

AM19AK18AP19AP18AM18AL18AN18AY17

AL26AP26AM26AK26

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

VCCIO_31

VCCIO_44

VCCIO_SEL

VCCIO_45

VCCIO_30

VSSAXG_SENSEVCCAXG_SENSE

VSSIO_SENSEVCCIO_SENSE

VCC_024

VCC_038

VCCIO_42

VCCIO_29VCCIO_28

VCCIO_09

VCC_001VCC_002VCC_003VCC_004

VCCIO_27

VCC_012

VCC_015

VCC_005VCC_006VCC_007VCC_008VCC_009VCC_010VCC_011

VCC_013VCC_014

VCC_016VCC_017VCC_018


VCC_025VCC_026VCC_027VCC_028VCC_029VCC_030VCC_031VCC_032VCC_033VCC_034VCC_035VCC_036VCC_037

VCC_039VCC_040VCC_041VCC_042VCC_043VCC_044VCC_045VCC_046VCC_047VCC_048VCC_049VCC_050VCC_051VCC_052

VCC_057VCC_058VCC_059VCC_060VCC_061VCC_062VCC_063VCC_064VCC_065VCC_066VCC_067VCC_068VCC_069VCC_070

VCCIO_02VCCIO_01

VCCIO_20

VCCIO_26

VCCIO_33VCCIO_34VCCIO_35VCCIO_36

VCCIO_40

VCCIO_43

VCCIO_04VCCIO_05VCCIO_06VCCIO_07VCCIO_08

VCCIO_10VCCIO_11VCCIO_12VCCIO_13VCCIO_14

VCCIO_16

VCCIO_19

VCCSA_SENSE

VIDALERT*

VIDSCLK

VIDSOUT

VSS_SENSE

VCCIO_41

VCC_SENSE


VCCIO_03

VCC_019

VCCIO_15

VCCIO_17VCC

Date post:	13-Feb-2021
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