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DAC7611
12-Bit Serial InputDIGITAL-TO-ANALOG CONVERTER
DESCRIPTIONThe DAC7611 is a 12-bit digital-to-analog converter(DAC) with guaranteed 12-bit monotonicity perfor-mance over the industrial temperature range. It re-quires a single +5V supply and contains an input shiftregister, latch, 2.435V reference, DAC, and high speedrail-to-rail output amplifier. For a full-scale step, theoutput will settle to 1 LSB within 7µs. The deviceconsumes 2.5mW (0.5mA at 5V).
The synchronous serial interface is compatible with awide variety of DSPs and microcontrollers. Clock(CLK), serial data in (SDI), and load strobe (LD)comprise the serial interface. In addition, two controlpins provide a chip select (CS) function and an asyn-chronous clear (CLR) input. The CLR input can beused to ensure that the DAC7611 output is 0V onpower-up or as required by the application.
The DAC7611 is available in an 8-lead SOIC or 8-pinplastic DIP package and is fully specified over theindustrial temperature range of –40°C to +85°C.
12-BIT LINEARITY AND MONOTONICITYOVER INDUSTRIAL TEMP RANGE
ASYNCHRONOUS RESET TO 0V
3-WIRE INTERFACE: Up to 20MHz Clock
ALTERNATE SOURCE TO DAC8512
12-Bit DACRef
DAC Register
Serial Shift Register
12
12
CLR
LD
CS
CLK
SDI
VDD
GND
VOUT
DAC7611
APPLICATIONS PROCESS CONTROL
DATA ACQUISITION SYSTEMS
CLOSED-LOOP SERVO-CONTROL
PC PERIPHERALS
PORTABLE INSTRUMENTATION
SBAS075
®
2DAC7611
SPECIFICATIONSELECTRICALAt TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.
DAC7611P, U DAC7611PB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DYNAMIC PERFORMANCESettling Time(2) (tS) To ±1 LSB of Final Value 7 µsDAC Glitch 15 nV-sDigital Feedthrough 2 nV-s
POWER SUPPLYVDD +4.75 +5.0 +5.25 VIDD VIH = 5V, VIL = 0V, No Load, at Code 000H 0.5 1 mA
Power Dissipation VIH = 5V, VIL = 0V, No Load 2.5 5 mWPower Supply Sensitivity ∆VDD = ±5% 0.001 0.004 %/%
TEMPERATURE RANGESpecified Performance –40 +85 °C
Same specification as for DAC7611P, U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions wherethe final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
®
3 DAC7611
1
2
3
4
8
7
6
5
VDD
CS
CLK
SDI
VOUT
GND
CLR
LD
DAC7611
PIN CONFIGURATION
Top View DIP
PIN CONFIGURATION
Top View SOIC
VDD to GND .......................................................................... –0.3V to 6VDigital Inputs to GND ............................................. –0.3V to VDD + 0.3VVOUT to GND ........................................................... –0.3V to VDD + 0.3VPower Dissipation ........................................................................ 325mWThermal Resistance, θJA ............................................................ 150°C/WMaximum Junction Temperature ................................................. +150°COperating Temperature Range ...................................... –40°C to +85°CStorage Temperature Range ........................................ –65°C to +150°CLead Temperature (soldering, 10s) ............................................. +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumconditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS (1)
1
2
3
4
8
7
6
5
VDD
CS
CLK
SDI
VOUT
GND
CLR
LD
DAC7611
PIN DESCRIPTION
PIN LABEL DESCRIPTION
1 VDD Power Supply
2 CS Chip Select (active LOW).
3 CLK Synchronous Clock for the Serial Data Input.
4 SDI Serial Data Input. Data is clocked into the internalserial register on the rising edge of CLK.
5 LD Loads the Internal DAC Register. NOTE: The DACregister is a transparent latch and is transparentwhen LD is LOW (regardless of the state of CS orCLK).
6 CLR Asynchronous Input to Clear the DAC Register.When CLR is strobbed LOW, the DAC register is setto 000H and the output voltage to 0V.
7 GND Ground
8 VOUT Voltage Output. Fixed output voltage range of ap-proximately 0V to 4.095V (1mV/LSB). The internalreference maintains this output range over time,temperature, and power supply variations (withinthe values defined in the specifications section).
ELECTROSTATICDISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brownrecommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage.
ESD damage can range from subtle performance degrada-tion to complete device failure. Precision integrated circuitsmay be more susceptible to damage because very smallparametric changes could cause the device not to meet itspublished specifications.
" " " " " " DAC7611U/2K5 Tape and ReelDAC7611PB ±1 ±1 –40°C to +85°C 8-Pin DIP 006 DAC7611PB RailsDAC7611UB ±1 ±1 –40°C to +85°C 8-Lead SOIC 182 DAC7611UB Rails
" " " " " " DAC7611UB/2K5 Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) areavailable only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7611/2K5” will get a single2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
4DAC7611
EQUIVALENT INPUT LOGIC
DACRegister
Serial Shift Register
DACSwitches
Force to 000H
Transparent
Latched
Data
12
12
ESD protectiondiodes to VDD
and GND
CLR
LD
SDI
CS
CLK
®
5 DAC7611
TIMING DIAGRAMS
LOGIC TRUTH TABLE
SERIAL SHIFTCS(1) CLK(1) CLR LD REGISTER DAC REGISTER
H X H H No Change No Change
L L H H No Change No Change
L H H H No Change No Change
L ↑ H H Advanced One Bit No Change
↑ L H H Advanced One Bit No Change
H(2) X H ↓ No Change Changes to Value ofSerial Shift Register
NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggestedin order to avoid to “false clock” from advancing the shift register and changingthe DAC voltage. (3) If data is clocked into the serial register while LD is LOW,the DAC output voltage will change, reflecting the current value of the serialshift register.
TIMING SPECIFICATIONSTA = –40°C to +85°C and VDD = +5V.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tCH Clock Width HIGH 30 ns
tCL Clock Width LOW 30 ns
tLDW Load Pulse Width 20 ns
tDS Data Setup 15 ns
tDH Data Hold 15 ns
tCLRW Clear Pulse Width 30 ns
tLD1 Load Setup 15 ns
tLD2 Load Hold 10 ns
tCSS Select 30 ns
tCSH Deselect 20 ns
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%of +5V) and timed from a voltage level of 1.6V. These parameters areguaranteed by design and are not subject to production testing.
D11
(MSB) (LSB)
SDI
CLK
CS
LD
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tCSS
tLD1 tLD2
tCSH
LD
FS
ZS
CLR
VOUT
tLDW
tS
tCLRW
tS±1 LSBError Band
SDI
CLK
tCL tCH
tDHtDS
®
6DAC7611
TYPICAL PERFORMANCE CURVESAt TA = +25°, and VDD = 5V, unless otherwise specified.
5
4
3
2
1
0
OUTPUT SWING vs LOAD
Out
put V
olta
ge (
V)
Load Resistance (Ω)
10 100 1k 10k 100k
RL tied to +5VData = 000H
RL tied to AGNDData = FFFH
BROADBAND NOISE
Noi
se V
olta
ge (
500µ
V/d
iv)
Time (2ms/div)
Code = FFFH
BW = 2MHz
4.0
3.2
2.4
1.6
0.8
0
SUPPLY CURRENT vs LOGIC INPUT VOLTAGES
uppl
y C
urre
nt (
mA
)
Logic Voltage (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
No Load
70
60
50
40
30
20
10
0
POWER SUPPLY REJECTION vs FREQUENCY
PS
R (
dB)
Frequency (Hz)
10 100 1k 10k 100k 1M
Data = FFFHVDD = 5V
±200mV AC
5.0
4.8
4.6
4.4
4.2
4.0
MINIMUM SUPPLY VOLTAGE vs LOAD
VD
D M
inim
um (
V)
Output Load Current (mA)
0.010 0.100 1.000 10.000
∆VFS = 1 LSBData = FFFH
1k
100
10
1
0.1
0.01
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
Del
ta V
OU
T (
mV
)
Current (mA)
0.001 0.01 0.1 1 10 100
85°C (mV)
–40°C
Data = 000H
25°C
®
7 DAC7611
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°, and VDD = 5V, unless otherwise specified.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT vs TEMPERATURE
Sup
ply
Cur
rent
(m
A)
Temperature (°C)
–50 –25 0 25 50 75 100 125
VLOGIC = 2.4VData = FFFHNo Load
VDD = 4.75V
VDD = 5.0VVDD = 5.25V
RISE TIME DETAIL
Out
put V
olta
ge (
1mV
/div
)
Time (10µs/div)
LD
VOUT
LARGE-SIGNAL SETTLING TIME
1V/d
iv
Time (20µs/div)
CL = 110pFRL = No Load
LD
VOUT
80
60
40
20
0
–20
–40
–60
–80
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
Out
put C
urre
nt (
mA
)
Output Voltage (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
PositiveCurrent
Limit
Data = 800HOutput tied to ISOURCE
NegativeCurrent
Limit
MIDSCALE GLITCH PERFORMANCE
VO
UT (
10m
V/d
iv)
Time (500ns/div)
LD
VOUT
7FFH to 800H
MIDSCALE GLITCH PERFORMANCE
VO
UT (
10m
V/d
iv)
Time (500ns/div)
LD
VOUT
800H to 7FFH
®
8DAC7611
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°, and VDD = 5V, unless otherwise specified.
3
2
1
0
–1
ZERO-SCALE VOLTAGE vs TEMPERATURE
Zer
o-S
cale
(m
V)
Temperature (°C)
–50 0 25–25 50 75 100 125
FALL TIME DETAIL
Out
put V
olta
ge (
1mV
/div
)
Time (10µs/div)
LD
VOUT
10.000
1.000
0.100
0.010
OUTPUT VOLTAGE NOISE vs FREQUENCY
Noi
se (
µV/√
Hz)
Frequency (Hz)
10 100 1k 10k 100k
Data = FFFH
5
4
3
2
1
0
–1
–2
–3
–4
–5
Out
put V
olta
ge C
hang
e (m
V)
Hours of Operation at +150°C
LONG-TERM DRIFT ACCELERATED BY BURN-IN
0 400200 600 800 1000 1200
avg
max
min
120 Units
0
10
20
30
40
50
60
–12 –8 –4 0 4 8 12
T.U.E = ΣINL = ZS + FSSample Size = 300 Units
TA = +25°C
Num
ber
of U
nits
TOTAL UNADJUSTED ERROR HISTOGRAM
4.115
4.110
4.105
4.100
4.095
4.090
4.085
4.080
4.075
FULL-SCALE VOLTAGE vs TEMPERATURE
Ful
l-Sca
le O
utpu
t (V
)
Temperature (°C)
–50 0 25–25 50 75 100 125
No LoadSample Size = 300Avg + 3σ
Avg – 3σ
Avg
®
9 DAC7611
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°, and VDD = 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE(at +85°C)
Line
arity
Err
or (
LSB
s)
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0512 1024 1536 2048 2560 3072 3584 4096
Code
LINEARITY ERROR vs DIGITAL CODE(at +25°C)
Line
arity
Err
or (
LSB
s)
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0512 1024 1536 2048 2560 3072 3584 4096
Code
LINEARITY ERROR vs DIGITAL CODE(at –40°C)
Line
arity
Err
or (
LSB
s)
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0512 1024 1536 2048 2560 3072 3584 4096
Code
®
10DAC7611
clear input (CLR) is provided to simplify start-up or periodicresets. Table I shows the relationship between input codeand output voltage.
The digital data into the DAC7611 is double-buffered. Thismeans that new data can be entered into the DAC withoutdisturbing the old data and the analog output of the con-verter. At some point after the data has been entered into theserial shift register, this data can be transferred into the DACregister. This transfer is accomplished with a HIGH to LOWtransition of the LD pin. However, the LD pin makes theDAC register transparent. If new data is shifted into the shiftregister while LD is LOW, the DAC output voltage willchange as each new bit is entered. To prevent this, LD mustbe returned HIGH prior to shifting in new serial data.
At any time, the contents of the DAC register can be set to000H (analog output equals 0V) by taking the CLR inputLOW. The DAC register will remain at this value until CLRis returned HIGH and LD is taken LOW to allow thecontents of the shift register to be transferred to the DACregister. If LD is LOW when CLR is taken LOW, the DACregister will be set to 000H and the analog output driven to0V. When CLR is returned HIGH, the DAC register will beset to the current value in the serial shift register and theanalog output will respond accordingly.
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage outputdevice that swings between ground and the internal ref-erence voltage. The DAC is realized by a laser-trimmedR-2R ladder network which is switched by N-channelMOSFETs. The DAC output is internally connected tothe rail-to-rail output operational amplifier.
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of theDAC section and provides additional gain to achieve a 0 to4.095V range. The amplifier has low offset voltage, lownoise, and a set gain of 1.682V/V (4.095/2.435). See Figure2 for an equivalent circuit schematic of the analog portion ofthe DAC7611.
FIGURE 2. Simplified Schematic of Analog Portion.
OPERATIONThe DAC7611 is a 12-bit digital-to-analog converter (DAC)complete with a serial-to-parallel shift register, DAC regis-ter, laser-trimmed 12-bit DAC, on-board reference, and arail-to-rail output amplifier. Figure 1 shows the basic opera-tion of the DAC7611.
INTERFACE
Figure 1 shows the basic connection between amicrocontroller and the DAC7611. The interface consists ofa serial clock (CLK), serial data (SDI), and a load strobesignal (LD). In addition, a chip select (CS) input is availableto enable serial communication when there are multipleserial devices. The data format is Straight Binary and isloaded MSB-first into the shift registers. An asynchronous
DAC7611 Full-Scale Range = 4.095VLeast Significant Bit = 1mV
DIGITAL INPUT CODE ANALOG OUTPUTSTRAIGHT BINARY (V) DESCRIPTION
FFFH +4.095 Full Scale801H +2.049 Midscale + 1 LSB800H +2.048 Midscale7FFH +2.047 Midscale – 1 LSB000H 0 Zero Scale
TABLE I. Digital Input Code and Corresponding IdealAnalog Output.
FIGURE 1. Basic Operation of the DAC7611.
2R
2R
2R
R
2R
2R
RR1
R
R2
Output AmplifierR-2R DAC
BandgapReference
2.435V
Buffer
1
2
3
4
8
7
6
5
VOUT
GND
CLR
LD
VDD
CS
CLK
SDI
Serial Clock
Serial Data
Load Strobe
DAC7611
+0.1µF10µF
FromµC
0V to+4.095V
+5V
®
11 DAC7611
The output amplifier has a 7µs typical settling time to ±1LSB of the final value. Note that there are differences in thesettling time for negative-going signals versus positive-going signals.
The rail-to-rail output stage of the amplifier provides thefull-scale range of 0V to 4.095V while operating on a supplyvoltage as low as 4.75V. In addition to its ability to driveresistive loads, the amplifier will remain stable while drivingcapacitive loads of up to 500pF. See Figure 3 for an equiva-lent circuit schematic of the amplifier’s output driver and theTypical Performance Curves section for more informationregarding settling time, load driving capability, and outputnoise.
The DAC7611 power supply should be bypassed as shownin Figure 1. The bypass capacitors should be placed as closeto the device as possible, with the 0.1uF capacitor takingpriority in this regard. The Power Supply Rejection vsFrequency graph in the Typical Performance Curves sectionshows the PSRR performance of the DAC7611. This shouldbe taken into account when using switching power suppliesor DC/DC converters.
In addition to offering guaranteed performance with VDD inthe 4.75V to 5.25V range, the DAC7611 will operate withreduced performance down to 4.5V. Operation between4.5V and 4.75V will result in longer settling time, reducedperformance, and current sourcing capability. Consult theVDD vs Load Current graph in the Typical PerformanceCurves section for more information.
APPLICATIONSPOWER AND GROUNDING
The DAC7611 can be used in a wide variety of situations—from low power, battery operated systems to large-scaleindustrial process control systems. In addition, some appli-cations require better performance than others, or are par-ticularly sensitive to one or two specific parameters. Thisdiversity makes it difficult to define definite rules to followconcerning the power supply, bypassing, and grounding.The following discussion must be considered in relation tothe desired performance and needs of the particular system.
A precision analog component requires careful layout, ad-equate bypassing, and a clean, well-regulated power supply.As the DAC7611 is a single-supply, +5V component, it willoften be used in conjunction with digital logic,microcontrollers, microprocessors, and digital signal proces-sors. The more digital logic present in the design and thehigher the switching speed, the more difficult it will be toachieve good performance.
Because the DAC7611 has a single ground pin, all returncurrents, including digital and analog return currents, mustflow through this pin. The GND pin is also the groundreference point for the internal bandgap reference. Ideally,GND would be connected directly to an analog groundplane. This plane would be separate from the ground con-nection for the digital components until they are connectedat the power entry point of the system (see Figure 4).
The power applied to VDD should be well regulated and low-noise. Switching power supplies and DC/DC converters willoften have high-frequency glitches or spikes riding on theoutput voltage. In addition, digital components can createsimilar high frequency spikes as their internal logic switchesstates. This noise can easily couple into the DAC outputvoltage through various paths between VDD and VOUT.
N-Channel
P-Channel
VDD
VOUT
AGND
FIGURE 3. Simplified Driver Section of Output Amplifier.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar andCMOS sections of the DAC7611 result in a very low powerdevice. Bipolar transistors are used where tight matchingand low noise are needed to achieve analog accuracy, andCMOS transistors are used for logic, switching functionsand for other low power stages.
If power consumption is critical, it is important to keep thelogic levels on the digital inputs (SDI, CLK, CS, LD, CLR)as close as possible to either VDD or ground. This will keepthe CMOS inputs (see “Supply Current vs Logic InputVoltages” in the Typical Performance Curves) from shunt-ing current between VDD and ground. Thus, CMOS logiclevels rather than TTL logic levels, are strongly recom-mended for driving the DAC7611.
®
12DAC7611
As with the GND connection, VDD should be connected toa +5V power supply plane or trace that is separate from theconnection for digital logic until they are connected at thepower entry point. In addition, the 10µF and 0.1µF capaci-tors shown in Figure 4 are strongly recommended andshould be installed as close to VDD and ground as possible.In some situations, additional bypassing may be requiredsuch as a 100µF electrolytic capacitor or even a “Pi” filtermade up of inductors and capacitors—all designed to essen-tially lowpass filter the +5V supply, removing the highfrequency noise (see Figure 4).
OFFSET ERROR MEASUREMENT
As with most DACs, the DAC7611 can have an offset error(or zero scale error) which is either negative or positive. Ifthe error is positive, the output voltage for an input code of000H will be greater than 0V. If the error is negative, theoutput voltage is below 0V. However, since the DAC7611 isa single-supply device and cannot swing below ground, theoutput voltage will be 0V, giving the impression that theoffset error is zero.
Since measuring the offset error on a DAC is such acommon task, a method is needed to reliably measure theoffset error of the DAC7611. This can easily be done asshown in Figure 5. The resistor between VOUT and a nega-tive voltage provides the output amplifier some ability toswing below ground.
FIGURE 4. Suggested Power and Ground Connections for a DAC7611 Sharing a +5V Supply with a Digital System.
FIGURE 5. Offset Error Measurement Circuit.
+
+5V
GND
100µF
Digital Circuits
+5V
GND
+5VPowerSupply
OtherAnalog
Components
VDD
GND
DAC7611
+10µF 0.1µF
Optional
1
2
3
4
8
7
6
5
VOUT
GND
CLR
LD
VDD
CS
CLK
SDI
DAC7611
+0.1µF10µF
+5V
R i ≤ 200µA
–V
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
