DAT Education

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IBM Systems and Technology Group

1 z/VM CP Storage Management Education Series

Dynamic Address TranslationAn Introduction

Dan FitzGeraldFriday, October 16, 2009 (Revision 2)



04/27/15z/VM CP Storage Management Education Series2

Outline

Concept Review

Background

Introducing the DAT Tables

The Translation Process

The Table Entries

Translation Lookaside Buffer




Concept Review

In this portion of the presentation, we will introduce concepts that will come up in our discussion on Dynamic Address Translation.

Most of this information is available from the z/Architecture Principles of Operation, Chapter 3.

We will present this information as a series of definitions. This is intended to be a fast reference/review only, so please consult the Principles of Operation or your Connections Coach if you have any questions.




Concept Review

Access Registers – A special set of 16 registers, one for each general purpose register. For use with AR Mode

AR Mode – Uses the access registers when doing base displacement addressing

Determined by bits 16 and 17 of the PSW

Address Space – A set of virtual addresses, together with the specific transformation parameters which allow each number to be associated with a byte location in memory.

Address-Space Control Element (ASCE) – 8-byte field containing the origin and length (“designator”) of the highest-level DAT table for a specific address space.




Concept Review The real address formed by DAT and the absolute address

then formed by prefixing are both always 64 bits in length. If the system is in the 24 or 31-bit addressing modes, then 40 or 33

zeros respectively are padded onto the address to make it 64-bit




Concept Review

There are four different types of addresses that we will encounter in z/Architecture. They are known as “absolute”, “real”, “virtual” and “logical.” Additionally, we will hear about “effective” addresses.

Absolute Address – The address assigned to a main storage location

These are the unmodified, “actual” addresses of bytes in storage.

Real Address – Identifies a location in real storage

This is an address that we will use for an access to storage

As we will see, real addresses are converted by prefixing into absolute addresses.




Concept Review

Virtual Address – Identifies a location in virtual storage– When a virtual address is used for an access to main storage, it is

translated by means of dynamic address translation (DAT) to a real address, which is then prefixed to an absolute address.

Logical Address – Your addresses are translated within whatever mode the architecture is set to

– In z/Architecture, a specific address mode can be set.For example, your machine may be set to “real address mode”. In this case, your logical addresses will be treated as real addresses.Unless otherwise specified, the storage-operand addresses for most instructions are logical addresses.




Concept Review

Effective Address – The address which exists before any transformation by dynamic address translation or any prefixing is performed

Instruction Address – Addresses used to fetch instructions from storage




Background What is Dynamic Address Translation and what does it mean

to me?

Dynamic Address Translation, or DAT, is the process by which the z/Architecture handles virtual memory.

The Principles of Operation defines DAT as “the process of translating a virtual address during a storage reference into the corresponding real address”

DAT itself consists of the mechanisms used by a z/Architecture-based OS to implement virtual memory, such as a hierarchy of lookup tables.

By utilizing the DAT facility, the operating system can provide to a user a system that appears to have more memory, “storage” in System/z terms, than it actually does.




Background Another use of the DAT facility would be to provide security

on a multi-user system. In this scheme, a number of address spaces are created In VM, this means that each user has a completely different address

space. A general user (as opposed to a privileged user) cannot interfere with the operations of another user.

For more details on address spaces, please see the guide “Address Spaces: An Introduction”, available as part of the CP Storage Management Education Series

Dynamic Address Translation may be specified for addresses generated by the CPU. It cannot be used for the addressing of data in many I/O operations.




Background Addresses generated through Dynamic Address Translation

are always 64 bits in length. When your machine is operating in 31-bit mode, 33 high-order zeroes

are appended to the address to make it 64-bit

Recall that DAT is used for translating virtual addresses to real addresses. This translation is accomplished through the use of an ASCE

The ASCE will point to the uppermost DAT table for a given user's address space

If the ASCE doesn't point to a translation table, then the address space is considered to be “real” and the address is used without translation.

There are four types of ASCEs: primary, secondary, home and AR-specified (specified by an access register)




Introducing the DAT Tables Once the appropriate ASCE has been selected, translation is

to be performed by a means of the DAT tables The exception, of course, being a real-space ASCE, in which case we

don't bother to translate anything at all.

The DAT tables are hierarchical. That is, the entries within a higher-level DAT table point to lower-level DAT tables

In the world of DAT tables, there are three units recognized: regions, segments and pages.

A region is a block of sequential virtual addresses spanning 2GB and starting on a 2GB boundary. These are the uppermost tables in the hierarchy.

Similarly, A segment is a block of sequential virtual addresses spanning 1MB and starting on a 1MB boundary and a page spans 4KB and starts on a 4KB boundary




Introducing the DAT Tables




Introducing the DAT Tables To facilitate this, the virtual address is divided into four fields:

Region Index (RX), which is subdivided three times− Region First Index (RFX)− Region Second Index (RSX)− Region Third Index (RTX)

Segment Index (SX)

Page Index (PX)

Byte Index (BX)




The Translation Process Let's pretend that we've been given the following address:

0000 0401 80F2 22A8 Breaking this down by field yields us,

RFX = 0x000 (not aligned) RSX = 0x001 (not aligned) RTX = 0x003 (not aligned) SX = 0x00F (not aligned) PX = 0x22 BX = 0x2A8

Note that the RFX, RSX, RTX and SX fields are 11 bits in length and thus are not halfword-aligned.

As such, the high order hex digit shown here only represents 3 bytes and they're not on a byte boundary




The Translation Process Let's translate the address in a process similar to what the

computer would use.

In order for us to digest this, let's begin by considering the RX field (the high 33 bits of the address) broken down into binary,

0000 0000 0000 0000 0000 0100 0000 0001 1000 0000...

The computer will first consider the RFX field (in blue) As the length of a single region table entry is eight bytes, we take the

RFX value and multiply by 8, giving us an index into the region first table. The entries in a region first table point to region second tables and will cover an area of up to 16 exobytes of storage.




The Translation Process The computer will first consider the RFX field (cont'd)

In this case the value is zero, so if we had a region 1 table we would index 0 bytes and use the first entry. Assume for this example that our address space size is at least 16EB, so that we have an R1 table.

If our address space size was less than 16EB, then we wouldn't even have a region 1 table.




The Translation Process How about an illustration of this process?

Note how the 11-bit RFX value was converted into an index into the table. This was a zero index, so we go with the first table entry.

This entry contains the address of the region second table that we will use for further translation.




The Translation Process We're still in the first 33 bits of the address, |----0x000---|----0x001----|----0x003----|

0000 0000 0000 0000 0000 0100 0000 0001 1000 0000...

Now consider the RSX field (in red) We're going to follow the same process with each index

Our value is 0x001, so we're indexing 8 bytes into the region second table.

In other words, the second entry in the region second table points to our region third table.

Well here's one thing we do know: as our address here has at least two region second tables, our address space must have more than 8 petabytes of storage

− A single R2 table handles 8PB of storage. We have two R2 tables, so one of them must be full.




The Translation Process One more field to go in the upper 33 bits...

0000 0000 0000 0000 0000 0100 0000 0001 1000 0000...

Next we'll look at the RTX field (in green) This value is 0x003, so our segment table is pointed to by the fourth

entry in the region third table

Now that you have the process down, the remaining three fields in the lower 32 bits should be easy!

SX = 0x00F, so we go to the sixteenth segment table entry and retrieve the address of our page table in storage

PX = 0x22, so we go to the thirty-fifth page table entry and retrieve the address of our page in storage

BX = 0x2A8, so we go to the six-hundred and eightieth byte in our 4K page




The Translation Process Remember before how we were talking about the ASCE?

Well, here's one way in which we use it... Let's say that your machine only has 2 GB of storage. Then we're not

going to want to bother checking the R1 and R2 tables if they're empty.

The solution is to have an ASCE that points to the R3 table as the uppermost DAT table. As translation always begins at the table pointed to by the ASCE, we'll skip those empty R1 and R2 tables and start translating right at R3.

We call the ASCE used for a particular address translation the effective ASCE




The Translation Process

Of course, this was just the basic translation process. We left out some of the virtual-memory specific details

For example, this machine may not really have upwards of 8 PB of storage. Rather, it may just think that it does.

During the translation process, pages of virtual storage have to be reconciled with frames of real storage.

− In other words, our page may not be resident in the system.




The Table Entries In our description of the translation process, we simplified

some of the details about the entries in the DAT tables A region-table entry, for instance, contains more than just a

pointer to the next lower table:

Here's a breakdown of what's inside, Table Origin – The address of the next lowest-level DAT table Table Offset (TF) – Number of 4KB segments that are empty at the

start of the next table (the table pointed to by the Table Origin) Region-Invalid Bit (I) – Is this this set of regions available?

− When this is set to 1, then they aren't and cannot be used for translation. Table Type (TT) – These identify the level of the table that contains

this entry. Table Length (TL) – How many 4K frames long is the next table?




The Table Entries A word on reading Table Type bits,

The two TT bits are read in four combinations, denoting a R1, R2, R3 or segment table

If bits 60 and 61 read 1 1, then the table is a R1 table



If bits 60 and 61 read 0 0, then the table is a segment table




The Table Entries A segment table entry is slightly different from a region table

entry:

Here's what's inside, Page-Table Origin – Pointer to the page table that this address uses Page-Protection Bit (P) – When this bit is set, page protection applies

to the entire 1M segment that the target page table covers Segment-Invalid Bit (I) – Is this this segment available?

− When this is set to 1, then it isn't available (or the page table just isn't resident in memory) and cannot be used for translation.

Common Segment Bit (C) – Controls the use of the Translation Lookaside Buffer (TLB)

Table Type (TT) – These identify the level of the table that contains this entry.

− As we know that this is a segment table, then these should be set to 00.




The Table Entries How is the Common-Segment Bit used?

The TLB is a buffer of high-speed memory that contains copies of the DAT tables

The Common-Segment Bit controls the use of the TLB copies of the segment-table entry and of the page table which it designates

When this bit is set to zero, then it is identifying a private segment. The segment-table entry and the page table it designates may be used only in association with the segment-table origin that designates the segment table in which the segment table entry resides.

− In other words, this segment-table entry and its associated target page table can only be referenced from the TLB by the current segment table

When this bit is set to one, then it is identifying a common segment. Then, this segment-table entry and its target page table may be used even if the referencing segment table isn't the “owner” of the entry.




The Table Entries Lastly, we have to consider the entries fetched from the page

table entries. These point to pages of storage,

The fields in the page-table entry are as follows, Page-Frame Real Address – When these bits are concatenated with

the 12-bit byte-index field of the virtual address, a 64-bit real address is obtained

Page-Invalid Bit (I) – Controls whether the page associated with this entry is available

− When this is set to 1, the page is not available and cannot be used for translation.

Page-Protection Bit (P) – Controls whether store accesses can be made to this page

− If this bit is one, stores are forbidden




Translation Lookaside Buffer Recall how earlier we mentioned the Translation Lookaside

Buffer, or TLB Some of the information specified in the region, segment and page

tables are kept in the TLB to enhance performance The TLB itself is composed of special, high-speed storage

When the CPU references a DAT-table entry, it only needs to access it in real or absolute storage on its initial access

By placing a copy of this data into the TLB, we can perform subsequent operations without having to look up or bring in the data again. It is in this manner that we improve performance.

And in case you were wondering about translating a real-space address, this is also performed by information in the TLB so as to provide consistency with virtual addressing.




Translation Lookaside Buffer A TLB entry may be one of three types,

TLB combined region-and-segment table entry TLB page-table entry TLB real-space entry

A TLB region/segment-table entry and a TLB page-table entry will contain both the information information obtained from the entries in storage as well as the attributes needed to fetch them from storage

A TLB real-space entry contains a page-frame real address and the real-space token origin and region segment, in addition to the page indexes used to form the entry




Translation Lookaside Buffer The details of the TLB don't affect CP all that much, but

when it does it becomes quite important. Therefore, it is something that you need to be aware of.

Keep in mind that as we're working on the DAT structures themselves, that TLB entries may need to be purged

For instance, say that we page out a page table. Any references in the TLB would need to be cleaned out to reflect this change in state

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