Datasheet

Virtex-5 FPGA Packaging and Pinout Specification

UG195 (v4.6) May 5, 2009

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Virtex-5 FPGA Packaging and Pinout Specification www.xilinx.com

UG195 (v4.6) May 5, 2009

Revision HistoryThe following table shows the revision history for this document.Date 04/14/06 05/12/06 09/05/06 Version 1.0 1.2 2.0 Initial Xilinx release. Added UG112 to list of documents. Added units to tables in Chapter 5. Added the LXT platform devices throughout document. In Chapter 1, Added a reference to UG112 for package electrical characteristic information in the Introductionsection. Corrected the description for pin names: CC and GC, removed Note 2, and changed PROGRAM_B_0 to PROGRAM_B (Table 1-7.) In Chapter 2, added Note 1 to each table and added note number to each pin affected by the note content. Added Chapter 6. 10/13/06 2.1 Added system monitor pin information throughout document. Added LX85T devices to appropriate tables. Updated Table 1-3, page 12. Added Note 2 to Table 2-2, Table 2-3, Table 2-4, Table 2-5, Table 2-6, Table 2-8, and Table 2-10. 02/02/07 3.0 Added the SXT devices, added LX220T. Added the FLOAT pin and the System Monitor analog inputs to Table 1-7 on page 16. Added RSVD Note 3 to Table 2-2, Table 2-3, Table 2-4, Table 2-5, Table 2-6, Table 2-8, and Table 2-10. Updated No Connect column to add LX110T device in Table 2-8. Replaced all figures in this chapter. Corrected the LX85 data in Table 6-1, page 408, and the LX85T and LX330T in Table 6-2, page 409. 02/08/07 03/21/07 3.0.1 3.1 Minor typographical error. Added LX220T to Figure 3-22. Fixed MGTTXN and MGTTXP in the legends of Figure 3-5, Figure 3-11, Figure 3-13, Figure 3-21, and Figure 3-25. These legends are now correct and match the pinout tables. Revised all the SelectIO bank diagrams in Chapter 3. Some power pins had been represented as I/O. 08/14/07 3.2 In Table 1-7:

Revision

Clarified general purpose I/O descriptions. Revised the description of RSVD. These pins MUST be tied to ground. Revised direction of FSn. Added note 2 to VCCO_#. Added note 3 to and updated directions for grounding Dedicated System Monitor Pins when not using the System Monitor function.

Removed LX30 from the No Connect (NC) column in Table 2-4 for bank 21, pin numbers AC20, AB23, and AE24. Updated the No Connect (NC) column by adding LX110T, LX220T for MGTAVCC_128 through MGTAVCC_134 in Table 2-8. Revised the pinout diagrams in Chapter 3 to replace some NC designations with open spaces matching the actual package configuration.

UG195 (v4.6) May 5, 2009

www.xilinx.com Virtex-5 FPGA Packaging and Pinout Specification

Date 12/11/07

Version 3.3

Revision Updated the tables in Chapter 1 to include LX20T, LX155, and LX155T devices and the FF323 package. Added center column discussion to description of CC in Table 1-7. Added Table 2-1. Updated Table 2-5 and Table 2-8 to include the LX155T. To avoid confusion, removed some No Connect designations in these tables as well. Updated Table 2-6 and Table 2-10 to include the LX155. Added Figure 3-1 and Figure 3-2. Added LX155 and LX155T to other figures in Chapter 3, Pinout and SelectIO Bank Diagrams. Updated Figure 3-11 and Figure 3-21. Added Figure 4-1, page 392 to Chapter 4. Updated Table 6-1 to include the LX155, and Table 6-2 to include the LX20T and LX155T as well as the added package FF323.

03/31/08

4.0

Added FXT platform to entire document. To include the GTX serial transceivers, added Table 1-4, page 13 and updated Table 1-6, page 13 and added a note to Table 1-7. Added new devices to Table 2-3, Table 2-5, and Table 2-8. Added Figure 3-24 and Figure 3-25. Updated Figure 4-1 and Figure 4-2 with current JEDEC specification reference. Added new devices to Table 6-2.

04/25/08

4.1

Added XC5VSX240T device to the entire document including Table 1-3, Table 1-6, Table 2-8, Figure 3-25, Figure 3-26, and Table 6-2. Updated ADDRn in Table 1-7. Revised Table 2-8 bank NA, Pin C9 and C15.

05/19/08 06/18/08 09/23/08 01/19/09

4.2 4.3 4.4 4.5

Clarified the direction for Multi-Function Pins, Other Pins, Dedicated System Monitor Pins, and RocketIO Serial Transceiver Pins (GTP_DUAL or GTX_DUAL) in Table 1-7. Revised no connect column for MGTAVCC_124 and MGTAVCC_126 in Table 2-5. Added TXT platform to entire document. Chapter 3: Corrected name of FF1156 PackageTX150T, page 376. Added Chapter 5, Recommended PCB Design Rules for BGA Packages. Chapter 6: Added TXT thermal resistance data to Table 6-2, page 409.

05/05/09

4.6

Added Virtex-5Q FPGA package information to Chapter 1, Packaging Overview, including adding Table 1-5, page 13. Updated legend in Figure 3-11, page 368.

Virtex-5 FPGA Packaging and Pinout Specification www.xilinx.com

UG195 (v4.6) May 5, 2009

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: Packaging OverviewSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 11 12 16

Chapter 2: Pinout TablesSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FF323 PackageLX20T and LX30T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FF324 PackageLX30 and LX50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70T . . . . . . . . . . . . 40 FF676 PackageLX30, LX50, LX85, and LX110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T, and FX100T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 FF1153 PackageLX50, LX85, LX110, and LX155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 FF1156 PackageTX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FF1738 PackageFX100T, LX110T, FX130T, LX155T, FX200T, LX220T, SX240T, and LX330T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 FF1759 PackageTX150T and TX240T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 FF1760 PackageLX110, LX155, LX220, and LX330 . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Chapter 3: Pinout and SelectIO Bank DiagramsSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF323 PackageLX20T and LX30T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF324 PackageLX30 and LX50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF665 PackageLX30T, FX30T, SX35T, LX50T, SX50T, and FX70T . . . . . . . . . . . FF676 PackageLX30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF676 PackageLX50, LX85, and LX110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1136 PackageLX50T, SX50T, and LX85T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1136 PackageFX70T, SX95T, FX100T, LX110T, and LX155T . . . . . . . . . . . . . . FF1153 PackageLX50 and LX85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1153 PackageLX110 and LX155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 360 361 362 364 366 368 370 372 374

Virtex-5 FPGA Packaging and Pinout Specification www.xilinx.com UG195 (v4.6) May 5, 2009

5

FF1156 PackageTX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1738 PackageFX100T, LX110T, LX155T, and LX220T. . . . . . . . . . . . . . . . . . . . . FF1738 PackageFX130T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1738 PackageFX200T, SX240T, and LX330T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1759 PackageTX150T and TX240T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1760 PackageLX110, LX155, and LX220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1760 PackageLX330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

376 378 380 382 384 386 388

Chapter 4: Mechanical DrawingsSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF323 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . FF324 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . FF665 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . FF1136 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . EF1136 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . FF1153 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . FF1156 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . FF1738 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . EF1738 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . FF1759 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . FF1760 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . .391 392 393 394 395 396 397 398 399 400 401 402 403

Chapter 5: Recommended PCB Design Rules for BGA Packages Chapter 6: Thermal SpecificationsSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Some Thermal Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 407 410 412 413 414

Chapter 7: Package Marking

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www.xilinx.com Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.6) May 5, 2009

Preface

About This GuideThis guide describes Virtex-5 FPGA and Virtex-5Q FPGA pinouts and package specifications; it also includes pinout diagrams and thermal data.

Guide ContentsThis document is comprised of the following chapters: Chapter 1, Packaging Overview Provides an introduction to the Virtex-5 and Virtex-5Q families with a summary of maximum I/Os available in each device/package combination. Also includes table of pin definitions. Chapter 2, Pinout Tables Provides pinout information for all Virtex-5 and Virtex-5Q devices and packages. Chapter 3, Pinout and SelectIO Bank Diagrams Provides pinout diagrams for all Virtex-5 and Virtex-5Q FPGA package/device combinations. Chapter 4, Mechanical Drawings Provides mechanical drawings of Virtex-5 and Virtex-5Q FPGA packages. Chapter 5, Recommended PCB Design Rules for BGA Packages Provides PCB design rules for BGA packages. Chapter 6, Thermal Specifications Provides thermal data associated with Virtex-5 and Virtex-5Q FPGA packages. Discusses FPGA power management strategy and thermal management options. Chapter 7, Package Marking Provides an example and a description of the marking on top of the package (topmark).


7

Preface: About This Guide

Related DocumentationThe following documents are also available for download at http://www.xilinx.com/virtex5. Virtex-5 Family Overview or the Virtex-5Q Family Overview

The features and product selection of the Virtex-5 family are outlined in this overview.

Virtex-5 FPGA User Guide This guide includes chapters on:

Clocking Resources Clock Management Technology (CMT) Phase-Locked Loops (PLLs) Block RAM Configurable Logic Blocks (CLBs) SelectIO Resources SelectIO Logic Resources Advanced SelectIO Logic Resources

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family.

Virtex-5 FPGA RocketIO GTP Transceiver User Guide This guide describes the RocketIO GTP transceivers available in the Virtex-5 LXT and SXT platforms.

Virtex-5 FPGA RocketIO GTX Transceiver User Guide This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT and FXT platforms.

Virtex-5 FPGA Embedded Processor Block for Virtex-5 FPGAs This reference guide is a description of the embedded processor block available in the Virtex-5 FXT platform.

Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, TXT and FXT platforms.

Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT and FXT platforms used for PCI Express designs.

Virtex-5 FPGA XtremeDSP Design Considerations This guide describes the XtremeDSP slice and includes reference designs for using the DSP48E slice.

8


Additional Resources

Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

Virtex-5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex-5 devices is outlined in this guide.

Virtex-5 FPGA PCB Designers Guide This guide provides information on PCB design for Virtex-5 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional ResourcesTo find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support/mysupport.htm.


9

Preface: About This Guide

10


Chapter 1

Packaging OverviewSummaryThis chapter covers the following topics: Introduction Device/Package Combinations and Maximum I/Os Pin Definitions

IntroductionThis section describes the pinouts for Virtex-5 devices in the 1.00 mm pitch flip-chip finepitch BGA packages. Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins. All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the No Connects column of each table. For Virtex-5Q devices, the EF package is offered. The only difference between an EF and an FF package is that the discrete substrate capacitors on the EF package are coated with epoxy. The coating is comprised of an undercoat epoxy that is dispensed under the capacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All other package construction characteristics of the EF matches that of the FF package. The EF package changes are noted in Chapter 4, Mechanical Drawings. Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O standards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table 1-7 provides definitions for all pin types. For information on package electrical characteristics and how the characteristics are measured, refer to UG112: Device Package User Guide found on the Xilinx website. For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updates to this document.


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Chapter 1: Packaging Overview

Device/Package Combinations and Maximum I/OsTable 1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). Table 1-1: Flip-Chip PackagesPackages FF324 1.00 19 x 19 220 FF665 1.00 27 x 27 360 FF676 1.00 27 x 27 440 FF1136 FF1153 1.00 35 x 35 640 1.00 35 x 35 800 FF1156 1.00 35 x 35 360 FF1738 1.00 42.5 x 42.5 960 FF1759 1.00 42.5 x 42.5 680 FF1760 1.00 42.5 x 42.5 1200

Package Specifications FF323 Pitch (mm) Size (mm) Maximum I/Os 1.00 19 x 19 172

The number of I/Os per package includes all user I/Os except the 19 pins listed in Table 1-2. Table 1-2:DXP DXN VBATT PROGRAM_B

Virtex-5 FPGA I/O Pins in the Dedicated Configuration Bank (Bank0)HSWAPEN D_IN DONE CCLK_0 INIT_B_0 CS_B_0 RDWR_B_0 TCK_0 M0_0 M1_0 M2_0 TMS TDI D_OUT_BUSY TDO_0

The RocketIO GTP transceiver I/O channels for the devices listed in Table 1-3 or the GTX transceiver I/O channels for the devices listed in Table 1-4. Table 1-3:I/O Channels MGTRXP MGTRXN MGTTXP MGTTXNNotes:1. The XC5VLX30T has 4 GTP I/O channels in the FF323/FFG323 package and 8 GTP I/O channels in the FF665/FFG665 package. 2. The XC5VLX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package. 3. The XC5VSX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.

Number of GTP Transceiver I/O Channels/DeviceDevice LX20T LX30T(1) SX35T LX50T(2) SX50T(3) LX85T SX95T LX110T LX155T LX220T SX240T LX330T4 4 4 4 4 or 8 4 or 8 4 or 8 4 or 8 8 8 8 8 8 or 12 8 or 12 8 or 12 8 or 12 8 or 12 8 or 12 8 or 12 8 or 12 12 12 12 12 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

24 24 24 24

24 24 24 24

12


Device/Package Combinations and Maximum I/Os

Table 1-4:I/O Channels MGTRXP MGTRXN MGTTXP MGTTXNNotes:

Number of GTX Transceiver I/O Channels/DeviceDevice FX30T 8 8 8 8 FX70T(1) 8 or 16 8 or 16 8 or 16 8 or 16 FX100T 16 16 16 16 FX130T 20 20 20 20 TX150T 40 40 40 40 FX200T 24 24 24 24 TX240T 48 48 48 48

1. The XC5VFX70T has 8 GTX I/O channels in the FF665/FFG665 package and 16 GTX I/O channels in the FF1136/FFG1136 package.

Table 1-5 shows the available EF packages for the Virtex-5Q devices. Table 1-5: Available Virtex-5Q Devices with EF Package TypeFF323(1) EF665 EF676 Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available EF1136 EF1153 EF1738

Virtex-5Q Device XQ5VLX85 XQ5VLX110 XQ5VLX30T XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200TNotes:

1. The XQ5VLX30T is only available in the standard FF323 package and not an epoxy coated capacitor EF version.

Table 1-6 shows the number of available I/Os and the number of differential I/O pairs for each Virtex-5 device/package combination. Table 1-6:Virtex-5 Device XC5VLX20T

Available I/O Pin/Device/Package CombinationsVirtex-5 FPGA Package User I/Os PinsFF323 FF324 FF665 FF676 FF1136 FF1153 FF1156 FF1738 FF1759 FF1760 Available User I/Os Differential I/O Pairs

172 86


13


Table 1-6:Virtex-5 Device

Available I/O Pin/Device/Package Combinations (Continued)Virtex-5 FPGA Package User I/Os PinsFF323 FF324 FF665 FF676 FF1136 FF1153 FF1156 FF1738 FF1759 FF1760 Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs

XC5VLX30

220 110

400 200

XC5VLX30T

172 86

360 180 360 180 360 180

XC5VFX30T

XC5VSX35T

XC5VLX50

220 110

440 220

560 280

XC5VLX50T

360 180 360 180 360 180

480 240 480 240 640 320

XC5VSX50T

XC5VFX70T

Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs

XC5VLX85

440 220

560 280

XC5VLX85T

480 240 640 320 640 320

XC5VSX95T

Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs

XC5VFX100T

680 340

XC5VLX110

440 220

800 400 800 400

800 400 800 400

XC5VLX155

XC5VLX110T

640 320

680 340 840 420

XC5VFX130T

14


Device/Package Combinations and Maximum I/Os

Table 1-6:Virtex-5 Device

Available I/O Pin/Device/Package Combinations (Continued)Virtex-5 FPGA Package User I/Os PinsFF323 FF324 FF665 FF676 FF1136 FF1153 FF1156 FF1738 FF1759 FF1760 Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs 360 180 680 340 680 340

XC5VTX150T

XC5VLX155T

640 320

680 340 960 480

XC5VFX200T

XC5VLX220

800 400

XC5VLX220T

680 340 960 480

XC5VSX240T

XC5VTX240T

XC5VLX330

Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs

1200 600

XC5VLX330T

960 480


15


Pin DefinitionsTable 1-7 lists the pin definitions used in Virtex-5 FPGA packages. Table 1-7: Virtex-5 FPGA Pin DefinitionsDirection Description

Pin Name User I/O Pins

IO_LXXY_#

Input/ Output

All user I/O pins are capable of differential signaling and can implement pairs. Each user I/O is labeled IO_LXXY_#, where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.

Multi-Function Pins IO_LXXY_ZZZ_# Dn ADDRn RSn FCS_B FOE_B FWE_B MOSI CSO_B FSn CC Input Multi-function pins are labelled IO_LXXY_ZZZ_#, where ZZZ represents one or more of the following functions in addition to being general purpose user I/O. If not used for their special function, these pins can be user I/O. Input Output Output Output Output Output Output Output Input In SelectMAP mode, D0 through D31 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. ADDR0ADDR25 BPI address output. These pins become user I/O after configuration. RS0 and RS1 revision select output. BPI and SPI flash chip select. BPI flash output enable. BPI flash write enable. SPI flash data output enable. Parallel daisy chain chip select. FS0FS2 SPI Flash vendor selection. These clock pins connect to Clock Capable I/Os. These pins become regular user I/Os when not needed for clocks. If a single-ended clock is connected to the differential CC pair of pins, it must be connected to the positive (P) side of the pair. Clock capable I/Os in the center column can not drive BUFRs. These clock pins connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. If a single-ended clock is connected to the differential GC pair of pins, it must be connected to the positive (P) side of the pair. System Monitor analog inputs. These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank). This pin is for the DCI voltage reference resistor of N transistor (per bank, to be pulled High with reference resistor). This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with reference resistor).

GC Input

SMnP/SMnN VREF VRN VRP

Input N/A N/A N/A

16


Pin Definitions

Table 1-7:

Virtex-5 FPGA Pin Definitions (Continued)Direction Pins(1) Input/ Output Input Input Input/ Output Configuration clock. Output and input in Master mode or Input in Slave mode. In SelectMAP mode, this is the active-low Chip Select signal. In bit-serial modes, D_IN is the single-data input. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. In bit-serial modes, DOUT gives preamble and configuration data to downstream devices in a daisy chain. Enable I/O pullups during configuration When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. Configuration mode selection Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. In SelectMAP mode, this is the active-low Write Enable signal. Boundary-Scan Clock. Boundary-Scan Data Input. Boundary-Scan Data Output. Boundary-Scan Mode Select. Temperature-sensing diode pins (Anode: DXP; Cathode: DXN). Description

Pin Name Dedicated Configuration CCLK_0 CS_B_0 D_IN_0 DONE_0

D_OUT_BUSY_0

Output

HSWAPEN_0 INIT_B_0 M0_0, M1_0, M2_0 PROGRAM_B RDWR_B_0 TCK_0 TDI_0 TDO_0 TMS_0 DXP_0, DXN_0 Reserved Pins RSVD FLOAT Other Pins GND VBATT_0 VCCAUX VCCINT VCCO_#(2)

Input Bidirectional (open-drain) Input Input Input Input Input Output Input N/A

N/A N/A

Reserved pinsmust be tied to ground. Do not connect this pin to the board. Leave floating.

N/A N/A N/A N/A N/A

Ground. Decryptor key memory backup supply; this pin should be tied to VCC or GND. Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Power-supply pins for the output drivers (per bank).


17


Table 1-7:

Virtex-5 FPGA Pin Definitions (Continued)Direction Description

Pin Name

Dedicated System Monitor Pins AVDD_0(3) AVSS_0(3) VP_0(3) VN_0(3) VREFP_0(3) VREFN_ 0(3) N/A N/A Input Input N/A N/A System Monitors ADC analog positive supply voltage. System Monitors ADC analog ground reference. System Monitor dedicated differential analog input (positive side). System Monitor dedicated differential analog input (negative side). External System Monitor 2.5V positive reference voltage. External System Monitor 2.5V ground reference voltage.

RocketIO Serial Transceiver Pins (GTP_DUAL or GTX_DUAL) MGTAVCC MGTAVCCPLL MGTAVTTRX MGTAVTTRXC MGTAVTTTX MGTREFCLKP MGTREFCLKN MGTRREF MGTRXP MGTRXN MGTTXP MGTTXNNotes:1. All dedicated pins (JTAG and configuration) are powered by VCC_CONFIG. 2. VCCO pins in unbonded banks must be connected to the VCCO for that bank for package migration. Do NOT connect unbonded VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be left unconnected or tied to a common supply (VCCO or ground). 3. When not using System Monitor, these pins must be grounded. See Disabling the System Monitor in UG192: Virtex-5 FPGA System Monitor User Guide. 4. MGTAVCCPLL voltage for GTP transceivers is not the same as the MGTAVCCPLL voltage for GTX transceivers, see DS202: Virtex-5 FPGA Data Sheet. UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide and UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide contain board design guidelines for these transceivers.

N/A N/A N/A N/A N/A Input Input Input Input Input Output Output

Power-supply pin for transceiver mixed-signal circuitry. Power-supply pin for PLL.(4) Power-supply pin for RX circuitry. Power-supply pin for the resistor calibration circuit. Power-supply pin for TX circuitry. Positive differential reference clock. Negative differential reference clock (negative). Precision reference resistor pin for internal calibration termination. Positive differential receive port. Negative differential receive port. Positive differential transmit port. Negative differential transmit port.

18


Chapter 2

Pinout TablesSummaryThis chapter includes the pinout information tables for the following packages: Table 2-1, FF323 PackageLX20T and LX30T, on page 19 Table 2-2, FF324 PackageLX30 and LX50, on page 30 Table 2-3, FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70T, on page 40 Table 2-4, FF676 PackageLX30, LX50, LX85, and LX110, on page 61 Table 2-5, FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T and FX100T, on page 82 Table 2-6, FF1153 PackageLX50, LX85, LX110, and LX155, on page 118 Table 2-7, FF1156 PackageTX150T, on page 154 Table 2-8, FF1738 PackageFX100T, LX110T, FX130T, LX155T, FX200T, LX220T, SX240T, and LX330T, on page 190 Table 2-9, FF1759 PackageTX150T and TX240T, on page 251 Table 2-10, FF1760 PackageLX110, LX155, LX220, and LX330, on page 305

FF323 PackageLX20T and LX30TTable 2-1:Bank

FF323 PackageLX20T and LX30TPin Description Pin Number No Connect (NC)

0 0 0 0 0 0 0 0 0 0

DXP_0 DXN_0 AVDD_0 AVSS_0 VP_0 VN_0 VREFP_0 VREFN_0 VBATT_0 PROGRAM_B_0

K10 K9 G10 G9 H10 J9 J10 H9 D5 E11


19

Chapter 2: Pinout Tables

Table 2-1:Bank

FF323 PackageLX20T and LX30T (Continued)Pin Description Pin Number No Connect (NC)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

HSWAPEN_0 D_IN_0 DONE_0 CCLK_0 INIT_B_0 CS_B_0 RDWR_B_0 RSVD(3) RSVD(3) TCK_0 M0_0 M2_0 M1_0 TMS_0 TDI_0 D_OUT_BUSY_0 TDO_0 IO_L0P_A19_1 IO_L0N_A18_1 IO_L1P_A17_1 IO_L1N_A16_1 IO_L2P_A15_D31_1 IO_L2N_A14_D30_1 IO_L3P_A13_D29_1 IO_L3N_A12_D28_1 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5P_A9_D25_1 IO_L5N_A8_D24_1 IO_L6P_A7_D23_1 IO_L6N_A6_D22_1 IO_L7P_A5_D21_1 IO_L7N_A4_D20_1

F11 F6 F9 E10 B5 A4 E6 L9 L10 M6 G6 M9 H5 N1 M5 N3 N5 A7 A6 E9 D8 D10 D9 C8 C7 B9 B8 B6 C6 A8 A9 D7 E7

20


FF323 PackageLX20T and LX30T

Table 2-1:Bank


1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4

IO_L8P_CC_A3_D19_1 IO_L8N_CC_A2_D18_1(2) IO_L9P_CC_A1_D17_1 IO_L9N_CC_A0_D16_1(2) IO_L0P_CC_RS1_2 IO_L0N_CC_RS0_2(2) IO_L1P_CC_A25_2 IO_L1N_CC_A24_2(2) IO_L2P_A23_2 IO_L2N_A22_2 IO_L3P_A21_2 IO_L3N_A20_2 IO_L4P_FCS_B_2 IO_L4N_VREF_FOE_B_MOSI_2 IO_L5P_FWE_B_2 IO_L5N_CSO_B_2 IO_L6P_D7_2 IO_L6N_D6_2 IO_L7P_D5_2 IO_L7N_D4_2 IO_L8P_D3_2 IO_L8N_D2_FS2_2 IO_L9P_D1_FS1_2 IO_L9N_D0_FS0_2 IO_L0P_GC_D15_4 IO_L0N_GC_D14_4(1) IO_L1P_GC_D13_4 IO_L1N_GC_D12_4(1) IO_L2P_GC_D11_4 IO_L2N_GC_D10_4(1) IO_L3P_GC_D9_4 IO_L3N_GC_D8_4(1) IO_L4P_GC_4

B10 C10 F8 F7 R1 T1 V1 U1 P2 P3 V2 V3 R2 T2 U4 U3 P4 R4 U5 V5 P5 R5 T4 T3 R9 P9 N7 N6 T9 U9 T6 R6 T8


21


Table 2-1:Bank


4 4 4 4 4 4 4 4 4 4 4 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

IO_L4N_GC_VREF_4(1) IO_L5P_GC_4 IO_L5N_GC_4(1) IO_L6P_GC_4 IO_L6N_GC_4(1) IO_L7P_GC_VRN_4 IO_L7N_GC_VRP_4(1) IO_L8P_CC_GC_4 IO_L8N_CC_GC_4(1)(2) IO_L9P_CC_GC_4 IO_L9N_CC_GC_4(1)(2) IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_11 IO_L8N_CC_11(2) IO_L9P_CC_11 IO_L9N_CC_11(2) IO_L10P_CC_SM15P_11 IO_L10N_CC_SM15N_11(2)

U8 V6 U6 V8 V7 N8 M8 T7 R7 P8 P7 D13 D14 E15 D15 E14 F14 A11 A12 C12 C13 B13 A13 G14 G15 B14 A14 G13 F13 C15 B15 B16 A16

22



Table 2-1:Bank


11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13

IO_L11P_CC_SM14P_11 IO_L11N_CC_SM14N_11(2) IO_L12P_VRN_11 IO_L12N_VRP_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_VREF_11 IO_L15P_SM13P_11 IO_L15N_SM13N_11 IO_L16P_SM12P_11 IO_L16N_SM12N_11 IO_L17P_SM11P_11 IO_L17N_SM11N_11 IO_L18P_SM10P_11 IO_L18N_SM10N_11 IO_L19P_SM9P_11 IO_L19N_SM9N_11 IO_L0P_SM8P_13 IO_L0N_SM8N_13 IO_L1P_SM7P_13 IO_L1N_SM7N_13 IO_L2P_SM6P_13 IO_L2N_SM6N_13 IO_L3P_SM5P_13 IO_L3N_SM5N_13 IO_L4P_13 IO_L4N_VREF_13 IO_L5P_SM4P_13 IO_L5N_SM4N_13 IO_L6P_SM3P_13 IO_L6N_SM3N_13 IO_L7P_SM2P_13

F16 G16 A18 A17 E17 E16 C17 C16 D12 E12 C18 B18 F18 F17 D18 D17 B11 C11 H13 J14 H17 G18 J15 K15 H18 J18 K12 L12 J17 K17 H15 H16 L18


23


Table 2-1:Bank


13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 17 17 17 17 17 17 17 17

IO_L7N_SM2N_13 IO_L8P_CC_SM1P_13 IO_L8N_CC_SM1N_13(2) IO_L9P_CC_SM0P_13 IO_L9N_CC_SM0N_13(2) IO_L10P_CC_13 IO_L10N_CC_13(2) IO_L11P_CC_13 IO_L11N_CC_13(2) IO_L12P_VRN_13 IO_L12N_VRP_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_VREF_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L4P_17 IO_L4N_VREF_17 IO_L5P_17 IO_L5N_17 IO_L6P_17 IO_L6N_17 IO_L7P_17 IO_L7N_17

L17 N12 M11 K16 L16 N18 M18 M14 L13 P18 N17 L14 K14 R17 P17 N13 M13 R15 R16 P14 P15 N16 M16 N15 M15 M10 N11 T17 T16 T12 R12 T18 U18

24



Table 2-1:Bank


17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 NA NA NA NA NA NA NA NA NA

IO_L8P_CC_17 IO_L8N_CC_17(2) IO_L9P_CC_17 IO_L9N_CC_17(2) IO_L10P_CC_17 IO_L10N_CC_17(2) IO_L11P_CC_17 IO_L11N_CC_17(2) IO_L12P_VRN_17 IO_L12N_VRP_17 IO_L13P_17 IO_L13N_17 IO_L14P_17 IO_L14N_VREF_17 IO_L15P_17 IO_L15N_17 IO_L16P_17 IO_L16N_17 IO_L17P_17 IO_L17N_17 IO_L18P_17 IO_L18N_17 IO_L19P_17 IO_L19N_17 MGTTXP0_112 MGTAVTTTX_112 MGTTXN0_112 MGTRXP0_112 MGTAVTTRX_112 MGTRXN0_112 MGTAVCCPLL_112 MGTRXN1_112 MGTREFCLKN_112

P10 N10 U16 U15 V18 V17 R10 R11 V16 V15 T11 U11 R14 T14 V10 U10 U14 T13 P12 P13 U13 V13 V12 V11 A2 F3 B2 B1 B3 C1 E4 D1 C4


25


Table 2-1:Bank


NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

MGTRXP1_112 MGTREFCLKP_112 MGTTXN1_112 MGTTXP1_112 MGTRREF_112 MGTTXP0_114 MGTAVTTTX_114 MGTTXN0_114 MGTRXP0_114 MGTAVTTRX_114 MGTRXN0_114 MGTAVCCPLL_114 MGTRXN1_114 MGTREFCLKN_114 MGTRXP1_114 MGTREFCLKP_114 MGTTXN1_114 MGTTXP1_114 MGTAVTTRXC GND GND GND GND GND GND GND GND GND GND GND GND GND GND

E1 C3 E2 F2 F5 G2 M3 H2 H1 H3 J1 L4 K1 J4 L1 J3 L2 M2 G4 A1 A3 A5 B17 B4 C14 C2 C5 C9 D11 D2 D4 D6 E18

26



Table 2-1:Bank


NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

E3 E5 F1 F10 F12 F15 F4 G1 G11 G17 G3 G5 G7 H12 H4 H6 H8 J11 J16 J2 J5 J7 K13 K2 K4 K6 K8 L11 L3 L5 L7 M1 M12


27


Table 2-1:Bank


NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 1 1 1 2 2 2

GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2

M17 M4 N14 N2 N9 P1 P6 R18 T10 T15 U12 U7 V4 G12 J13 K7 L6 L8 G8 H11 H7 J12 J6 J8 K11 K5 N4 A10 B7 E8 R3 T5 U2

28



Table 2-1:Bank


4 4 4 11 11 11 11 13 13 13 13 17 17 17 17 NA NANotes:

VCCO_4 VCCO_4 VCCO_4 VCCO_11 VCCO_11 VCCO_11 VCCO_11 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_17 VCCO_17 VCCO_17 VCCO_17 MGTAVCC_112 MGTAVCC_114

R8 V9 M7 A15 B12 D16 E13 H14 K18 L15 P16 P11 R13 U17 V14 D3 K3

1. Do not connect a single-ended clock to the N-side of the differential clock pair of pins, for example, IO_L3N_GC_3. 2. Do not connect a single-ended clock to the N-side of clock capable pins, for example, IO_L8N_CC_11. 3. RSVD pins must be tied to GND (logic 0).


29


FF324 PackageLX30 and LX50Table 2-2:Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

FF324 PackageLX30 and LX50Pin Description Pin Number L10 L9 H10 H9 J10 K9 K10 J9 T18 U18 T17 R7 P8 N8 M8 R16 P15 R14 P14 M9 N12 N13 L11 V5 U5 T6 U6 F11 G11 G10 F9 No Connect (NC)

DXP_0 DXN_0 AVDD_0 AVSS_0 VP_0 VN_0 VREFP_0 VREFN_0 VBATT_0 PROGRAM_B_0 HSWAPEN_0 D_IN_0 DONE_0 CCLK_0 INIT_B_0 CS_B_0 RDWR_B_0 RSVD(3) RSVD(3) TCK_0 M0_0 M2_0 M1_0 TMS_0 TDI_0 D_OUT_BUSY_0 TDO_0 IO_L0P_A19_1 IO_L0N_A18_1 IO_L1P_A17_1 IO_L1N_A16_1

30


FF324 PackageLX30 and LX50

Table 2-2:Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number E12 D12 F8 G9 C12 D13 G8 F7 F12 F13 D8 E7 G13 H13 D7 C6 T8 T7 R15 T16 R9 T9 V18 V17 P10 P9 U16 V16 N10 M10 T14 T13 N11 No Connect (NC)

IO_L2P_A15_D31_1 IO_L2N_A14_D30_1 IO_L3P_A13_D29_1 IO_L3N_A12_D28_1 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5P_A9_D25_1 IO_L5N_A8_D24_1 IO_L6P_A7_D23_1 IO_L6N_A6_D22_1 IO_L7P_A5_D21_1 IO_L7N_A4_D20_1 IO_L8P_CC_A3_D19_1 IO_L8N_CC_A2_D18_1(2) IO_L9P_CC_A1_D17_1 IO_L9N_CC_A0_D16_1(2) IO_L0P_CC_RS1_2 IO_L0N_CC_RS0_2 (2) IO_L1P_CC_A25_2 IO_L1N_CC_A24_2 (2) IO_L2P_A23_2 IO_L2N_A22_2 IO_L3P_A21_2 IO_L3N_A20_2 IO_L4P_FCS_B_2 IO_L4N_VREF_FOE_B_MOSI_2 IO_L5P_FWE_B_2 IO_L5N_CSO_B_2 IO_L6P_D7_2 IO_L6N_D6_2 IO_L7P_D5_2 IO_L7N_D4_2 IO_L8P_D3_2


31


Table 2-2:Bank 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number M11 P13 P12 A8 A9 B9 B10 E9 D9 E10 E11 C8 B8 D10 C10 A6 A7 B11 C11 B6 C7 A11 A12 U15 V15 V7 V6 V13 V12 V8 U8 U14 U13 No Connect (NC)

IO_L8N_D2_FS2_2 IO_L9P_D1_FS1_2 IO_L9N_D0_FS0_2 IO_L0P_CC_GC_3 IO_L0N_CC_GC_3(1)(2) IO_L1P_CC_GC_3 IO_L1N_CC_GC_3(1)(2) IO_L2P_GC_VRN_3 IO_L2N_GC_VRP_3(1) IO_L3P_GC_3 IO_L3N_GC_3(1) IO_L4P_GC_3 IO_L4N_GC_VREF_3(1) IO_L5P_GC_3 IO_L5N_GC_3(1) IO_L6P_GC_3 IO_L6N_GC_3(1) IO_L7P_GC_3 IO_L7N_GC_3(1) IO_L8P_GC_3 IO_L8N_GC_3(1) IO_L9P_GC_3 IO_L9N_GC_3(1) IO_L0P_GC_D15_4 IO_L0N_GC_D14_4(1) IO_L1P_GC_D13_4 IO_L1N_GC_D12_4(1) IO_L2P_GC_D11_4 IO_L2N_GC_D10_4(1) IO_L3P_GC_D9_4 IO_L3N_GC_D8_4(1) IO_L4P_GC_4 IO_L4N_GC_VREF_4(1)

32



Table 2-2:Bank 4 4 4 4 4 4 4 4 4 4 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number U10 U9 R12 T12 V11 V10 U11 T11 R11 R10 C15 C16 A13 A14 B14 B15 B16 A16 D14 E14 A17 A18 C13 B13 B18 C17 F14 G14 F16 E16 E17 D17 D15 No Connect (NC)

IO_L5P_GC_4 IO_L5N_GC_4(1) IO_L6P_GC_4 IO_L6N_GC_4(1) IO_L7P_GC_VRN_4 IO_L7N_GC_VRP_4(1) IO_L8P_CC_GC_4 IO_L8N_CC_GC_4(1)(2) IO_L9P_CC_GC_4 IO_L9N_CC_GC_4(1)(2) IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_11 IO_L8N_CC_11 (2) IO_L9P_CC_11 IO_L9N_CC_11 (2) IO_L10P_CC_SM15P_11 IO_L10N_CC_SM15N_11 (2) IO_L11P_CC_SM14P_11


33


Table 2-2:Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number E15 D18 C18 H15 G15 F18 F17 H16 G16 H18 G18 H17 J17 K17 J18 J15 J14 E6 F6 B5 C5 D5 D4 B4 A4 E5 E4 A3 B3 G5 G6 C3 D3 No Connect (NC)

IO_L11N_CC_SM14N_11 (2) IO_L12P_VRN_11 IO_L12N_VRP_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_VREF_11 IO_L15P_SM13P_11 IO_L15N_SM13N_11 IO_L16P_SM12P_11 IO_L16N_SM12N_11 IO_L17P_SM11P_11 IO_L17N_SM11N_11 IO_L18P_SM10P_11 IO_L18N_SM10N_11 IO_L19P_SM9P_11 IO_L19N_SM9N_11 IO_L0P_12 IO_L0N_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12

34



Table 2-2:Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number H6 H5 D2 C2 A1 A2 G4 F4 C1 B1 G3 F3 F1 E1 J5 J4 H3 J3 H2 J2 E2 F2 G1 H1 K15 L16 L17 K16 K14 L14 M18 L18 L13 No Connect (NC)

IO_L8P_CC_12 IO_L8N_CC_12 (2) IO_L9P_CC_12 IO_L9N_CC_12 (2) IO_L10P_CC_12 IO_L10N_CC_12 (2) IO_L11P_CC_12 IO_L11N_CC_12 (2) IO_L12P_VRN_12 IO_L12N_VRP_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_VREF_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L0P_SM8P_13 IO_L0N_SM8N_13 IO_L1P_SM7P_13 IO_L1N_SM7N_13 IO_L2P_SM6P_13 IO_L2N_SM6N_13 IO_L3P_SM5P_13 IO_L3N_SM5N_13 IO_L4P_13


35


Table 2-2:Bank 13 13 13 13 13 13 13 13 13 13 13 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number M13 P18 N18 M14 N15 P17 R17 M15 M16 N16 N17 K5 K4 K2 K1 L6 M6 L2 L1 L4 L3 N1 M1 M4 M3 N2 N3 N5 M5 P2 P3 R2 R1 No Connect (NC)

IO_L4N_VREF_13 IO_L5P_SM4P_13 IO_L5N_SM4N_13 IO_L6P_SM3P_13 IO_L6N_SM3N_13 IO_L7P_SM2P_13 IO_L7N_SM2N_13 IO_L8P_CC_SM1P_13 IO_L8N_CC_SM1N_13 (2) IO_L9P_CC_SM0P_13 IO_L9N_CC_SM0N_13 (2) IO_L0P_18 IO_L0N_18 IO_L1P_18 IO_L1N_18 IO_L2P_18 IO_L2N_18 IO_L3P_18 IO_L3N_18 IO_L4P_18 IO_L4N_VREF_18 IO_L5P_18 IO_L5N_18 IO_L6P_18 IO_L6N_18 IO_L7P_18 IO_L7N_18 IO_L8P_CC_18 IO_L8N_CC_18 (2) IO_L9P_CC_18 IO_L9N_CC_18 (2) IO_L10P_CC_18 IO_L10N_CC_18 (2)

36



Table 2-2:Bank 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number N6 P5 T2 T1 N7 P7 V1 U1 P4 R4 V2 V3 R5 R6 U3 T3 T4 U4 D1 J1 P1 B2 M2 U2 E3 R3 H4 V4 A5 L5 D6 K6 P6 No Connect (NC)

IO_L11P_CC_18 IO_L11N_CC_18 (2) IO_L12P_VRN_18 IO_L12N_VRP_18 IO_L13P_18 IO_L13N_18 IO_L14P_18 IO_L14N_VREF_18 IO_L15P_18 IO_L15N_18 IO_L16P_18 IO_L16N_18 IO_L17P_18 IO_L17N_18 IO_L18P_18 IO_L18N_18 IO_L19P_18 IO_L19N_18 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND


37


Table 2-2:Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number G7 J7 L7 U7 H8 K8 C9 N9 F10 T10 J11 B12 H12 K12 M12 E13 J13 R13 H14 V14 A15 L15 D16 P16 B17 G17 U17 E18 K18 J6 H7 M7 G12 No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX

38



Table 2-2:Bank NA NA NA NA NA NA NA NA 0 0 1 1 2 2 3 3 4 4 11 11 11 12 12 12 13 13 18 18 18 Notes:

FF324 PackageLX30 and LX50 (Continued)Pin Description Pin Number K13 K7 J8 L8 H11 K11 J12 L12 R18 T15 B7 E8 R8 V9 A10 D11 P11 U12 C14 F15 J16 C4 F5 G2 M17 N14 K3 N4 T5 No Connect (NC)

VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_18 VCCO_18 VCCO_18



39


FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TTable 2-3:Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number R15 R14 M15 M14 N15 P14 P15 N14 J19 J20 K20 J10 K11 J11 H12 L20 M20 P20 R20 V11 T20 U20 W20 W13 V13 U12 V12 G15 G16 H13 G14 No Connect (NC)


40


FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70T

Table 2-3:Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number G17 F17 F15 F14 F18 G19 F13 G12 H18 H19 G11 H11 G20 H21 G10 H9 W11 Y10 Y20 AA19 AA10 Y11 AA18 Y18 Y12 AA12 AA17 Y17 AA13 AA14 Y16 W16 Y13 No Connect (NC)

IO_L2P_A15_D31_1 IO_L2N_A14_D30_1 IO_L3P_A13_D29_1 IO_L3N_A12_D28_1 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5P_A9_D25_1 IO_L5N_A8_D24_1 IO_L6P_A7_D23_1 IO_L6N_A6_D22_1 IO_L7P_A5_D21_1 IO_L7N_A4_D20_1 IO_L8P_CC_A3_D19_1 IO_L8N_CC_A2_D18_1 (2) IO_L9P_CC_A1_D17_1(2) IO_L9N_CC_A0_D16_1(2) IO_L0P_CC_RS1_2 IO_L0N_CC_RS0_2(2) IO_L1P_CC_A25_2 IO_L1N_CC_A24_2(2) IO_L2P_A23_2 IO_L2N_A22_2 IO_L3P_A21_2 IO_L3N_A20_2 IO_L4P_FCS_B_2 IO_L4N_VREF_FOE_B_MOSI_2 IO_L5P_FWE_B_2 IO_L5N_CSO_B_2 IO_L6P_D7_2 IO_L6N_D6_2 IO_L7P_D5_2 IO_L7N_D4_2 IO_L8P_D3_2


41


Table 2-3:Bank 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number W14 Y15 AA15 D15 E15 D16 E16 D14 D13 E17 D18 E13 E12 E18 F19 F12 E11 E20 E21 E10 F10 F20 G21 Y21 AA20 AB10 AB11 AB21 AB20 AC11 AB12 AB19 AC19 No Connect (NC)


42



Table 2-3:Bank 4 4 4 4 4 4 4 4 4 4 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number AC12 AC13 AC18 AB17 AB14 AC14 AC17 AB16 AB15 AC16 E26 E25 F25 G26 H26 G25 F24 G24 E23 E22 F23 F22 G22 H22 H23 J23 J21 K21 K22 K23 L23 L22 M21 No Connect (NC)

IO_L5P_GC_4 IO_L5N_GC_4(1) IO_L6P_GC_4 IO_L6N_GC_4(1) IO_L7P_GC_VRN_4 IO_L7N_GC_VRP_4(1) IO_L8P_CC_GC_4 IO_L8N_CC_GC_4(1)(2) IO_L9P_CC_GC_4 IO_L9N_CC_GC_4(1)(2) IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_11 IO_L8N_CC_11(2) IO_L9P_CC_11 IO_L9N_CC_11(2) IO_L10P_CC_SM15P_11 IO_L10N_CC_SM15N_11(2) IO_L11P_CC_SM14P_11


43


Table 2-3:Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number N21 H24 J24 J25 J26 K26 L25 L24 K25 N26 M26 M25 M24 N24 N23 N22 M22 Y6 Y5 G6 H6 Y4 W4 G5 F5 W5 W6 G4 H4 V6 V7 J5 J6 No Connect (NC)

IO_L11N_CC_SM14N_11(2) IO_L12P_VRN_11 IO_L12N_VRP_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_VREF_11 IO_L15P_SM13P_11 IO_L15N_SM13N_11 IO_L16P_SM12P_11 IO_L16N_SM12N_11 IO_L17P_SM11P_11 IO_L17N_SM11N_11 IO_L18P_SM10P_11 IO_L18N_SM10N_11 IO_L19P_SM9P_11 IO_L19N_SM9N_11 IO_L0P_12 IO_L0N_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12

44



Table 2-3:Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number U7 T8 K5 L5 K6 K7 U6 U5 K8 L7 T5 R5 M7 L8 R6 T7 P6 N6 M6 N7 N8 P8 R8 R7 P26 R26 P25 R25 P24 P23 R23 R22 U26 No Connect (NC)

IO_L8P_CC_12 IO_L8N_CC_12 (2) IO_L9P_CC_12 IO_L9N_CC_12 (2) IO_L10P_CC_12 IO_L10N_CC_12 (2) IO_L11P_CC_12 IO_L11N_CC_12 (2) IO_L12P_VRN_12 IO_L12N_VRP_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_VREF_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L0P_SM8P_13 IO_L0N_SM8N_13 IO_L1P_SM7P_13 IO_L1N_SM7N_13 IO_L2P_SM6P_13 IO_L2N_SM6N_13 IO_L3P_SM5P_13 IO_L3N_SM5N_13 IO_L4P_13


45


Table 2-3:Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 15 15

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number V26 U25 T25 T24 T23 U24 V24 W26 W25 W24 V23 AA22 Y22 Y23 W23 Y26 Y25 AA25 AB26 AB25 AA24 AB24 AA23 P21 R21 T22 U22 U21 V22 V21 W21 C13 C14 No Connect (NC)

IO_L4N_VREF_13 IO_L5P_SM4P_13 IO_L5N_SM4N_13 IO_L6P_SM3P_13 IO_L6N_SM3N_13 IO_L7P_SM2P_13 IO_L7N_SM2N_13 IO_L8P_CC_SM1P_13 IO_L8N_CC_SM1N_13 (2) IO_L9P_CC_SM0P_13 IO_L9N_CC_SM0N_13 (2) IO_L10P_CC_13 IO_L10N_CC_13 (2) IO_L11P_CC_13 IO_L11N_CC_13 (2) IO_L12P_VRN_13 IO_L12N_VRP_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_VREF_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L0P_15 IO_L0N_15

46



Table 2-3:Bank 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number B14 A13 A14 A15 B15 C16 B16 C17 B17 A17 A18 A19 B19 C18 A20 B20 C19 D19 D21 D20 B21 C21 D23 C22 B22 A22 A23 A24 B24 C23 D24 C24 B25 No Connect (NC)

IO_L1P_15 IO_L1N_15 IO_L2P_15 IO_L2N_15 IO_L3P_15 IO_L3N_15 IO_L4P_15 IO_L4N_VREF_15 IO_L5P_15 IO_L5N_15 IO_L6P_15 IO_L6N_15 IO_L7P_15 IO_L7N_15 IO_L8P_CC_15 IO_L8N_CC_15 (2) IO_L9P_CC_15 IO_L9N_CC_15 (2) IO_L10P_CC_15 IO_L10N_CC_15 (2) IO_L11P_CC_15 IO_L11N_CC_15 (2) IO_L12P_VRN_15 IO_L12N_VRP_15 IO_L13P_15 IO_L13N_15 IO_L14P_15 IO_L14N_VREF_15 IO_L15P_15 IO_L15N_15 IO_L16P_15 IO_L16N_15 IO_L17P_15


47


Table 2-3:Bank 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number A25 B26 C26 D26 D25 H7 G7 F7 F8 F9 G9 H8 J8 A9 A8 E8 E7 B9 C8 E6 D6 C9 D8 C7 C6 A7 B7 D9 D10 B6 A5 B10 A10 No Connect (NC)

IO_L17N_15 IO_L18P_15 IO_L18N_15 IO_L19P_15 IO_L19N_15 IO_L0P_16 IO_L0N_16 IO_L1P_16 IO_L1N_16 IO_L2P_16 IO_L2N_16 IO_L3P_16 IO_L3N_16 IO_L4P_16 IO_L4N_VREF_16 IO_L5P_16 IO_L5N_16 IO_L6P_16 IO_L6N_16 IO_L7P_16 IO_L7N_16 IO_L8P_CC_16 IO_L8N_CC_16 (2) IO_L9P_CC_16 IO_L9N_CC_16 (2) IO_L10P_CC_16 IO_L10N_CC_16 (2) IO_L11P_CC_16 IO_L11N_CC_16 (2) IO_L12P_VRN_16 IO_L12N_VRP_16 IO_L13P_16 IO_L13N_16

48



Table 2-3:Bank 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number A4 A3 B11 A12 B4 B5 B12 C12 D5 E5 C11 D11 AC26 AD26 AD25 AD24 AE25 AE26 AF25 AF24 AF23 AE23 AE22 AD23 AC24 AC23 AC22 AB22 AF22 AE21 AF20 AE20 AD19 No Connect (NC)

IO_L14P_16 IO_L14N_VREF_16 IO_L15P_16 IO_L15N_16 IO_L16P_16 IO_L16N_16 IO_L17P_16 IO_L17N_16 IO_L18P_16 IO_L18N_16 IO_L19P_16 IO_L19N_16 IO_L0P_17 IO_L0N_17 IO_L1P_17 IO_L1N_17 IO_L2P_17 IO_L2N_17 IO_L3P_17 IO_L3N_17 IO_L4P_17 IO_L4N_VREF_17 IO_L5P_17 IO_L5N_17 IO_L6P_17 IO_L6N_17 IO_L7P_17 IO_L7N_17 IO_L8P_CC_17 IO_L8N_CC_17 (2) IO_L9P_CC_17 IO_L9N_CC_17 (2) IO_L10P_CC_17


49


Table 2-3:Bank 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number AD20 AC21 AD21 AF19 AF18 AE18 AD18 AE17 AF17 AE16 AD16 AD15 AE15 AF15 AF14 AF13 AE13 AD13 AD14 AF12 AE12 V8 V9 AE11 AD11 W9 W8 AD10 AE10 Y7 Y8 AF9 AF10 No Connect (NC)

IO_L10N_CC_17 (2) IO_L11P_CC_17 IO_L11N_CC_17 (2) IO_L12P_VRN_17 IO_L12N_VRP_17 IO_L13P_17 IO_L13N_17 IO_L14P_17 IO_L14N_VREF_17 IO_L15P_17 IO_L15N_17 IO_L16P_17 IO_L16N_17 IO_L17P_17 IO_L17N_17 IO_L18P_17 IO_L18N_17 IO_L19P_17 IO_L19N_17 IO_L0P_18 IO_L0N_18 IO_L1P_18 IO_L1N_18 IO_L2P_18 IO_L2N_18 IO_L3P_18 IO_L3N_18 IO_L4P_18 IO_L4N_VREF_18 IO_L5P_18 IO_L5N_18 IO_L6P_18 IO_L6N_18

50



Table 2-3:Bank 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 NA NA NA NA NA NA NA

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number AA7 AA8 AF7 AF8 AA5 AB5 AB6 AB7 AE8 AE7 AC6 AD5 AE6 AF5 AE5 AD4 AF4 AF3 AD6 AC7 AC8 AD8 AD9 AC9 AB9 AA9 H2 H3 J2 J1 J3 K1 M3 No Connect (NC)

IO_L7P_18 IO_L7N_18 IO_L8P_CC_18 IO_L8N_CC_18 (2) IO_L9P_CC_18 IO_L9N_CC_18 (2) IO_L10P_CC_18 IO_L10N_CC_18 (2) IO_L11P_CC_18 IO_L11N_CC_18 (2) IO_L12P_VRN_18 IO_L12N_VRP_18 IO_L13P_18 IO_L13N_18 IO_L14P_18 IO_L14N_VREF_18 IO_L15P_18 IO_L15N_18 IO_L16P_18 IO_L16N_18 IO_L17P_18 IO_L17N_18 IO_L18P_18 IO_L18N_18 IO_L19P_18 IO_L19N_18 MGTTXP0_112 MGTAVTTTX_112 MGTTXN0_112 MGTRXP0_112 MGTAVTTRX_112 MGTRXN0_112 MGTAVCCPLL_112


51


Table 2-3:Bank NA NA NA NA NA NA NA NA NA NC NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number L1 K3 M1 K4 M2 N3 N2 P5 P4 M5 P2 P3 R2 R1 R3 T1 V3 U1 T3 V1 T4 V2 W3 W2 B2 B3 C2 C1 C3 D1 F3 E1 LX30T, FX30T, LX50T, SX35T, SX50T, FX70T No Connect (NC)

MGTRXN1_112 MGTREFCLKN_112 MGTRXP1_112 MGTREFCLKP_112 MGTTXN1_112 MGTAVTTTX_112 MGTTXP1_112 MGTAVTTRXC MGTRREF_112 NC MGTTXP0_114 MGTAVTTTX_114 MGTTXN0_114 MGTRXP0_114 MGTAVTTRX_114 MGTRXN0_114 MGTAVCCPLL_114 MGTRXN1_114 MGTREFCLKN_114 MGTRXP1_114 MGTREFCLKP_114 MGTTXN1_114 MGTAVTTTX_114 MGTTXP1_114 MGTTXP0_116 MGTAVTTTX_116 MGTTXN0_116 MGTRXP0_116 MGTAVTTRX_116 MGTRXN0_116 MGTAVCCPLL_116 MGTRXN1_116

52




FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number D3 F1 D4 F2 G3 G2 Y2 Y3 AA2 AA1 AA3 AB1 AD3 AC1 AB3 AD1 AB4 AD2 AE3 AE2 A2 D2 E2 K2 L2 T2 U2 AB2 AC2 AF2 C4 F4 J4 No Connect (NC)

MGTREFCLKN_116 MGTRXP1_116 MGTREFCLKP_116 MGTTXN1_116 MGTAVTTTX_116 MGTTXP1_116 MGTTXP0_118 MGTAVTTTX_118 MGTTXN0_118 MGTRXP0_118 MGTAVTTRX_118 MGTRXN0_118 MGTAVCCPLL_118 MGTRXN1_118 MGTREFCLKN_118 MGTRXP1_118 MGTREFCLKP_118 MGTTXN1_118 MGTAVTTTX_118 MGTTXP1_118 GND GND GND GND GND GND GND GND GND GND GND GND GND


53



FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number M4 R4 V4 AA4 AE4 C5 N5 V5 AC5 A6 F6 T6 AF6 J7 W7 B8 M8 AB8 E9 L9 N9 R9 U9 Y9 AE9 H10 K10 M10 P10 T10 V10 A11 L11 No Connect (NC)


54




FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number N11 R11 U11 AA11 AF11 D12 K12 M12 P12 T12 W12 AD12 G13 J13 L13 N13 R13 U13 H14 K14 T14 V14 Y14 C15 J15 L15 U15 W15 AC15 A16 F16 H16 K16 No Connect (NC)



55



FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number M16 P16 T16 V16 AF16 J17 L17 N17 R17 U17 W17 B18 K18 M18 P18 T18 V18 AB18 E19 L19 N19 R19 U19 W19 AE19 C20 H20 V20 A21 L21 T21 AA21 AF21 No Connect (NC)


56




FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number D22 P22 AD22 G23 U23 K24 Y24 C25 N25 AC25 A26 F26 L26 T26 AA26 AF26 U8 K9 M9 P9 T9 W10 M19 P19 T19 V19 Y19 N20 L10 N10 R10 U10 M11 No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT


57



FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number P11 T11 L12 N12 R12 K13 M13 P13 T13 J14 L14 U14 H15 K15 T15 V15 J16 L16 N16 R16 U16 H17 K17 M17 P17 T17 V17 J18 L18 N18 R18 U18 W18 No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

58



Table 2-3:Bank NA 0 0 1 1 2 2 3 3 4 4 11 11 11 12 12 12 13 13 13 15 15 15 16 16 16 17 17 17 18 18 18 NA

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number K19 F11 J12 B13 E14 AA16 AD17 D17 G18 AB13 AE14 J22 M23 H25 H5 L6 P7 W22 R24 V25 F21 B23 E24 D7 G8 C10 AC20 AB23 AE24 AA6 AD7 AC10 L3 No Connect (NC)

VCCINT VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 VCCO_15 VCCO_15 VCCO_15 VCCO_16 VCCO_16 VCCO_16 VCCO_17 VCCO_17 VCCO_17 VCCO_18 VCCO_18 VCCO_18 MGTAVCC_112


59


Table 2-3:Bank NA NA NA NA NA NA NA NA Notes:

FF665 PackageLX30T, FX30T, LX50T, SX35T, SX50T, and FX70TPin Description Pin Number L4 U3 U4 E3 E4 AC3 AC4 N4 No Connect (NC)

MGTAVCC_112 MGTAVCC_114 MGTAVCC_114 MGTAVCC_116 MGTAVCC_116 MGTAVCC_118 MGTAVCC_118 FLOAT


60


FF676 PackageLX30, LX50, LX85, and LX110

FF676 PackageLX30, LX50, LX85, and LX110Table 2-4:Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

FF676 PackageLX30, LX50, LX85, and LX110Pin Description Pin Number R14 R13 M14 M13 N14 P13 P14 N13 K18 J18 L18 K11 K10 J10 J11 N18 P18 R18 T18 U11 W18 V18 Y17 V12 V11 W11 W10 G14 F13 H14 H13 No Connect (NC)



61


Table 2-4:Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number F15 G15 G12 H12 G16 H16 H11 G11 H17 G17 G10 G9 G19 H18 H9 H8 Y10 Y11 AA18 Y18 Y8 AA8 AA17 AB17 AA10 AA9 AB15 AB16 Y12 Y13 AA15 AB14 AA12 No Connect (NC)

IO_L2P_A15_D31_1 IO_L2N_A14_D30_1 IO_L3P_A13_D29_1 IO_L3N_A12_D28_1 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5P_A9_D25_1 IO_L5N_A8_D24_1 IO_L6P_A7_D23_1 IO_L6N_A6_D22_1 IO_L7P_A5_D21_1 IO_L7N_A4_D20_1 IO_L8P_CC_A3_D19_1 IO_L8N_CC_A2_D18_1 (2) IO_L9P_CC_A1_D17_1 IO_L9N_CC_A0_D16_1 (2) IO_L0P_CC_RS1_2 IO_L0N_CC_RS0_2 (2) IO_L1P_CC_A25_2 IO_L1N_CC_A24_2 (2) IO_L2P_A23_2 IO_L2N_A22_2 IO_L3P_A21_2 IO_L3N_A20_2 IO_L4P_FCS_B_2 IO_L4N_VREF_FOE_B_MOSI_2 IO_L5P_FWE_B_2 IO_L5N_CSO_B_2 IO_L6P_D7_2 IO_L6N_D6_2 IO_L7P_D5_2 IO_L7N_D4_2 IO_L8P_D3_2

62



Table 2-4:Bank 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number AB11 AA13 AA14 F14 E13 D13 D14 E12 F12 D15 E15 E10 E11 E16 E17 F9 F10 E18 F19 F8 E8 F18 F17 AD18 AC18 AB10 AB9 AC17 AC16 AC8 AC9 AD15 AD14 No Connect (NC)



63


Table 2-4:Bank 4 4 4 4 4 4 4 4 4 4 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number AD8 AC7 AD13 AC14 AB12 AC11 AC13 AC12 AD11 AD10 G20 F20 E21 E20 E22 E23 F22 F23 G21 G22 H21 H22 J19 H19 H23 J23 J21 J20 K21 K20 K23 K22 L20 No Connect (NC)

IO_L5P_GC_4 IO_L5N_GC_4(1) IO_L6P_GC_4 IO_L6N_GC_4(1) IO_L7P_GC_VRN_4 IO_L7N_GC_VRP_4(1) IO_L8P_CC_GC_4 IO_L8N_CC_GC_4(1)(2) IO_L9P_CC_GC_4 IO_L9N_CC_GC_4(1)(2) IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_11 IO_L8N_CC_11(2) IO_L9P_CC_11 IO_L9N_CC_11(2) IO_L10P_CC_SM15P_11 IO_L10N_CC_SM15N_11(2) IO_L11P_CC_SM14P_11

64



Table 2-4:Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number L19 L23 L22 M22 M21 P19 N19 M20 M19 P23 N23 N22 N21 R22 R23 P21 P20 E7 F7 E6 E5 G6 G7 F5 F4 J6 H7 H6 G5 H4 G4 J5 J4 No Connect (NC)

IO_L11N_CC_SM14N_11(2) IO_L12P_VRN_11 IO_L12N_VRP_11 IO_L13P_11 IO_L13N_11 IO_L14P_11 IO_L14N_VREF_11 IO_L15P_SM13P_11 IO_L15N_SM13N_11 IO_L16P_SM12P_11 IO_L16N_SM12N_11 IO_L17P_SM11P_11 IO_L17N_SM11N_11 IO_L18P_SM10P_11 IO_L18N_SM10N_11 IO_L19P_SM9P_11 IO_L19N_SM9N_11 IO_L0P_12 IO_L0N_12 IO_L1P_12 IO_L1N_12 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12


65


Table 2-4:Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number K6 K7 L7 M7 K5 L5 L4 L3 M5 M6 N7 N6 P3 N3 M4 N4 P5 P4 R3 T3 R6 R5 P6 R7 F24 F25 E25 E26 G26 H26 G24 G25 J25 No Connect (NC)

IO_L8P_CC_12 IO_L8N_CC_12(2) IO_L9P_CC_12 IO_L9N_CC_12(2) IO_L10P_CC_12 IO_L10N_CC_12(2) IO_L11P_CC_12 IO_L11N_CC_12(2) IO_L12P_VRN_12 IO_L12N_VRP_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_VREF_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L0P_SM8P_13 IO_L0N_SM8N_13 IO_L1P_SM7P_13 IO_L1N_SM7N_13 IO_L2P_SM6P_13 IO_L2N_SM6N_13 IO_L3P_SM5P_13 IO_L3N_SM5N_13 IO_L4P_13

66



Table 2-4:Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number J26 H24 J24 L24 L25 K25 K26 M25 M26 M24 N24 P26 N26 P25 P24 R25 R26 T24 T25 V26 U26 U24 U25 W25 W26 Y25 Y26 AB25 AA25 AC26 AB26 E2 E1 No Connect (NC)

IO_L4N_VREF_13 IO_L5P_SM4P_13 IO_L5N_SM4N_13 IO_L6P_SM3P_13 IO_L6N_SM3N_13 IO_L7P_SM2P_13 IO_L7N_SM2N_13 IO_L8P_CC_SM1P_13 IO_L8N_CC_SM1N_13(2) IO_L9P_CC_SM0P_13 IO_L9N_CC_SM0N_13(2) IO_L10P_CC_13 IO_L10N_CC_13(2) IO_L11P_CC_13 IO_L11N_CC_13(2) IO_L12P_VRN_13 IO_L12N_VRP_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_VREF_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L0P_14 IO_L0N_14


67


Table 2-4:Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number F3 E3 G1 H1 F2 G2 K3 K2 H3 J3 L2 K1 J1 H2 M1 N1 M2 N2 P1 R1 T2 R2 U2 U1 V2 V1 Y1 W1 AA2 Y2 AB2 AB1 AC2 No Connect (NC)

IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_14 IO_L8N_CC_14(2) IO_L9P_CC_14 IO_L9N_CC_14(2) IO_L10P_CC_14 IO_L10N_CC_14(2) IO_L11P_CC_14 IO_L11N_CC_14(2) IO_L12P_VRN_14 IO_L12N_VRP_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_VREF_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L17P_14

68



Table 2-4:Bank 14 14 14 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number AC1 AE1 AD1 AF2 AE2 C14 B14 A14 A15 B15 B16 D16 C16 D18 C17 B17 A17 A18 A19 B19 C18 A20 B20 C19 D19 D21 D20 C21 B21 D23 C22 B22 A22 No Connect (NC)

IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L0P_15 IO_L0N_15 IO_L1P_15 IO_L1N_15 IO_L2P_15 IO_L2N_15 IO_L3P_15 IO_L3N_15 IO_L4P_15 IO_L4N_VREF_15 IO_L5P_15 IO_L5N_15 IO_L6P_15 IO_L6N_15 IO_L7P_15 IO_L7N_15 IO_L8P_CC_15 IO_L8N_CC_15(2) IO_L9P_CC_15 IO_L9N_CC_15(2) IO_L10P_CC_15 IO_L10N_CC_15(2) IO_L11P_CC_15 IO_L11N_CC_15(2) IO_L12P_VRN_15 IO_L12N_VRP_15 IO_L13P_15 IO_L13N_15


69


Table 2-4:Bank 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number A23 A24 B24 C23 D24 C24 B25 A25 B26 C26 D26 D25 D11 D10 C11 C12 C13 B12 A13 A12 C9 D9 B9 B10 B11 A10 A9 A8 D8 C8 B7 A7 D5 No Connect (NC)

IO_L14P_15 IO_L14N_VREF_15 IO_L15P_15 IO_L15N_15 IO_L16P_15 IO_L16N_15 IO_L17P_15 IO_L17N_15 IO_L18P_15 IO_L18N_15 IO_L19P_15 IO_L19N_15 IO_L0P_16 IO_L0N_16 IO_L1P_16 IO_L1N_16 IO_L2P_16 IO_L2N_16 IO_L3P_16 IO_L3N_16 IO_L4P_16 IO_L4N_VREF_16 IO_L5P_16 IO_L5N_16 IO_L6P_16 IO_L6N_16 IO_L7P_16 IO_L7N_16 IO_L8P_CC_16 IO_L8N_CC_16(2) IO_L9P_CC_16 IO_L9N_CC_16(2) IO_L10P_CC_16

70



Table 2-4:Bank 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number D6 C6 C7 A4 A5 B5 B6 D3 D4 C4 B4 C2 C3 A2 A3 D1 C1 B1 B2 T23 T22 R21 R20 T20 T19 U22 U21 W24 W23 V24 V23 AA23 AA24 No Connect (NC)

IO_L10N_CC_16(2) IO_L11P_CC_16 IO_L11N_CC_16(2) IO_L12P_VRN_16 IO_L12N_VRP_16 IO_L13P_16 IO_L13N_16 IO_L14P_16 IO_L14N_VREF_16 IO_L15P_16 IO_L15N_16 IO_L16P_16 IO_L16N_16 IO_L17P_16 IO_L17N_16 IO_L18P_16 IO_L18N_16 IO_L19P_16 IO_L19N_16 IO_L0P_17 IO_L0N_17 IO_L1P_17 IO_L1N_17 IO_L2P_17 IO_L2N_17 IO_L3P_17 IO_L3N_17 IO_L4P_17 IO_L4N_VREF_17 IO_L5P_17 IO_L5N_17 IO_L6P_17 IO_L6N_17


71


Table 2-4:Bank 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number Y23 Y22 AC23 AC22 AB24 AC24 AB22 AA22 AC21 AB21 V21 V22 W21 W20 U19 U20 V19 W19 Y21 Y20 AD19 AC19 AB20 AB19 AA20 AA19 V3 U4 T5 T4 T7 U7 U5 No Connect (NC)

IO_L7P_17 IO_L7N_17 IO_L8P_CC_17 IO_L8N_CC_17(2) IO_L9P_CC_17 IO_L9N_CC_17(2) IO_L10P_CC_17 IO_L10N_CC_17(2) IO_L11P_CC_17 IO_L11N_CC_17(2) IO_L12P_VRN_17 IO_L12N_VRP_17 IO_L13P_17 IO_L13N_17 IO_L14P_17 IO_L14N_VREF_17 IO_L15P_17 IO_L15N_17 IO_L16P_17 IO_L16N_17 IO_L17P_17 IO_L17N_17 IO_L18P_17 IO_L18N_17 IO_L19P_17 IO_L19N_17 IO_L0P_18 IO_L0N_18 IO_L1P_18 IO_L1N_18 IO_L2P_18 IO_L2N_18 IO_L3P_18

72



Table 2-4:Bank 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number U6 V4 W4 W3 Y3 V6 V7 W5 W6 Y6 Y5 AA4 AA5 Y7 AA7 AB4 AA3 AC4 AC3 AD4 AD3 AB6 AB5 AC6 AB7 AF3 AE3 AD6 AD5 AF5 AF4 AE6 AE5 No Connect (NC)

IO_L3N_18 IO_L4P_18 IO_L4N_VREF_18 IO_L5P_18 IO_L5N_18 IO_L6P_18 IO_L6N_18 IO_L7P_18 IO_L7N_18 IO_L8P_CC_18 IO_L8N_CC_18(2) IO_L9P_CC_18 IO_L9N_CC_18(2) IO_L10P_CC_18 IO_L10N_CC_18(2) IO_L11P_CC_18 IO_L11N_CC_18(2) IO_L12P_VRN_18 IO_L12N_VRP_18 IO_L13P_18 IO_L13N_18 IO_L14P_18 IO_L14N_VREF_18 IO_L15P_18 IO_L15N_18 IO_L16P_18 IO_L16N_18 IO_L17P_18 IO_L17N_18 IO_L18P_18 IO_L18N_18 IO_L19P_18 IO_L19N_18


73


Table 2-4:Bank 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number AD24 AD23 AE26 AD26 AF24 AF25 AE25 AD25 AF23 AE23 AD20 AD21 AE20 AE21 AF22 AE22 AF18 AE18 AF19 AF20 AF17 AE17 AE16 AD16 AF15 AE15 AF14 AF13 AF12 AE13 AE12 AE11 AF10 No Connect (NC) LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30 LX30

IO_L0P_21 IO_L0N_21 IO_L1P_21 IO_L1N_21 IO_L2P_21 IO_L2N_21 IO_L3P_21 IO_L3N_21 IO_L4P_21 IO_L4N_VREF_21 IO_L5P_21 IO_L5N_21 IO_L6P_21 IO_L6N_21 IO_L7P_21 IO_L7N_21 IO_L8P_CC_21 IO_L8N_CC_21(2) IO_L9P_CC_21 IO_L9N_CC_21(2) IO_L10P_CC_21 IO_L10N_CC_21(2) IO_L11P_CC_21 IO_L11N_CC_21(2) IO_L12P_VRN_21 IO_L12N_VRP_21 IO_L13P_21 IO_L13N_21 IO_L14P_21 IO_L14N_VREF_21 IO_L15P_21 IO_L15N_21 IO_L16P_21

74



Table 2-4:Bank 21 21 21 21 21 21 21 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number AE10 AF9 AF8 AF7 AE7 AE8 AD9 A1 F1 L1 T1 AA1 AF1 D2 P2 AD2 B3 G3 M3 U3 K4 Y4 AE4 C5 N5 AC5 A6 F6 T6 AF6 J7 P7 W7 No Connect (NC) LX30 LX30 LX30 LX30 LX30 LX30 LX30

IO_L16N_21 IO_L17P_21 IO_L17N_21 IO_L18P_21 IO_L18N_21 IO_L19P_21 IO_L19N_21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND


75



FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number B8 K8 M8 P8 T8 V8 AB8 E9 J9 L9 N9 R9 U9 W9 AE9 H10 M10 P10 T10 V10 A11 L11 N11 R11 AA11 AF11 D12 K12 M12 P12 T12 AD12 B13 No Connect (NC)


76




FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number G13 J13 L13 U13 W13 K14 T14 V14 Y14 AE14 C15 J15 L15 N15 R15 U15 W15 AC15 A16 F16 K16 M16 P16 T16 V16 Y16 AF16 J17 L17 N17 R17 U17 W17 No Connect (NC)



77



FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number B18 G18 M18 U18 AB18 E19 K19 R19 Y19 AE19 H20 V20 A21 L21 AA21 AF21 D22 P22 AD22 G23 U23 K24 Y24 C25 N25 AC25 A26 F26 L26 T26 AA26 AF26 J8 No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX

78




FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number L8 N8 R8 U8 W8 W16 K17 M17 P17 T17 V17 K9 M9 P9 T9 V9 L10 N10 R10 U10 M11 P11 T11 J12 L12 N12 R12 U12 K13 T13 V13 J14 L14 No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT


79


Table 2-4:Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 1 1 2 2 3 3 4 4 11 11 11 12 12 12 13 13 13

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number U14 W14 H15 K15 M15 P15 T15 V15 Y15 J16 L16 N16 U16 R16 Y9 W12 C10 F11 AA16 AD17 E14 D17 AC10 AB13 F21 J22 H25 J2 H5 L6 N20 M23 R24 No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_11 VCCO_11 VCCO_11 VCCO_12 VCCO_12 VCCO_12 VCCO_13 VCCO_13 VCCO_13

80



Table 2-4:Bank 14 14 14 15 15 15 16 16 16 17 17 17 18 18 18 21 21 21 Notes:

FF676 PackageLX30, LX50, LX85, and LX110 (Continued)Pin Description Pin Number W2 R4 V5 C20 B23 E24 E4 D7 G8 T21 W22 V25 AB3 AA6 AD7 AC20 AB23 AE24 No Connect (NC)

VCCO_14 VCCO_14 VCCO_14 VCCO_15 VCCO_15 VCCO_15 VCCO_16 VCCO_16 VCCO_16 VCCO_17 VCCO_17 VCCO_17 VCCO_18 VCCO_18 VCCO_18 VCCO_21 VCCO_21 VCCO_21

1. Do not connect a single ended clock to the N-side of the differential clock pair of pins, for example, IO_L3N_GC_3. 2. Do not connect a single-ended clock to the N-side of clock capable pins, for example, IO_L8N_CC_11. 3. RSVD pins must be tied to GND (logic 0).


81


FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T, and FX100TTable 2-5: FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T and FX100TBank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Pin Description Pin Number W18 W17 T18 T17 U18 V17 V18 U17 L23 M22 M23 P15 M15 N15 N14 N22 N23 AB23 AC23 AB15 AD21 AD22 AC22 AC14 AC15 AD15 AD14 L21 L20 L15 No Connect (NC)

DXP_0 DXN_0 AVDD_0 AVSS_0 VP_0 VN_0 VREFP_0 VREFN_0 VBATT_0 PROGRAM_B_0 HSWAPEN_0 D_IN_0 DONE_0 CCLK_0 INIT_B_0 CS_B_0 RDWR_B_0 RSVD(3) RSVD(3) TCK_0 M0_0 M2_0 M1_0 TMS_0 TDI_0 D_OUT_BUSY_0 TDO_0 IO_L0P_A19_1 IO_L0N_A18_1 IO_L1P_A17_1

82


FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T, and FX100T

Table 2-5: FF1136 PackageLX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T and FX100T (Continued)Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pin Description Pin Number L16 J22 K21 K16 J15 G22 H22 L14 K14 K23 K22 J12 H12 G23 H23 K13 K12 AE13 AE12 AF23 AG23 AF13 AG12 AE22 AE23 AE14 AF14 AF20 AF21 AF15 AE16 AE21 No Connect (NC)

IO_L1N_A16_1 IO_L2P_A15_D31_1 IO_L2N_A14_D30_1 IO_L3P_A13_D29_1 IO_L3N_A12_D28_1 IO_L4P_A11_D27_1 IO_L4N_VREF_A10_D26_1 IO_L5P_A9_D25_1 IO_L5N_A8_D24_1 IO_L6P_A7_D23_1 IO_L6N_A6_D22_1 IO_L7P_A5_D21_1 IO_L7N_A4_D20_1 IO_L8P_CC_A3_D19_1 IO_L8N_CC_A2_D18_1(2) IO_L9P_CC_A1_D17_1 IO_L9N_CC_A0_D16_1(2) IO_L0P_CC_RS1_2 IO_L0N_CC_RS0_2(2) IO_L1P_CC_A25_2 IO_L1N_CC_A24_2(2) IO_L2P_A23_2 IO_L2N_A22_2 IO_L3P_A21_2 IO_L3N_A20_2 IO_L4P_FCS_B_2 IO_L4N_VREF_FOE_B_MOSI_2 IO_L5P_FWE_B_2 IO_L5N_CSO_B_2 IO_L6P_D7_2 IO_L6N_D6_2 IO_L7P_D5_2


83


Table 2-5: FF1136 Pa

Date post:	02-Dec-2014
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