Datasheet for Telink
BLE SoC TLSR8266/
TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19
Ver 2.0.2
2015/06/02
TE
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KS
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Keyword:
Features; Package; Pin layout; Working mode;
Memory; MCU; RF Transceiver; Baseband; Clock;
Timers; Interrupt; Interface; PWM; KeyScan; Audio;
QDEC; ADC; PGA; Electrical specification; Application
Brief:
This datasheet is dedicated for Telink BLE SoC TLSR8266
(without internal flash) / TLSR8266F512 (with internal
flash). In this datasheet, key features, working mode,
main modules, electrical specification and application of
the TLSR8266/TLSR8266F512 are introduced.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 1 Ver2.0.2
Published by Telink Semiconductor Bldg 3, 1500 Zuchongzhi Rd, Zhangjiang Hi-Tech Park, Shanghai, China © Telink Semiconductor All Right Reserved
Legal Disclaimer
Telink Semiconductor reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Telink Semiconductor
disclaims any and all liability for any errors, inaccuracies or incompleteness contained
herein or in any other disclosure relating to any product.
Telink Semiconductor does not assume any liability arising out of the application or
use of any product or circuit described herein; neither does it convey any license
under its patent rights, nor the rights of others
The products shown herein are not designed for use in medical, life-saving, or
life-sustaining applications. Customers using or selling Telink Semiconductor products
not expressly indicated for use in such applications do so entirely at their own risk and
agree to fully indemnify Telink Semiconductor for any damages arising or resulting
from such use or sale.
Information:
For further information on the technology, product and business term, please contact
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For sales or technical support, please send email to the address of:
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 2 Ver2.0.2
Revision History
Version Major Changes Date Author
0.8 Preliminary release 2014/3 Cynthia
1.0
Mainly added section 11~13, and updated
section 1, 7, 10, 14.
Added TLSR8266ET48 package.
2014/5 Cynthia
1.01 Updated section 14.4 2014/5 Cynthia
1.1 Updated section 15 2014/5 Cynthia
1.2 Mainly updated section 1 and section 15 2014/7 Cynthia
1.3 Updated section 4 2014/7 Cynthia
1.4 Mainly updated section 1, section 6 and
section 15 2014/8 Cynthia
1.41 Updated section 14.3 2014/8 Cynthia
1.42 Updated section 1 and section 3 2014/8 Cynthia
1.5 Updated section 8 2014/10 Cynthia
1.6 Added section 2.5, updated section 7.1 and 7.3 2015/1 S.G.J., Cynthia
1.7 Updated section 2.3 2015/1 S.G.J., Cynthia
1.71 Updated section 14.4 2015/3 Cynthia
1.8 Updated section 2.5, 4.4.2, 5, 7.1.3, 7.4, 12 and
14.4 2015/3 Cynthia
1.9 Updated section 1 and 14.2 2015/3 Cynthia
1.91 Updated section 12.5~12.6 and 12.9 2015/4 Cynthia
2.0 Updated section 1.6 and 7.1 2015/4 S.G.J., Cynthia
2.01 Mainly updated section 1.6, 7.1.1.2 and 12.3
Modified Figure 13-1 2015/5 L.L.J., Cynthia
2.0.2 Updated package dimension figures (Figure
1-2~1-4 in section 1.5) 2015/6 X.S.J., Cynthia Te
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 3 Ver2.0.2
1 Table of contents
1 Overview ............................................................................................................... 10
1.1 Block diagram .............................................................................................. 10
1.2 Key features ................................................................................................. 11
1.2.1 General features ..................................................................................... 11
1.2.2 RF Features ............................................................................................. 12
1.2.3 Features of power management module ............................................... 12
1.3 Typical applications ...................................................................................... 12
1.4 Ordering information ................................................................................... 13
1.5 Package ........................................................................................................ 15
1.6 Pin layout ..................................................................................................... 19
1.7 Telink SDK .................................................................................................... 32
2 Memory and MCU ................................................................................................ 33
2.1 Memory ....................................................................................................... 33
2.2 MCU ............................................................................................................. 34
2.3 Working modes ............................................................................................ 34
2.3.1 Active mode ............................................................................................ 34
2.3.2 Idle mode ................................................................................................ 34
2.3.3 Power-saving mode ................................................................................ 35
2.4 Reset, Wakeup and Power down enabling .................................................... 35
2.5 Wakeup sources ............................................................................................. 37
2.5.1 Wakeup source - USB.............................................................................. 37
2.5.2 Wakeup source – 32K timer ................................................................... 37
2.5.3 Wakeup source – pad ............................................................................. 37
3 2.4G RF Transceiver .............................................................................................. 39
3.1 Block diagrams ............................................................................................. 39
3.2 Function description .................................................................................... 39
3.2.1 Turn on/off .............................................................................................. 39
3.2.2 Air interface data rate and RF channel frequency .................................. 39
3.3 Baseband ..................................................................................................... 40
3.3.1 Packet format ......................................................................................... 40
3.3.2 RSSI.......................................................................................................... 40
4 Clock ..................................................................................................................... 41
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 4 Ver2.0.2
4.1 Clock sources ............................................................................................... 41
4.2 Register table ............................................................................................... 41
4.3 System clock ................................................................................................ 43
4.4 Module clock ................................................................................................ 44
4.4.1 ADC clock ................................................................................................ 44
4.4.2 DMIC clock .............................................................................................. 44
5 Timers ................................................................................................................... 46
5.1 Timer0~Timer2 ............................................................................................ 46
5.1.1 Register table .......................................................................................... 46
5.1.2 Mode0 (System Clock Mode) .................................................................. 48
5.1.3 Mode1 (GPIO Trigger Mode) .................................................................. 48
5.1.4 Mode2 (GPIO Pulse Width Mode) .......................................................... 49
5.1.5 Mode3 (Tick Mode) ................................................................................ 50
5.1.6 Watchdog ................................................................................................ 51
5.2 32K LTIMER .................................................................................................. 52
5.3 System Timer ............................................................................................... 52
6 Interrupt System ................................................................................................... 53
6.1 Interrupt structure ....................................................................................... 53
6.2 Register configuration ................................................................................. 53
6.2.1 Enable/Mask interrupt sources .............................................................. 54
6.2.2 Interrupt mode and priority ................................................................... 54
6.2.3 Interrupt source flag ............................................................................... 55
7 Interface ............................................................................................................... 56
7.1 GPIO ............................................................................................................. 56
7.1.1 Basic configuration ................................................................................. 56
7.1.1.1 Multiplexed functions ........................................................................ 56
7.1.1.2 Drive strength .................................................................................... 57
7.1.1.3 GPIO lookup table .............................................................................. 57
7.1.2 Connection relationship between GPIO and related modules ............... 61
7.1.3 Pull-up/Pull-down resistor ...................................................................... 64
7.2 SWM and SWS ............................................................................................. 70
7.3 I2C ................................................................................................................ 70
7.3.1 Communication protocol ........................................................................ 70
7.3.2 Register table .......................................................................................... 71
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 5 Ver2.0.2
7.3.3 I2C Slave mode........................................................................................ 72
7.3.3.1 DMA mode......................................................................................... 73
7.3.3.2 Mapping mode .................................................................................. 74
7.3.4 I2C Master mode .................................................................................... 74
7.3.4.1 I2C Master Write transfer ...................................................................... 75
7.3.4.2 I2C Master Read transfer ....................................................................... 75
7.4 SPI ................................................................................................................ 76
7.4.1 Register table ............................................................................................... 76
7.4.2 SPI Master mode ......................................................................................... 77
7.4.3 SPI Slave mode ............................................................................................ 78
7.5 UART ............................................................................................................ 79
8 PWM ..................................................................................................................... 83
8.1 Register table ............................................................................................... 83
8.2 Enable PWM ................................................................................................ 86
8.3 Set PWM clock ............................................................................................. 86
8.4 PWM waveform, polarity and output inversion .......................................... 86
8.4.1 PWM waveform ...................................................................................... 86
8.4.2 Invert PWM output ................................................................................. 87
8.4.3 Polarity for signal frame ......................................................................... 87
8.5 PWM mode .................................................................................................. 88
8.5.1 Select PWM mode .................................................................................. 88
8.5.2 Continuous mode ................................................................................... 88
8.5.3 Counting mode ....................................................................................... 88
8.5.4 IR mode ................................................................................................... 89
8.6 PWM interrupt ............................................................................................. 90
9 Keyscan ................................................................................................................. 91
9.1 Register table ............................................................................................... 91
9.2 Keyscan enable ............................................................................................ 95
9.3 Keyscan IO configuration ............................................................................. 96
9.4 Keyscan flow and frame ............................................................................... 97
9.5 Keyscan FIFO buffer ..................................................................................... 99
10 Audio .................................................................................................................. 100
10.1 Audio input path .......................................................................................... 100
10.2 Audio input processing ................................................................................ 100
10.3 Audio output path ....................................................................................... 102
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 6 Ver2.0.2
10.3.1 Rate Matching ......................................................................................... 102
10.3.2 SDM ....................................................................................................... 103
10.3.3 Register configuration ........................................................................ 104
10.4 Audio performance ...................................................................................... 105
11 Quadrature Decoder .......................................................................................... 107
11.1 Input pin selection ....................................................................................... 107
11.2 Common mode and double accuracy mode................................................ 108
11.3 QDEC interrupt............................................................................................. 110
11.4 QDEC reset ................................................................................................... 110
11.5 Other configuration ..................................................................................... 110
11.6 Register table ............................................................................................... 111
12 ADC ..................................................................................................................... 113
12.1 ADC clock ..................................................................................................... 113
12.2 Set period ..................................................................................................... 113
12.3 Select ADC input range ................................................................................ 114
12.4 Select resolution and sampling time ........................................................... 114
12.5 Select input mode and channel ................................................................... 114
12.6 Enable auto mode and output ..................................................................... 115
12.7 ADC done signal ........................................................................................... 115
12.8 ADC status .................................................................................................... 115
12.9 Register table ............................................................................................... 116
13 PGA ..................................................................................................................... 119
13.1 Left/Right channel enabling ......................................................................... 119
13.2 Input channel selection ............................................................................... 119
13.3 Gain setting .................................................................................................. 119
13.4 PGA output .................................................................................................. 120
13.5 Register table ............................................................................................... 120
14 Key Electrical Specifications ............................................................................... 123
14.1 Absolute maximum ratings .......................................................................... 123
14.2 Recommended operating condition ............................................................ 123
14.3 DC characteristics ........................................................................................ 124
14.4 AC characteristics ......................................................................................... 124
15 Applications ........................................................................................................ 128
15.1 Application example for the TLSR8266ET48 ................................................ 128
15.1.1 Schematic .............................................................................................. 128
15.1.2 Layout ................................................................................................... 130
15.1.3 BOM (Bill of Material) ........................................................................... 131
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 7 Ver2.0.2
2 Table of Figures
Figure 1- 1 Block diagram of the system .............................................................. 10
Figure 1- 2 Package dimension for the TLSR8266ET/AT56 (Unit: mm) ................ 16
Figure 1- 3 Package dimension for the TLSR8266ET/AT48/TLSR8266F512ET/AT48
17
Figure 1- 4 Package dimension for the TLSR8266ET/AT32/ TLSR8266F512ET/AT32
19
Figure 1- 5 Pin assignment for the TLSR8266ET/AT56 ......................................... 19
Figure 1- 6 Pin assignment for the TLSR8266ET/AT48 ......................................... 22
Figure 1- 7 Pin assignment for the TLSR8266ET/AT32 ......................................... 25
Figure 1- 8 Pin assignment for the TLSR8266F512ET/AT48 ................................. 27
Figure 1- 9 Pin assignment for the TLSR8266F512ET/AT32 ................................. 30
Figure 2- 1 Physical memory map ....................................................................... 33
Figure 2- 2 MCU memory map ............................................................................ 33
Figure 2- 3 Transition chart of working modes .................................................... 34
Figure 2- 4 Wakeup sources ............................................................................... 37
Figure 3- 1 Block diagram of RF transceiver ........................................................ 39
Figure 4- 1 Block diagram of system clock ........................................................... 43
Figure 7- 1 Logic relationship between GPIO and related modules .................... 61
Figure 7- 2 I2C timing chart ................................................................................. 70
Figure 7- 3 Byte consisted of slave address and R/W flag bit .............................. 72
Figure 7- 4 Read format in DMA mode ................................................................ 73
Figure 7- 5 Write format in DMA mode .............................................................. 73
Figure 7- 6 Read format in Mapping mode.......................................................... 74
Figure 7- 7 Write format in Mapping mode ......................................................... 74
Figure 7- 8 SPI write/read command format ....................................................... 79
Figure 7- 9 UART communication ........................................................................ 79
Figure 8- 1 PWM output waveform chart ........................................................... 87
Figure 8-2 Continuous mode .............................................................................. 88
Figure 8-3 Counting mode .................................................................................. 89
Figure 8-4 IR mode .............................................................................................. 90
Figure 9- 1 Keyscan flow and frame .................................................................... 98
Figure 9- 2 Keyscan Module Scaning sequence in a frame .................................. 98
Figure 9- 3 Keyscan FIFO buffer ........................................................................... 99
Figure 10- 1 Audio input path .............................................................................. 100
Figure 10- 2 Audio input processing .................................................................... 101
Figure 10- 3 Audio output path ........................................................................... 102
Figure 10- 4 Linear interpolation ......................................................................... 103
Figure 10- 5 Block diagram of SDM ..................................................................... 103
Figure 11- 1 Common mode ................................................................................ 109
Figure 11- 2 Double accuracy mode .................................................................... 110
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 8 Ver2.0.2
Figure 11- 3 Shuttle mode ................................................................................... 111
Figure 12- 1 Sampling and analog-to-digital conversion process ........................ 113
Figure 13- 1 PGA block diagram .......................................................................... 119
Figure 15-1 Schematic for the TLSR8266ET48 .................................................... 129
Figure 15-2 Layout for the TLSR8266ET48 .......................................................... 130
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 9 Ver2.0.2
3 Table of Tables
Table 1- 1 Ordering information of the TLSR8266/TLSR8266F512 .................... 13
Table 1- 2 Pin functions for the TLSR8266ET/AT56 ............................................ 20
Table 1- 3 Pin functions for the TLSR8266ET/AT48 ............................................ 22
Table 1- 4 Pin functions for the TLSR8266ET/AT32 ............................................ 25
Table 1- 5 Pin functions for the TLSR8266F512ET/AT48 .................................... 27
Table 1- 6 Pin functions for the TLSR8266F512ET/AT32 .................................... 30
Table 2- 1 Register configuration for reset, wakeup and power down enabling35
Table 2- 2 Analog registers for Wakeup.............................................................. 38
Table 3- 1 Packet Format .................................................................................... 40
Table 4- 1 Register table for clock ...................................................................... 41
Table 5- 1 Register configuration for Timer0~Timer2 ........................................ 46
Table 6- 1 Register table for Interrupt system .................................................... 53
Table 7- 1 GPIO lookup table .............................................................................. 57
Table 7- 2 GPIO lookup table2 ............................................................................ 62
Table 7- 3 Analog registers for pull-up/pull-down resistor control .................... 64
Table 7- 4 Register configuration for I2C ............................................................ 71
Table 7- 5 Register configuration for SPI ............................................................ 76
Table 7- 6 SPI mode ............................................................................................ 78
Table 7- 7 Register configuration for UART ........................................................ 80
Table 8- 1 Register table for PWM ..................................................................... 83
Table 9- 1 Register table for Keyscan ................................................................. 91
Table 9- 2 IO configuration for Columns ............................................................ 96
Table 9- 3 IO configuration for Rows .................................................................. 97
Table 10- 1 Audio data flow direction ................................................................ 100
Table 10- 2 Register configuration related to audio input processing ............... 101
Table 10- 3 Register configuration related to audio output path ...................... 104
Table 10- 4 Codec output with 32ohm load performance ................................. 105
Table 11- 1 Input pin selection ........................................................................... 107
Table 11- 2 Register table for QDEC ................................................................... 111
Table 12- 1 Register table related to SAR ADC ................................................... 116
Table 13- 1 Analog register table related to PGA ............................................... 120
Table 13- 2 Digital register related to PGA ......................................................... 122
Table 14- 1 Absolute Maximum Ratings ............................................................. 123
Table 14- 2 Recommended operation condition ................................................ 123
Table 14- 3 DC characteristics ............................................................................ 124
Table 14- 4 AC Characteristics ............................................................................ 124
Table 15- 1 BOM table for the TLSR8266ET48 ................................................... 131
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 10 Ver2.0.2
1 Overview
The TLSR8266/TLSR8266F512 is Telink-developed BLE SoC solution which is fully
standard compliant and allows easy connectivity with Bluetooth Smart Ready mobile
phones, tablets, laptops. The TLSR8266/TLSR8266F512 supports BLE slave and master
mode operation, including broadcast, encryption, connection updates, and channel
map updates. It’s completely RoHS-compliant and 100% lead (Pb)-free.
1.1 Block diagram
The TLSR8266/TLSR8266F512 is designed to offer high integration, ultra-low
power application capabilities. It integrates strong 32-bit MCU, BLE/2.4G Radio, 16KB
SRAM, 128/256/512KB external FLASH (TLSR8266) or 512KB internal Flash
(TLSR8266F512), 14bit ADC with PGA, 6-channel PWM, three quadrature decoders, a
hardware keyboard scanner(Keyscan), abundant GPIO interfaces, multi-stage power
management module and nearly all the peripherals needed for Bluetooth Low Energy
applications development. The system’s block diagram is as shown in Figure 1-1:
RISC 32bit MCU
PGA14bit ADC
Timer0/1/2Watchdog
I2C
SPI
UART
GPIO
USB
12MHz/16MHz Crystal Oscillator
32.768KHz Crystal Oscillator
32MHz RC Oscillator
32KHz RC Oscillator
CLOCK
RESET
POWER-ON RESET
LDO
POWER Management
ControllerBROWN OUT
BLE/2.4G Radio
POWER MANAGEMENT
DMIC
Debug Interface
3 Quadrature Decoders
16KB SRAM
128/256/512KB FLASH
MEMORY
SDM
AMIC
PWM
Keyscan
Figure 1- 1 Block diagram of the system
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 11 Ver2.0.2
With the high integration level of TLSR8266/TLSR8266F512, few external
components are needed to satisfy customers’ ultra-low cost requirements.
1.2 Key features
1.2.1 General features
General features are as follows:
1) Embed 32-bit high performance MCU with clock up to 48MHz.
2) Program memory: external 128/256/512KB FLASH (TLSR8266) or internal
512KB Flash (TLSR8266F512).
3) Data memory: 16KB on-chip SRAM.
4) 12MHz/16MHz & 32.768KHz Crystal and 32KHz/32MHz embedded RC
oscillator.
5) A rich set of I/Os:
TLSR8266: Up to 41/37/22 GPIOs depending on package option;
TLSR8266F512: Up to 35/20 GPIOs depending on package option;
DMIC (Digital Mic);
AMIC (Analog Mic);
Mono-channel Audio output;
SPI;
I2C;
UART;
USB;
Debug Interface.
6) Up to 6 channels of PWM.
7) Sensor:
14bit ADC with PGA;
Temperature sensor.
8) Three quadrature decoders.
9) Embeds hardware AES.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 12 Ver2.0.2
10) Compatible with USB2.0 Full speed mode.
11) Operating temperature:
ET versions: -40℃~+85℃ temperature range;
AT versions: -40℃~+125℃ temperature range.
1.2.2 RF Features
RF features include:
1) BLE/2.4GHz RF transceiver embedded, working in worldwide 2.4GHz ISM
band.
2) Bluetooth 4.0 Compliant, 1Mbps and 2.4GHz 2Mbps Boost Mode.
3) -92dBm BT4.0 Rx Sensitivity.
4) RF link data rate up to 2Mbps.
5) Tx output power up to +8dBm.
6) Single-pin antenna interface.
7) RSSI monitoring.
1.2.3 Features of power management module
Features of power management module include:
1) Embedded LDO.
2) Battery monitor: Supports low battery detection.
3) Power supply: 1.9V~3.6V
4) Multiple stage power management to minimize power consumption.
5) Low power consumption:
13mA Receiver mode
13mA Transmitter mode
Suspend mode current: 20uA
Deep sleep mode current: 0.7uA
1.3 Typical applications
Typical applications for the TLSR8266/TLSR8266F512 are as follows:
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 13 Ver2.0.2
Smartphone accessories
PC and tablet peripherals, including Mouse / Keyboard
Remote Control and 3D glasses
Wireless Microphone
Health monitoring
Sports and fitness tracking
Wearable devices
1.4 Ordering information
Table 1- 1 Ordering information of the TLSR8266/TLSR8266F512
PRODUCT PACKAGE
TYPE
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING NUMBER
TRANSPORT
MEDIA,
QUANTITY
TLSR8266
56-pin
7×7mm
TQFN
-40℃~+85℃ TLSR8266ET56
TLSR8266ET56CL Large Tape and
Reel, 3000
TLSR8266ET56CT Small Tape and
Reel, 300
TLSR8266ET56C Rail, 100
-40℃~+125℃ TLSR8266AT56
TLSR8266AT56CL Large Tape and
Reel, 3000
TLSR8266AT56CT Small Tape and
Reel, 300
TLSR8266AT56C Rail, 100
48-pin
7×7mm
TQFN
-40℃~ +85℃ TLSR8266ET48
TLSR8266ET48CL Large Tape and
Reel, 3000
TLSR8266ET48CT Small Tape and
Reel, 300
TLSR8266ET48C Rail, 100
-40℃~+125℃ TLSR8266AT48
TLSR8266AT48CL Large Tape and
Reel, 3000
TLSR8266AT48CT Small Tape and
Reel, 300
TLSR8266AT48C Rail, 100
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 14 Ver2.0.2
PRODUCT PACKAGE
TYPE
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING NUMBER
TRANSPORT
MEDIA,
QUANTITY
32-pin
5×5mm
TQFN
-40℃~+85℃ TLSR8266ET32
TLSR8266ET32CL Large Tape and
Reel, 3000
TLSR8266ET32CT Small Tape and
Reel, 300
TLSR8266ET32C Rail, 100
-40℃~+125℃ TLSR8266AT32
TLSR8266AT32CL Large Tape and
Reel, 3000
TLSR8266AT32CT Small Tape and
Reel, 300
TLSR8266AT32C Rail, 100
TLSR8266F512
48-pin
7×7mm
TQFN
-40℃~+85℃ TLSR8266F512
ET48
TLSR8266F512ET48CL Large Tape and
Reel, 3000
TLSR8266F512ET48CT Small Tape and
Reel, 300
TLSR8266F512ET48C Rail, 100
-40℃~+125℃ TLSR8266F512
AT48
TLSR8266F512AT48CL Large Tape and
Reel, 3000
TLSR8266F512AT48CT Small Tape and
Reel, 300
TLSR8266F512AT48C Rail, 100
32-pin
5×5mm
TQFN
-40℃~ +85℃ TLSR8266F512
ET32
TLSR8266F512ET32CL Large Tape and
Reel, 3000
TLSR8266F512ET32CT Small Tape and
Reel, 300
TLSR8266F512ET32C Rail, 100
-40℃~+125℃ TLSR8266F512
AT32
TLSR8266F512AT32CL Large Tape and
Reel, 3000
TLSR8266F512AT32CT Small Tape and
Reel, 300
TLSR8266F512AT32C Rail, 100
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 15 Ver2.0.2
1.5 Package
For the TLSR8266, 56-pin QFN 7×7mm, 48-pin QFN 7×7mm and 32-pin QFN 5
×5mm package options are available. For the TLSR8266F512, 48-pin QFN 7×7mm
and 32-pin QFN 5×5mm package options are available. Package dimension for the
TLSR8266ET/AT56, the TLSR8266ET/AT48/TLSR8266F512ET/AT48 and the
TLSR8266ET/AT32/TLSR8266F512ET/AT32 are shown as Figure 1-2, Figure 1-3 and
Figure 1-4, respectively.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 16 Ver2.0.2
Figure 1- 2 Package dimension for the TLSR8266ET/AT56 (Unit: mm)
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DS-TLSR8266/TLSR8266F512-E19 17 Ver2.0.2
Figure 1- 3 Package dimension for the TLSR8266ET/AT48/
TLSR8266F512ET/AT48 (Unit: mm)
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DS-TLSR8266/TLSR8266F512-E19 18 Ver2.0.2
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DS-TLSR8266/TLSR8266F512-E19 19 Ver2.0.2
Figure 1- 4 Package dimension for the TLSR8266ET/AT32/
TLSR8266F512ET/AT32 (Unit: mm)
1.6 Pin layout
Pin assignment for the TLSR8266ET/AT56 is as shown in Figure 1-5:
1
2
3
4
5
6
7
8
9
11
12
13
14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
40
39
38
37
36
35
34
33
32
31
30
29
42
41
15 16 17 18 19 20 21 22 23 24 25 26 27 28
10
SWS/ANA_A
PWM3/ANA_A
MSDI/ANA_A
MCLK/ANA_A
GP18/PWM3_N/ANA_A
PWM4/ANA_A
GP19/PWM4_N/ANA_A
SWM/ANA_A
PWM5/ANA_B
GP20/PWM5_N/ANA_B
MSDO/ANA_B
MSCN/ANA_B
DM/ANA_B
DP/ANA_B
VB
US
VD
DO
3
DV
DD
3
DV
SS
DV
SS
VD
DD
EC
GP
0/P
WM
0_N
/AN
A_B
<7
>
PW
M0/A
NA
_C
<0>
/Am
ic_B
ias
GP
1/P
WM
1_N
/AN
A_C
<1>
/Am
ic_In
PW
M1_N
/AN
A_C
<2>
GP
2/P
WM
1/A
NA
_C
<3>
PW
M2/A
NA
_C
<4>
GP
3/P
WM
2_N
/AN
A_C
<5>
GP
4/u
art_
tx/A
NA
_C
<6>
GP5/uart_rx/ANA_C
GP6/uart_rts/ANA_D
GP7/uart_cts/ANA_D
GP8/PWM3/ANA_D
GP9/PWM4/ANA_D
GP10/ANA_D
GP11/ANA_D
GP12/ANA_D/Rbias_EXT
XC2
AVDD3
XC1
AVDD3
NC
NC
AN
T
AV
DD
3
GP
13/A
NA
_D
<7>
GP
14/A
NA
_E
<0>
RE
SE
TB
DM
IC_C
K/A
NA
_E
<1>
DM
IC_D
I/A
NA
_E
<2>
GP
15/A
NA
_E
<3>
GP
16/S
DM
_P
/AN
A_E
<4>
GP
17/S
DM
_N
/AN
A_E
<5>
CN
/uar
t_rt
s/A
NA
_E
<6>
DI/
I2C
_S
DA
/AN
A_E
<7>
DO
/uar
t_ct
s/A
NA
_F
<0>
CK
/I2C
_S
CL
/AN
A_F
<1>
TLSR8266ET/AT56
Figure 1- 5 Pin assignment for the TLSR8266ET/AT56
Functions of 56pins for the TLSR8266ET/AT56 are described in Table 1-2:
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 20 Ver2.0.2
Table 1- 2 Pin functions for the TLSR8266ET/AT56
QFN56 7X7
No. Pin Name Type Description
1 SWS/ANA_A Digital I/O Single wire slave/GPIO/ANA_A
2 PWM3/ANA_A Digital I/O PWM3 output/GPIO/ ANA_A
3 MSDI/ANA_A Digital I/O Memory SPI data input/GPIO/ANA_A
4 MCLK/ANA_A Digital I/O Memory SPI clock/GPIO/ANA_A
5 GP18/PWM3_N/ANA_A Digital I/O GPIO18/PWM3 inverting output/ANA_A
6 PWM4/ANA_A Digital I/O PWM4 output/GPIO/ANA_A
7 GP19/PWM4_N/ANA_A Digital I/O GPIO19/PWM4 inverting output/ANA_A
8 SWM/ANA_A Digital I/O Single Wire Master/GPIO/ANA_A
9 PWM5/ANA_B Digital I/O PWM5 output/GPIO/ANA_B
10 GP20/PWM5_N/ANA_B Digital I/O GPIO20/PWM5 inverting output/ ANA_B
11 MSDO/ANA_B Digital I/O Memory SPI data output/GPIO/ANA_B
12 MSCN/ANA_B Digital I/O Memory SPI chip-select(Active low)/GPIO/
ANA_B
13 DM/ANA_B Digital I/O USB data Minus/GPIO/ANA_B
14 DP/ANA_B Digital I/O USB data Positive/GPIO/ANA_B
15 VBUS PWR USB 5V supply
16 VDDO3 PWR 5V-to-3V LDO output
17 DVDD3 PWR 3.3V IO supply
18 DVSS GND Digital LDO ground
19 VDDDEC PWR Digital LDO 1.8V output
20 DVSS GND Digital LDO ground
21 GP0/PWM0_N/ANA_B Digital I/O GPIO0/ PWM0 inverting output /ANA_B
22 PWM0/ANA_C/Amic_Bias Digital I/O PWM0 output/GPIO/ANA_C/Analog
microphone Bias
23 GP1/PWM1_N/ANA_C/
Amic_In Digital I/O
GPIO1/PWM1 inverting output/ANA_C/Analog microphone input
24 PWM1_N/ANA_C Digital I/O PWM1 inverting output/GPIO/ANA_C
25 GP2/PWM1/ANA_C Digital I/O GPIO2/PWM1 output/ANA_C
26 PWM2/ANA_C Digital I/O PWM2 output/GPIO/ ANA_C
27 GP3/PWM2_N/ANA_C Digital I/O GPIO3/PWM2 inverting output/ ANA_C
28 GP4/uart_tx/ANA_C Digital I/O GPIO4/UART_TX/ ANA_C
29 GP5/uart_rx/ANA_C Digital I/O GPIO5/UART_RX/ ANA_C
30 GP6/uart_rts/ANA_D Digital I/O GPIO6/UART_RTS / ANA_D
31 GP7/uart_cts/ANA_D Digital I/O GPIO7/UART_CTS / ANA_D
32 GP8/PWM3/ANA_D Digital I/O GPIO8/ PWM3 output/ ANA_D
33 GP9/PWM4/ANA_D Digital I/O GPIO9/ PWM4 output/ ANA_D
34 GP10/ANA_D Digital I/O GPIO10/ ANA_D
35 GP11/ANA_D Digital I/O GPIO11/ ANA_D
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 21 Ver2.0.2
QFN56 7X7
No. Pin Name Type Description
36 GP12/ANA_D/Rbias_EXT Digital I/O GPIO12/ ANA_D/off-chip bias resistor
37 AVDD3 PWR Analog 3.3V supply
38 XC2 Analog O 12MHz/16MHz crystal output
39 XC1 Analog I 12MHz/16MHz crystal input
40 AVDD3 PWR Analog 3.3V supply
41 NC Not connected
42 NC Not connected
43 ANT Analog I/O RF antenna
44 AVDD3 PWR Analog 3.3V supply
45 GP13/ANA_D Digital I/O GPIO13/ ANA_D
46 GP14/ANA_E Digital I/O GPIO14/ ANA_E
47 RESETB RESET Power on reset, active low
48 DMIC_CK/ANA_E Digital I/O DMIC clock/GPIO/ANA_E
49 DMIC_DI/ANA_E Digital I/O DMIC data input/ GPIO/ANA_E
50 GP15/ANA_E Digital I/O GPIO15/ ANA_E
51 GP16/SDM_P/ANA_E Digital I/O GPIO16/ ANA_E
52 GP17/SDM_N/ANA_E Digital I/O GPIO17/ ANA_E
53 CN/uart_rts/ANA_E Digital I/O SPI chip select. Active low/ UART_RTS /GPIO/
ANA_E
54 DI/I2C_SDA/ANA_E Digital I/O SPI data input/I2C_SDA/GPIO/ ANA_E
55 DO/uart_cts/ANA_F Digital I/O SPI data output/ UART_CTS /GPIO/
ANA_F
56 CK/I2C_SCL/ANA_F Digital I/O SPI clock/I2C_SCK/GPIO/ ANA_F
*Note:
1) Pins with bold typeface can be used as GPIOS. All GPIOs have configurable
pull-up/pull-down resistor.
2) Pin drive strength: All pins support drive strength up to 4mA (4mA when “DS”=1,
0.7mA when “DS”=0) with the following exceptions: ANA_B and ANA_B
support high drive strength up to 8mA (8mA when “DS”=1, 4mA when “DS”=0);
ANA_E and ANA_E support high drive strength up to 16mA (16mA when
“DS”=1, 12mA when “DS”=0). “DS” configuration will take effect when the pin is used
as output. Please refer to section 7.1 for corresponding “DS” register address and the
default setting.
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 22 Ver2.0.2
Pin assignment for the TLSR8266ET/AT48 is as shown in Figure 1-6:
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
SWS/ANA_A
PWM3/ANA_A
MSDI/ANA_A
MCLK/ANA_A
PWM4/ANA_A
GP19/PWM4_N/ANA_A
SWM/ANA_A
PWM5/ANA_B
MSDO/ANA_B
DM/ANA_B
DP/ANA_B
DV
DD
3
DV
SS
VD
DD
EC
DV
SS
GP
0/P
WM
0_
N/A
NA
_B
<7
>
PW
M0
/AN
A_
C<
0>
/Am
ic_
Bia
s
GP
1/P
WM
1_
N/A
NA
_C
<1
>/A
mic
_In
PW
M1
_N
/AN
A_
C<
2>
GP
2/P
WM
1/A
NA
_C
<3
>
PW
M2
/AN
A_
C<
4>
GP
3/P
WM
2_
N/A
NA
_C
<5
>
GP
4/u
art_
tx/A
NA
_C
<6
>GP5/uart_rx/ANA_C
XC1
GP7/uart_cts/ANA_D
GP8/PWM3/ANA_D
GP9/PWM4/ANA_D
GP12/ANA_D/Rbias_EXT
AVDD3
XC2
AVDD3
GP6/uart_rts/ANA_D
AN
T
AV
DD
3
GP
13
/AN
A_
D<
7>
RE
SE
TB
DM
IC_
CK
/AN
A_
E<
1>
DM
IC_
DI/
AN
A_
E<
2>
GP
16
/SD
M_
P/A
NA
_E
<4>
GP
17
/SD
M_
N/A
NA
_E
<5
>
CN
/uar
t_rt
s/A
NA
_E
<6
>
DI/
I2C
_S
DA
/AN
A_
E<
7>
DO
/uar
t_ct
s/A
NA
_F
<0
>
CK
/I2
C_
SC
L/A
NA
_F
<1
>
TLSR8266ET/AT48
MSCN/ANA_B
GP10/ANA_D
GP11/ANA_D
Figure 1- 6 Pin assignment for the TLSR8266ET/AT48
Functions of 48 pins for the TLSR8266ET/AT48 are described in Table 1-3:
Table 1- 3 Pin functions for the TLSR8266ET/AT48
QFN48 7X7
No. Pin Name Type Description
1 SWS/ANA_A Digital
I/O Single wire slave/GPIO/ANA_A
2 PWM3/ANA_A Digital
I/O PWM3 output/GPIO/ ANA_A
3 MSDI/ANA_A Digital
I/O Memory SPI data input/GPIO/ANA_A
4 MCLK/ANA_A Digital
I/O Memory SPI clock/GPIO/ANA_A
5 PWM4/ANA_A Digital
I/O PWM4 output/GPIO/ANA_A
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 23 Ver2.0.2
QFN48 7X7
No. Pin Name Type Description
6 GP19/PWM4_N/ANA_A Digital
I/O GPIO19/PWM4 inverting output/ANA_A
7 SWM/ANA_A Digital
I/O Single Wire Master/GPIO/ANA_A
8 PWM5/ANA_B Digital
I/O PWM5 output/GPIO/ANA_B
9 MSDO/ANA_B Digital
I/O Memory SPI data output/GPIO/ANA_B
10 MSCN/ANA_B Digital
I/O Memory SPI chip-select(Active low)/GPIO/
ANA_B
11 DM/ANA_B Digital
I/O USB data Minus/GPIO/ANA_B
12 DP/ANA_B Digital
I/O USB data Positive/GPIO/ANA_B
13 DVDD3 PWR 3.3V IO supply
14 DVSS GND Digital LDO ground
15 VDDDEC PWR Digital LDO 1.8V output
16 DVSS GND Digital LDO ground
17 GP0/PWM0_N/ANA_B Digital
I/O GPIO0/PWM0 inverting output/ANA_B
18 PWM0/ANA_C/Amic_Bias Digital
I/O PWM0 output/GPIO/ANA_C/ Analog
microphone Bias
19 GP1/PWM1_N/ANA_C/
Amic_In
Digital I/O
GPIO1/PWM1 inverting output/ANA_C/Analog microphone input
20 PWM1_N/ANA_C Digital
I/O PWM1 inverting output/GPIO/ANA_C
21 GP2/PWM1/ANA_C Digital
I/O GPIO2/PWM1 output/ANA_C
22 PWM2/ANA_C Digital
I/O PWM2 output/GPIO/ ANA_C
23 GP3/PWM2_N/ANA_C Digital
I/O GPIO3/PWM2 inverting output/ ANA_C
24 GP4/uart_tx/ANA_C Digital
I/O GPIO4/UART_TX/ ANA_C
25 GP5/uart_rx/ANA_C Digital
I/O GPIO5/UART_RX/ ANA_C
26 GP6/uart_rts/ANA_D Digital
I/O GPIO6/UART_RTS / ANA_D
27 GP7/uart_cts/ANA_D Digital
I/O GPIO7/UART_CTS / ANA_D
28 GP8/PWM3/ANA_D Digital
I/O GPIO8/ PWM3 output/ANA_D
29 GP9/PWM4/ANA_D Digital
I/O GPIO9/ PWM4 output/ANA_D
30 GP10/ANA_D GPIO10/ ANA_D
31 GP11/ANA_D GPIO11/ ANA_D
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 24 Ver2.0.2
QFN48 7X7
No. Pin Name Type Description
32 GP12/ANA_D/Rbias_EXT Digital
I/O GPIO12/ ANA_D/off-chip bias resistor
33 AVDD3 PWR Analog 3.3V supply
34 XC2 Analog
O 12MHz/16MHz crystal output
35 XC1 Analog
I 12MHz/16MHz crystal input
36 AVDD3 PWR Analog 3.3V supply
37 ANT Analog
O RF antenna
38 AVDD3 PWR Analog 3.3V supply
39 GP13/ANA_D Digital
I/O GPIO13/ ANA_D
40 RESETB RESET Power on reset, active low
41 DMIC_CK/ANA_E Digital
I/O DMIC clock/GPIO/ANA_E
42 DMIC_DI/ANA_E Digital
I/O DMIC data input/GPIO/ ANA_E
43 GP16/SDM_P/ANA_E Digital
I/O GPIO16/ ANA_E
44 GP17/SDM_N/ANA_E Digital
I/O GPIO17/ ANA_E
45 CN/uart_rts/ANA_E Digital
I/O SPI chip select. Active low/ UART_RTS /GPIO/
ANA_E
46 DI/I2C_SDA/ANA_E Digital
I/O SPI data input/I2C_SDA/GPIO/ ANA_E
47 DO/uart_cts/ANA_F Digital
I/O SPI data output/ UART_CTS /GPIO/ ANA_F
48 CK/I2C_SCL/ANA_F Digital
I/O SPI clock/I2C_SCK/GPIO/ ANA_F
*Note:
1) Pins with bold typeface can be used as GPIOS. All GPIOs have configurable
pull-up/pull-down resistor.
2) Pin drive strength: All pins support drive strength up to 4mA (4mA when “DS”=1,
0.7mA when “DS”=0) with the following exceptions: ANA_B and ANA_B
support high drive strength up to 8mA (8mA when “DS”=1, 4mA when “DS”=0);
ANA_E and ANA_E support high drive strength up to 16mA (16mA when
“DS”=1, 12mA when “DS”=0). “DS” configuration will take effect when the pin is used
as output. Please refer to section 7.1 for corresponding “DS” register address and the
default setting.
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 25 Ver2.0.2
Pin assignment for the TLSR8266ET/AT32 is as shown in Figure 1-7:
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 1110 12 13 14 1615
32 3031 29 28 27 2526
SWS/ANA_A
DV
DD
3
DV
SS
VD
DD
EC
GP5/uart_rx/ANA_C
XC1
XC2
AVDD3
AV
DD
3
RE
SE
TB
TLSR8266ET/AT32
PWM3/ANA_A
MSDI/ANA_A
MCLK/ANA_A
MSDO/ANA_B
MSCN/ANA_B
DM/ANA_B
DP/ANA_B
PW
M0
/AN
A_
C<
0>
/Am
ic_
Bia
s
GP
1/P
WM
1_
N/A
NA
_C
<1>
/Am
ic_
In
PW
M1
_N
/AN
A_
C<
2>
PW
M2
/AN
A_
C<
4>
AVDD3
CN
/uar
t_rt
s/A
NA
_E
<6
>
DI/
I2C
_S
DA
/AN
A_
E<
7>
DO
/uar
t_ct
s/A
NA
_F
<0
>
CK
/I2
C_
SC
L/A
NA
_F
<1
>
GP10/ANA_D
GP11/ANA_D
GP
4/u
art_
tx/A
NA
_C
<6
>
ANT
DM
IC_
CK
/AN
A_
E<
1>
DM
IC_
DI/
AN
A_
E<
2>
Figure 1- 7 Pin assignment for the TLSR8266ET/AT32
Functions of 32 pins for the TLSR8266ET/AT32 are described in Table 1-4:
Table 1- 4 Pin functions for the TLSR8266ET/AT32
QFN32 5X5
No. Pin Name Pin Type Description
1 SWS/ANA_A Digital I/O Single wire slave/GPIO/ANA_A
2 PWM3/ANA_A Digital I/O PWM3 output/GPIO/ ANA_A
3 MSDI/ANA_A Digital I/O Memory SPI data input/GPIO/ANA_A
4 MCLK/ANA_A Digital I/O Memory SPI clock/GPIO/ANA_A
5 MSDO/ANA_B Digital I/O Memory SPI data output/GPIO/ANA_B
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 26 Ver2.0.2
QFN32 5X5
No. Pin Name Pin Type Description
6 MSCN/ANA_B Digital I/O Memory SPI chip-select(Active low)/GPIO/
ANA_B
7 DM/ANA_B Digital I/O USB data Minus/GPIO/ANA_B
8 DP/ANA_B Digital I/O USB data Positive/GPIO/ANA_B
9 DVDD3 PWR 3.3V IO supply
10 DVSS GND Digital LDO ground
11 VDDDEC PWR Digital LDO 1.8V output
12 PWM0/ANA_C/
Amic_Bias Digital I/O
PWM0 output/GPIO/ANA_C/ Analog microphone Bias
13 GP1/PWM1_N/
ANA_C/Amic_In Digital I/O
GPIO1/PWM1 inverting output/ANA_C/Analog microphone input
14 PWM1_N/ANA_C Digital I/O PWM1 inverting output/GPIO/ANA_C
15 PWM2/ANA_C Digital I/O PWM2 output/GPIO/ ANA_C
16 GP4/uart_tx/ANA_C Digital I/O GPIO4/UART_TX/ ANA_C
17 GP5/uart_rx/ANA_C Digital I/O GPIO5/UART_RX/ ANA_C
18 GP10/ANA_D Digital I/O GPIO10/ ANA_D
19 GP11/ANA_D Digital I/O GPIO11/ ANA_D
20 AVDD3 PWR Analog 3.3V supply
21 XC2 Analog O 12MHz/16MHz crystal output
22 XC1 Analog I 12MHz/16MHz crystal input
23 AVDD3 PWR Analog 3.3V supply
24 ANT Analog
I/O RF antenna
25 AVDD3 PWR Analog 3.3V supply
26 RESETB RESET Power on reset, active low
27 DMIC_CK/ANA_E Digital I/O DMIC clock/GPIO/ANA_E
28 DMIC_DI/ANA_E Digital I/O DMIC data input/GPIO/ ANA_E
29 CN/uart_rts/ANA_E Digital I/O SPI chip select. Active low/ UART_RTS /GPIO/
ANA_E
30 DI/I2C_SDA/ANA_E Digital I/O SPI data input/I2C_SDA/GPIO/ ANA_E
31 DO/uart_cts/ANA_F Digital I/O SPI data output/ UART_CTS /GPIO/ ANA_F
32 CK/I2C_SCL/ANA_F Digital I/O SPI clock/I2C_SCK/GPIO/ ANA_F
*Note:
1) Pins with bold typeface can be used as GPIOS. All GPIOs have configurable
pull-up/pull-down resistor.
2) Pin drive strength: All pins support drive strength up to 4mA (4mA when “DS”=1,
0.7mA when “DS”=0) with the following exceptions: ANA_B and ANA_B
support high drive strength up to 8mA (8mA when “DS”=1, 4mA when “DS”=0). “DS”
configuration will take effect when the pin is used as output. Please refer to section
7.1 for corresponding “DS” register address and the default setting.
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 27 Ver2.0.2
Pin assignment for the TLSR8266F512ET/AT48 is as shown in Figure 1-8:
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
SWS/ANA_A
PWM3/ANA_A
3-12
GP18/PWM3_N/ANA_A
PWM4/ANA_A
GP19/PWM4_N/ANA_A
SWM/ANA_A
PWM5/ANA_B
GP20/PWM5_N/ANA_B
DM/ANA_B
DP/ANA_B
12-3
DV
DD
3
DV
SS
VD
DD
EC
DV
SS
GP
0/P
WM
0_
N/A
NA
_B
<7
>
PW
M0
/AN
A_
C<
0>
/Am
ic_B
ias
GP
1/P
WM
1_
N/A
NA
_C
<1
>/A
mic
_In
PW
M1
_N
/AN
A_
C<
2>
GP
2/P
WM
1/A
NA
_C
<3
>
PW
M2
/AN
A_
C<
4>
GP
3/P
WM
2_
N/A
NA
_C
<5
>
GP
4/u
art_
tx/A
NA
_C
<6
>
GP5/uart_rx/ANA_C
XC1
GP7/uart_cts/ANA_D
GP8/PWM3/ANA_D
GP9/PWM4/ANA_D
GP12/ANA_D/Rbias_EXT
AVDD3
XC2
AVDD3
GP6/uart_rts/ANA_DA
NT
AV
DD
3
GP
13
/AN
A_
D<
7>
RE
SE
TB
DM
IC_
CK
/AN
A_
E<
1>
DM
IC_
DI/
AN
A_
E<
2>
GP
16
/SD
M_
P/A
NA
_E
<4
>
GP
17
/SD
M_
N/A
NA
_E
<5
>
CN
/uar
t_rt
s/A
NA
_E
<6
>
DI/
I2C
_S
DA
/AN
A_
E<
7>
DO
/uar
t_ct
s/A
NA
_F
<0
>
CK
/I2
C_
SC
L/A
NA
_F
<1
>
TLSR8266F512ET/AT48GP10/ANA_D
GP11/ANA_D
Figure 1- 8 Pin assignment for the TLSR8266F512ET/AT48
Functions of 48 pins for the TLSR8266F512ET/AT48 are described in Table 1-5:
Table 1- 5 Pin functions for the TLSR8266F512ET/AT48
QFN48 7X7
No. Pin Name Type Description
1 SWS/ANA_A Digital
I/O Single wire slave/GPIO/ANA_A
2 PWM3/ANA_A Digital
I/O PWM3 output/GPIO/ ANA_A
3 3-12 - This pin should be connected to Pin #12
4 GP18/PWM3_N/ANA_A Digital
I/O GPIO18/PWM3 inverting output/ANA_A
Telink for customer
Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 28 Ver2.0.2
QFN48 7X7
No. Pin Name Type Description
5 PWM4/ANA_A Digital
I/O PWM4 output/GPIO/ANA_A
6 GP19/PWM4_N/ANA_A Digital
I/O GPIO19/PWM4 inverting output/ANA_A
7 SWM/ANA_A Digital
I/O Single Wire Master/GPIO/ANA_A
8 PWM5/ANA_B Digital
I/O PWM5 output/GPIO/ANA_B
9 GP20/PWM5_N/ANA_B Digital
I/O GPIO20/PWM5 inverting output/ ANA_B
10 DM/ANA_B Digital
I/O USB data Minus/GPIO/ANA_B
11 DP/ANA_B Digital
I/O USB data Positive/GPIO/ANA_B
12 12-3 - This pin should be connected to Pin #3
13 DVDD3 PWR 3.3V IO supply
14 DVSS GND Digital LDO ground
15 VDDDEC PWR Digital LDO 1.8V output
16 DVSS GND Digital LDO ground
17 GP0/PWM0_N/ANA_B Digital
I/O GPIO0/PWM0 inverting output/ANA_B
18 PWM0/ANA_C/
Amic_Bias
Digital I/O
PWM0 output/GPIO/ANA_C/ Analog microphone Bias
19 GP1/PWM1_N/
ANA_C/Amic_In
Digital I/O
GPIO1/PWM1 inverting output/ANA_C/Analog microphone input
20 PWM1_N/ANA_C Digital
I/O PWM1 inverting output/GPIO/ANA_C
21 GP2/PWM1/ANA_C Digital
I/O GPIO2/PWM1 output/ANA_C
22 PWM2/ANA_C Digital
I/O PWM2 output/GPIO/ ANA_C
23 GP3/PWM2_N/ANA_C Digital
I/O GPIO3/PWM2 inverting output/ ANA_C
24 GP4/uart_tx/ANA_C Digital
I/O GPIO4/UART_TX/ ANA_C
25 GP5/uart_rx/ANA_C Digital
I/O GPIO5/UART_RX/ ANA_C
26 GP6/uart_rts/ANA_D Digital
I/O GPIO6/UART_RTS / ANA_D
27 GP7/uart_cts/ANA_D Digital
I/O GPIO7/UART_CTS / ANA_D
28 GP8/PWM3/ANA_D Digital
I/O GPIO8/ PWM3 output/ANA_D
29 GP9/PWM4/ANA_D Digital
I/O GPIO9/ PWM4 output/ANA_D
30 GP10/ANA_D GPIO10/ ANA_D
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 29 Ver2.0.2
QFN48 7X7
No. Pin Name Type Description
31 GP11/ANA_D GPIO11/ ANA_D
32 GP12/ANA_D/Rbias_EXT Digital
I/O GPIO12/ ANA_D/off-chip bias resistor
33 AVDD3 PWR Analog 3.3V supply
34 XC2 Analog
O 12MHz/16MHz crystal output
35 XC1 Analog
I 12MHz/16MHz crystal input
36 AVDD3 PWR Analog 3.3V supply
37 ANT Analog
O RF antenna
38 AVDD3 PWR Analog 3.3V supply
39 GP13/ANA_D Digital
I/O GPIO13/ ANA_D
40 RESETB RESET Power on reset, active low
41 DMIC_CK/ANA_E Digital
I/O DMIC clock/GPIO/ANA_E
42 DMIC_DI/ANA_E Digital
I/O DMIC data input/GPIO/ ANA_E
43 GP16/SDM_P/ANA_E Digital
I/O GPIO16/ ANA_E
44 GP17/SDM_N/ANA_E Digital
I/O GPIO17/ ANA_E
45 CN/uart_rts/ANA_E Digital
I/O SPI chip select. Active low/ UART_RTS /GPIO/
ANA_E
46 DI/I2C_SDA/ANA_E Digital
I/O SPI data input/I2C_SDA/GPIO/ ANA_E
47 DO/uart_cts/ANA_F Digital
I/O SPI data output/ UART_CTS /GPIO/ ANA_F
48 CK/I2C_SCL/ANA_F Digital
I/O SPI clock/I2C_SCK/GPIO/ ANA_F
*Note:
1) Pins with bold typeface can be used as GPIOS. All GPIOs have configurable
pull-up/pull-down resistor.
2) Pin drive strength: All pins support drive strength up to 4mA (4mA when “DS”=1,
0.7mA when “DS”=0) with the following exceptions: ANA_B and ANA_B
support high drive strength up to 8mA (8mA when “DS”=1, 4mA when “DS”=0);
ANA_E and ANA_E support high drive strength up to 16mA (16mA when
“DS”=1, 12mA when “DS”=0). “DS” configuration will take effect when the pin is used
as output. Please refer to section 7.1 for corresponding “DS” register address and the
default setting.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 30 Ver2.0.2
Pin assignment for the TLSR8266F512ET/AT32 is as shown in Figure 1-9:
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 1110 12 13 14 1615
32 3031 29 28 27 2526
SWS/ANA_AD
VD
D3
DV
SS
VD
DD
EC
GP5/uart_rx/ANA_C
XC1
XC2
AVDD3
AV
DD
3
RE
SE
TB
TLSR8266F512ET/AT32
PWM3/ANA_A
3-8
PWM4/ANA_A
PWM5/ANA_B
DM/ANA_B
DP/ANA_B
PW
M0
/AN
A_
C<
0>
/Am
ic_
Bia
s
GP
1/P
WM
1_
N/A
NA
_C
<1>
/Am
ic_
In
PW
M1
_N
/AN
A_
C<
2>
PW
M2
/AN
A_
C<
4>
AVDD3
CN
/uar
t_rt
s/A
NA
_E
<6
>
DI/
I2C
_S
DA
/AN
A_
E<
7>
DO
/uar
t_ct
s/A
NA
_F
<0
>
CK
/I2
C_
SC
L/A
NA
_F
<1
>
GP10/ANA_D
GP11/ANA_D
GP
4/u
art_
tx/A
NA
_C
<6
>
ANT
GP
16
/SD
M_
P/A
NA
_E
<4>
GP
17
/SD
M_
N/A
NA
_E
<5
>
8-3
Figure 1- 9 Pin assignment for the TLSR8266F512ET/AT32
Functions of 32 pins for the TLSR8266F512ET/AT32 are described in Table 1-6:
Table 1- 6 Pin functions for the TLSR8266F512ET/AT32
QFN32 5X5
No. Pin Name Type Description
1 SWS/ANA_A Digital I/O Single wire slave/GPIO/ANA_A
2 PWM3/ANA_A Digital I/O PWM3 output/GPIO/ ANA_A
3 3-8 - This pin should be connected to Pin #8
4 PWM4/ANA_A Digital I/O PWM4 output/GPIO/ANA_A
5 PWM5/ANA_B Digital I/O PWM5 output/GPIO/ANA_B
6 DM/ANA_B Digital I/O USB data Minus/GPIO/ANA_B
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QFN32 5X5
No. Pin Name Type Description
7 DP/ANA_B Digital I/O USB data Positive/GPIO/ANA_B
8 8-3 - This pin should be connected to Pin #3
9 DVDD3 PWR 3.3V IO supply
10 DVSS GND Digital LDO ground
11 VDDDEC PWR Digital LDO 1.8V output
12 PWM0/ANA_C/Amic_Bias Digital I/O PWM0 output/GPIO/ANA_C/Analog
microphone Bias
13 GP1/PWM1_N/ANA_C/
Amic_In Digital I/O
GPIO1/PWM1 inverting output/ANA_C/Analog microphone input
14 PWM1_N/ANA_C Digital I/O PWM1 inverting output/GPIO/ANA_C
15 PWM2/ANA_C Digital I/O PWM2 output/GPIO/ ANA_C
16 GP4/uart_tx/ANA_C Digital I/O GPIO4/UART_TX/ ANA_C
17 GP5/uart_rx/ANA_C Digital I/O GPIO5/UART_RX/ ANA_C
18 GP10/ANA_D Digital I/O GPIO10/ ANA_D
19 GP11/ANA_D Digital I/O GPIO11/ ANA_D
20 AVDD3 PWR Analog 3.3V supply
21 XC2 Analog O 12MHz/16MHz crystal output
22 XC1 Analog I 12MHz/16MHz crystal input
23 AVDD3 PWR Analog 3.3V supply
24 ANT Analog I/O RF antenna
25 AVDD3 PWR Analog 3.3V supply
26 RESETB RESET Power on reset, active low
27 GP16/SDM_P/ANA_E Digital I/O GPIO16/ ANA_E
28 GP17/SDM_N/ANA_E Digital I/O GPIO17/ ANA_E
29 CN/uart_rts/ANA_E Digital I/O SPI chip select. Active low/ UART_RTS /GPIO/
ANA_E
30 DI/I2C_SDA/ANA_E Digital I/O SPI data input/I2C_SDA/GPIO/ ANA_E
31 DO/uart_cts/ANA_F Digital I/O SPI data output/ UART_CTS /GPIO/
ANA_F
32 CK/I2C_SCL/ANA_F Digital I/O SPI clock/I2C_SCK/GPIO/ ANA_F
*Note:
1) Pins with bold typeface can be used as GPIOS. All GPIOs have configurable
pull-up/pull-down resistor.
2) Pin drive strength: All pins support drive strength up to 4mA (4mA when “DS”=1,
0.7mA when “DS”=0) with the following exceptions: ANA_B and ANA_B
support high drive strength up to 8mA (8mA when “DS”=1, 4mA when “DS”=0);
ANA_E and ANA_E support high drive strength up to 16mA (16mA when
“DS”=1, 12mA when “DS”=0). “DS” configuration will take effect when the pin is used
as output. Please refer to section 7.1 for corresponding “DS” register address and the
default setting.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 32 Ver2.0.2
1.7 Telink SDK
A full featured SDK is provided with the chip for Bluetooth Low Energy
applications. The customers can easily develop rich BLE applications by employing the
firmware, along with the system configuration data composed according to the
specific hardware design.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 33 Ver2.0.2
2 Memory and MCU
2.1 Memory
The TLSR8266/TLSR8266F512 embeds 16KB data memory (SRAM), and
128/256/512KB selectable FLASH.
SRAM/Register memory map is shown as follows:
0x808000
0x80BFFF
0x80C000
16KB SRAM
0x807FFF
0x800000
Register
Figure 2- 1 Physical memory map
Register address: from 0x800000 to 0x807FFF;
16KB SRAM address: from 0x808000 to 0x80C000.
Both register and 16KB SRAM address can be accessed via SPI/I2C, SWS/SWM
interface.
FLASH address mapping is configurable. FLASH address can be accessed via MSPI
interface.
SPI FLASH
SRAM
0x0000
0x800000
0x7FFFFF
IO
Configurable
0xFFFFFF
Figure 2- 2 MCU memory map
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2.2 MCU
The TLSR8266/TLSR8266F512 integrates a powerful 32-bit MCU developed by
Telink. The digital core is based on 32-bit RISC, and the length of instructions is 16 bits;
four hardware breakpoints are supported.
2.3 Working modes
The TLSR8266/TLSR8266F512 has four working modes: Active, Idle, Suspend and
Deep Sleep. This section mainly gives the description of every working mode and
mode transition.
Idle State
Suspend
State
Active State
Deep Sleep
State
Wakeup
Wakeup
Wakeup
Figure 2- 3 Transition chart of working modes
2.3.1 Active mode
In active mode, the MCU block is at working state, and the
TLSR8266/TLSR8266F512 can transmit or receive data via its embedded RF transceiver.
The RF transceiver can also be powered down if no data transfer is needed.
2.3.2 Idle mode
In Idle mode, the MCU block stalls, and the RF transceiver can be at working state
or be powered down. The time needed for the transition from Idle mode to Active
mode is negligible.
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2.3.3 Power-saving mode
For the TLSR8266/TLSR8266F512, there are two kinds of power-saving modes:
suspend mode and deep sleep mode. The two modes have similar transition
sequences but different register settings. For 1.8V digital core, it’s still provided with
the working power by 1.8V LDO in suspend mode; while in deep sleep mode, the 1.8V
LDO will be turned off, and the digital core is powered down.
In suspend mode, the RF transceiver is powered down, and the clock of the MCU
block is stopped. It only takes about 400us for the TLSR8266/TLSR8266F512 to enter
the active mode from suspend mode.
While in deep sleep mode, both the RF transceiver and the MCU block are
powered down with only power management block being active. The transition time
needed from deep sleep mode to active mode is 1ms, almost the same as power-up
time.
2.4 Reset, Wakeup and Power down enabling
Table 2- 1 Register configuration for reset, wakeup and power down enabling
Address Mnemonic Type Description Reset
Value
0x60 RST0 R/W
Reset control, 1 for reset, 0 for clear
[0] : SPI
[1] : I2C
[2]: USB
[3]: rsvd
[4]: MCU
[5]: mac
[6]: AIF
[7]: zb
00
0x61 RST1 R/W
[0] system_timer
[1]algm
[2]dma
[3]rs232
[4]pwm0
[5]aes
[6]bbpll48m
df
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Address Mnemonic Type Description Reset
Value
[7]swires
0x62 RST2 R/W
[0]sbc
[1]audio
[2]dfifo
[3]adc
[4]mcic
[5]soft reset to reset mcic enable
[6]mspi
[7] algs
00
0x6e WAKEUPEN R/W
Wakeup enable
[0]: enable wakeup from I2C host
[1]: enable wakeup from SPI host
[2]: enable wakeup from USB
[3]: enable wakeup from gpio
[4]: enable wakeup from I2C
synchronous interface
System resume control
[5]: enable GPIO remote wakeup
[6]: if set to1, system will issue USB
resume signal on USB bus
[7]: sleep wakeup reset system enable
00
0x6f PWDNEN W
[0]: suspend enable
[5]:rst all (act as power on reset)
[6]:mcu low power mode
[7]: stall mcu trig If bit[0] set 1, then
system will go to suspend. Or only stall
mcu
Except for power on reset, it is also feasible to carry out software reset for the
whole chip or some modules. Setting address 0x6f[5] to 1b’1 is to reset the whole chip.
Addresses 0x60~0x62 serve to reset individual modules: if some bit is set to logic “1”,
the corresponding module is reset. Address 0x6e serves to enable various wakeup
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2.5 Wakeup sources
Wakeup_timer wakeup
Pad wakeup[41:0]
PM_TOP
32K timer
Wakeup_dig
Usb wakeup
Figure 2- 4 Wakeup sources
2.5.1 Wakeup source - USB
This wakeup source can only wake up the system from suspend mode.
First, set the digital core address 0x6e bit [2] to 1.
To activate this mode, 3V_reg38 bit[5] should also be set to 1.
Once USB host sends out resuming signal, the system will be wake up.
2.5.2 Wakeup source – 32K timer
This wakeup source is able to wake up the system from suspend mode or deep
sleep mode.
Address 3V_reg38 bit[6] is the enabling bit for wakeup source from 32k timer.
2.5.3 Wakeup source – pad
This wakeup source is able to wake up the system from suspend mode or deep
sleep mode. And Pad wakeup supports high level or low level wakeup which is
configurable via polarity control registers.
Enabling control registers: Pad PA[7:0] enabling control register is 3V_reg39[7:0],
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Pad PB[7:0] enabling control register is 3V_reg40[7:0], Pad PC[7:0] enabling control
register is 3V_reg41[7:0], Pad PD[7:0] enabling control register is 3V_reg42[7:0], Pad
PE[7:0] enabling control register is 3V_reg43[7:0], Pad PF[1:0] enabling control
register is 3V_reg38[3:2]. Total wakeup pin can be up to 42.
Polarity control registers: Pad PA[7:0] polarity control register is 3V_reg33[7:0],
Pad PB[7:0] polarity control register is 3V_reg34[7:0], Pad PC[7:0] polarity control
register is 3V_reg35[7:0], Pad PD[7:0] polarity control register is 3V_reg36[7:0], Pad
PE[7:0] polarity control register is 3V_reg37[7:0], and Pad PF[1:0] polarity control
register is 3V_reg38[1:0].
Table 2- 2 Analog registers for Wakeup
ADDR Dec ADDR Hex Description Default
r33 0x21 pa_pol 0x00
r34 0x22 pb_pol 0x00
r35 0x23 pc_pol 0x00
r36 0x24 pd_pol 0x00
r37 0x25 pe_pol 0x00
r38[1:0] 0x26[1:0] pf_pol[1:0] 0x00
r38[3:2] 0x26[3:2] wkup_pf_en[1:0] 0x00
r38[5] 0x26[5] wkup dig (usb) 0x00
r38[6] 0x26[6] wkup 32k timer 0x00
r38[7] 0x26[7] rsvd (wkup comparator) 0x00
r39 0x27 wkup_pa_en 0x00
r40 0x28 wkup_pb_en 0x00
r41 0x29 wkup_pc_en 0x00
r42 0x2a wkup_pd_en 0x00
r43 0x2b wkup_pe_en 0x00
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3 2.4G RF Transceiver
3.1 Block diagrams
The TLSR8266/TLSR8266F512 integrates an advanced 2.4GHz RF transceiver. The
RF transceiver works in the worldwide 2.4GHz ISM (Industrial Scientific Medical) band
and contains an integrated balun with a single-ended RF Tx/Rx port pin. No matching
components are needed.
The transceiver consists of a fully integrated frequency synthesizer, a power
amplifier, a modulator and a receiver. The transceiver can be configured to work in
standard-compliant BLE mode and can also be configured to work in proprietary
2Mbps mode. All modes support FSK/GFSK modulations.
LNA
TX Filter
RX Filter
Baseband
Modulator
Baseband
Demodulator
RF Synthesizer
ANT
PA
Figure 3- 1 Block diagram of RF transceiver
The internal PA can deliver a maximum 8dBm output power, avoiding the needs
for an external RF PA.
3.2 Function description
3.2.1 Turn on/off
For the sake of saving power, the transceiver can be turned on/off via the
software. Setting the address 0x7c bit[6] to 1 enables the RF transceiver, while
clearing the bit totally disables the RF transceiver.
3.2.2 Air interface data rate and RF channel frequency
Air interface data rate, the modulated signaling rate for RF transceiver when
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transmitting and receiving data, is configurable via related register setting: 1Mbps,
2Mbps are available for the TLSR8266/TLSR8266F512.
For the TLSR8266/TLSR8266F512, RF transceiver can operate with frequency
ranging from 2.400GHz to 2.4835GHz. The RF channel frequency setting determines
the center of the channel.
3.3 Baseband
The baseband contains dedicated hardware logic to perform fast AGC control,
access code correlation, CRC checking, data whitening, encryption/decryption and
frequency hopping logic.
The baseband supports all features required by Bluetooth v4.0 specification.
3.3.1 Packet format
Packet format is shown as Table 3-1:
Table 3- 1 Packet Format
LSB MSB
Preamble
(1 octet)
Access Address
(4 octets)
PDU
(2 to 39 octets)
CRC
(3 octets)
Packet length 80bit ~ 376bit (80~376us @ 1Mbps).
3.3.2 RSSI
The TLSR8266/TLSR8266F512 provides accurate RSSI (Receiver Signal Strength
Indicator) indication which can be read on per packet basis.
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4 Clock
4.1 Clock sources
The TLSR8266/TLSR8266F512 embeds a 32MHz RC oscillator which can be used
as clock source for system, ADC and DMIC. A 32KHz RC oscillator is also embedded to
provide clock source for sleep state.
Other than the RC clock source, PLL generates a 192MHz clock source and a
48MHz clock source, which can be used as clock sources for system, ADC and DMIC.
External crystal is also available via pin XC1, which provide a 12MHz/16MHz clock
source for system, ADC and DMIC.
4.2 Register table
Table 4- 1 Register table for clock
Address Mnemonic Type Description Reset
Value
0x63 CLKEN0 R/W
Clock enable control: 1 for enable; 0 for
disable
[0] : SPI
[1] : I2C
[2]: USB
[3]: USB PHY
[4]: MCU
[5]: mac
[6]: AIF
[7]: zb
8c
0x64 CLKEN1 R/W
[0]system timer
[1]algm
[2]dma
[3]rs232
[4]pwm0
[5]aes
[6]clk32k for system timer
[7]swires
00
0x65 CLKEN2 R/W
[0]32k for qdec
[1]audio
[2]dfifo
00
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Address Mnemonic Type Description Reset
Value
[3]key scan
[4]mcic
[5]qdec
[6]32k for pwm
[7]32k for keyscan
0x66 CLKSEL R/W
System clock select
[4:0]: system clock divider:
fhs/((CLKSEL[4:0]+1)).
Fhs refer 0x70 FHS_sel
[6:5]
2’b00:32m clock from rc
2’b01:hs divider clk
2’b10:16M clock from pad
2’b11:32k clk from pad
{0x70[0], 0x66[7]}: FHS sel
ff
0x67 I2S step R/W Reserved 33
0x68 I2S Mod R/W Reserved 2
0x69 Adc step[7:0] R/W ADC clock step[7:0] 00
0x6a Adc mod[7:0] R/W Adc clock mod[7:0] 2
0x6b adcmodstep R/W
[7]: adc clock enable
[6:4] :adc step[10:8]
[3:0] adc mod[11:8]
Adc clock = fhs * step[10:0]/mod[11:0]
Mod need be larger than or equal to 2*step
Fhs refer 0x70 FHS_sel
00
0x6c DMIC_step R/W [7]:digital mic clock enable
[6:0] step 1
0x6d DMIC_mod R/W
[7:0] mod
DMIC clock =fhs*DMIC_step[6:0]/DMIC_mod
Mod need be larger than or equal to 2*step
Fhs refer 0x70 FHS_sel
2
0x70 FHS_sel R/W
{0x70[0], 0x66[7]}: fhs select
2’b00: 192M clock from pll
2’b01:48M pll
2’b10:32M clock from osc
2’b11:16M clock from pad
00
0x71 DC/DC clk mod R/W Reserved
0x73 Clk mux sel
[0]: clk32k select;0:sel 32k osc 1: 32k pad [1]dmic clock select, 1:select 32k (refer bit[0] to decide which 32k ; 0:dmic clk div [2] usb phy clock select,1 : 192M divider
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Address Mnemonic Type Description Reset
Value
0:48M pll [7:4] r_lpr_div, decide system clock speed in low power mode
4.3 System clock
Rc 32MRC Oscillator
Pad 12M/16MCrystal Oscillator
Pad 32.768KHzCrystal Oscillator
FHS
divider hs divider clk
{0x70[0], 0x66[7]}
00
10
11
0x66[4:0]
sys_clk
System Clock M
UX
01
0x66[6:5]
/4 48M
192M
RC_32MRC Oscillator
Pad_12M/16MCrystal Oscillator
PLL
FHS MUX
00
10
11
01
Figure 4- 1 Block diagram of system clock
There are four selectable clock sources for MCU system clock: 32MHz RC clock,
HS divider clock (divided from a High speed clock), and Pad clock (12MHz/16MHz,
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32.768KHz).
The high speed clock (FHS) is selectable via address {0x70[0], 0x66[7]} from the
following sources: 192MHz clock from PLL, 48MHz clock from PLL, 32MHz RC clock,
and 12MHz/16MHz Pad clock.
Register CLKSEL (address 0x66) serves to set system clock. System clock source is
selectable via bit[6:5]. If address 0x66[6:5] is set to 2b’01 to select the HS divider clock,
system clock frequency is adjustable via address 0x66[4:0]. FSystem clock = FFHS / (system
clock divider value in address 0x66[4:0] + 1).
4.4 Module clock
Registers CLKEN0~CLKEN2 (address 0x63~0x65) are used to enable or disable
clock for various modules. By disable the clocks of unused modules, current
consumption could be reduced.
4.4.1 ADC clock
ADC clock derives from FHS. ADC clock is enabled via setting address 0x6b[7] to
1b’1.
ADC clock frequency dividing factor contains step and mod. Address 0x6b[6:4]
and 0x69 serve to set ADC clock step[10:0]. Address 0x6b[3:0] and 0x6a serve to set
ADC clock mod[11:0].
ADC clock frequency, FADC clock, equals to FFHS* step[10:0] / mod[11:0].
4.4.2 DMIC clock
Address 0x6c[7] serves to enable DMIC clock.
DMIC clock pin can select 32KHz clock or derive from FHS. Address 0x73 serves to
select DMIC clock source.
In normal DMIC working mode 0x73[1] needs to be set to 1b’0, DMIC clock
divider is selected and frequency dividing factor should be further configured. DMIC
clock frequency dividing factor contains step and mod. Address 0x6c[6:0] serves to set
DMIC clock step[6:0], while address 0x6d serves set DMIC clock mod. In this situation,
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 45 Ver2.0.2
DMIC clock frequency, FDMIC clock, equals to FFHS* step[6:0] / mod[7:0].
When DMIC is not used, and a 32Khz clock is needed, bit[1] of 0x73 is set to 1b’1
to select the 32KHz clock. bit[0] can be configured to select 32KHz RC oscillator or
32.768KHz Pad clock.
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Datasheet for Telink TLSR8266/TLSR8266F512
DS-TLSR8266/TLSR8266F512-E19 46 Ver2.0.2
5 Timers
5.1 Timer0~Timer2
The TLSR8266/TLSR8266F512 supports three timers: Timer0~ Timer2. The three
timers all support four modes: Mode 0 (System Clock Mode), Mode 1 (GPIO Trigger
Mode), Mode 2 (GPIO Pulse Width Mode) and Mode 3 (Tick Mode).
Timer 2 can also be configured as “watchdog” to monitor firmware running.
5.1.1 Register table
Table 5- 1 Register configuration for Timer0~Timer2
Address Mnemonic Type Description Reset
Value
0x620 TMR_CTRL0 RW
[0]Timer0 enable
[2:1] Timer0 mode.
0 using sclk, 1, using gpio,
2 count widht of gpi, 3 tick
[3]Timer1 enable
[5:4] Timer1 mode.
[6]Timer2 enable
[7]Bit of timer2 mode
00
0x621 TMR_CTRL1 RW [0]Bit of timer2 mode
[7:1]Low bits of watch dog capture 00
0x622 TMR_CTRL2 RW
[6:0]High bits of watch dog capture.
It is compared with [31:18] of
timer2 ticker
[7]watch dog capture
00
0x623 TMR_STATUS RW
[0] timer0 status, write 1 to clear
[1] timer1 status, write 1 to clear
[2] timer2 status, write 1 to clear