FN7872 Rev 0.00 Page 1 of 19 June 21, 2011 FN7872 Rev 0.00 June 21, 2011 ISL23345 Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) DATASHEET The ISL23345 is a volatile, low voltage, low noise, low power, 256 tap, quad digitally controlled potentiometer (DCP) with an I 2 C Bus ™ interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I 2 C bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (128 tap position). The low voltage, low power consumption, and small package of the ISL23345 make it an ideal choice for use in battery operated equipment. In addition, the ISL23345 has a V LOGIC pin allowing down to 1.2V bus operation, independent from the V CC value. This allows for low logic levels to be connected directly to the ISL23345 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Applications • Power supply margining • Trimming sensor circuits • Gain adjustment in battery powered instruments • RF power amplifier bias compensation Features • Four potentiometers per package • 256 resistor taps • 10k50kor 100ktotal resistance •I 2 C serial interface - No additional level translator for low bus supply - Three address pins allow up to eight devices per bus • Maximum supply current without serial bus activity (standby) - 5μA @ V CC and V LOGIC = 5V - 2μA @ V CC and V LOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Power supply - V CC = 1.7V to 5.5V analog power supply - V LOGIC = 1.2V to 5.5V I 2 C bus/logic power supply • Wiper resistance: 70typical @ V CC = 3.3V • Power-on preset to mid-scale (128 tap position) • Extended industrial temperature range: -40°C to +125°C • 20 Ld TSSOP or 20 QFN packages • Pb-free (RoHS compliant) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP FIGURE 2. V REF ADJUSTMENT 0 2000 4000 6000 8000 10000 0 64 128 192 256 TAP POSITION (DECIMAL) RESISTANCE (Ω) VREF_M ISL28114 1 DCP of ISL23345 + - VREF RL1 RW1 RH1 NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL23325
Transcript
FN7872Rev 0.00
June 21, 2011
ISL23345Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
DATASHEETNOT RECOMMENDED FOR NEW DESIGNSRECOMMENDED REPLACEMENT PART
ISL23325
The ISL23345 is a volatile, low voltage, low noise, low power, 256 tap, quad digitally controlled potentiometer (DCP) with an I2C Bus™ interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit.
Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (128 tap position).
The low voltage, low power consumption, and small package of the ISL23345 make it an ideal choice for use in battery operated equipment. In addition, the ISL23345 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23345 without passing through a voltage level shifter.
The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Applications• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
Features• Four potentiometers per package
• 256 resistor taps
• 10k 50kor 100k total resistance
• I2C serial interface
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
• Maximum supply current without serial bus activity (standby)
- 5µA @ VCC and VLOGIC = 5V
- 2µA @ VCC and VLOGIC = 1.7V
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally
- Reduces power consumption by disconnecting the DCP resistor from the circuit
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70 typical @ VCC = 3.3V
• Power-on preset to mid-scale (128 tap position)
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 QFN packages
• Pb-free (RoHS compliant)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP
1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23345. For more information on MSL please see techbrief TB363.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact productreliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379.
6. For JC, the “case temp” location is taken at the package top center.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20) TYP (Note 8)MAX
(Note 20) UNITS
RTOTAL RH to RL Resistance W option 10 k
U option 50 k
T option 100 k
RH to RL Resistance Tolerance -20 ±2 +20 %
End-to-End Temperature Coefficient W option 125 ppm/°C
U option 65 ppm/°C
T option 45 ppm/°C
VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0 VCC V
RW Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V
70 200
VCC = 1.7V 580
CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page 9 32/32/32 pF
ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 < 0.1 0.4 µA
Noise Resistor Noise Density Wiper at middle point, W option 16
Wiper at middle point, U option 49
Wiper at middle point, T option 61
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB
PSRR Power Supply Reject Ratio Wiper output change if VCC change ±10%; wiper at middle point
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL(Note 13)
Integral Non-linearity, Guaranteed Monotonic
W option -1.0 ±0.5 +1.0 LSB(Note 9)
U, T option -0.5 ±0.15 +0.5 LSB(Note 9)
DNL(Note 12)
Differential Non-linearity, Guaranteed Monotonic
W option -1 ±0.4 +1 LSB(Note 9)
U, T option -0.4 ±0.1 +0.4 LSB(Note 9)
FSerror(Note 11)
Full-scale Error W option -5 -2 0 LSB(Note 9)
U, T option -2 -0.5 0 LSB(Note 9)
ZSerror(Note 10)
Zero-scale Error W option 0 2 5 LSB(Note 9)
U, T option 0 0.4 2 LSB(Note 9)
Vmatch(Note 22)
DCP to DCP Matching DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals
-2 ±0.5 2 LSB(Note 9)
TCV(Notes 14)
Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C
U option, Wiper Register set to 80 hex 4 ppm/°C
T option, Wiper Register set to 80 hex 2.3 ppm/°C
tLS_Settling Large Signal Wiper Settling Time From code 0 to FF hex, measured from 0 to 1LSB settling of the wiper
300 ns
fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz
Wiper at middle point U option 250 kHz
Wiper at middle point T option 120 kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL(Note 18)
Integral Non-linearity, Guaranteed Monotonic
W option; VCC = 2.7V to 5.5V -2.0 ±1 +2.0 MI(Note 15)
W option; VCC = 1.7V 10.5 MI(Note 15)
U, T option; VCC = 2.7V to 5.5V -1.0 ±0.3 +1.0 MI(Note 15)
U, T option; VCC = 1.7V 2.1 MI(Note 15)
RDNL(Note 17)
Differential Non-linearity, Guaranteed Monotonic
W option; VCC = 2.7V to 5.5V -1 ±0.4 +1 MI(Note 15)
W option; VCC = 1.7V ±0.6 MI(Note 15)
U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI(Note 15)
U, T option; VCC = 1.7V ±0.35 MI(Note 15)
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20) TYP (Note 8)MAX
(Note 20) UNITS
FN7872 Rev 0.00 Page 5 of 19June 21, 2011
ISL23345
Roffset(Note 16)
Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 0 3 5.5 MI(Note 15)
W option; VCC = 1.7V 6.3 MI(Note 15)
U, T option; VCC = 2.7V to 5.5V 0 0.5 2 MI(Note 15)
U, T option; VCC = 1.7V 1.1 MI(Note 15)
Rmatch(Note 23)
DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages
-2 2 LSB(Note 9)
TCR(Note 19)
Resistance Temperature Coefficient W option; Wiper register set between 32 hex and FF hex
170 ppm/°C
U option; Wiper register set between 32 hex and FF hex
80 ppm/°C
T option; Wiper register set between 32 hex and FF hex
50 ppm/°C
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20) TYP (Note 8)MAX
(Note 20) UNITS
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20) TYP (Note 8)MAX
(Note 20) UNITS
ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V, fSCL = 400 kHz (for I2C active read and write)
200 µA
VLOGIC = 1.2V, VCC = 1.7V,fSCL = 400 kHz (for I2C active read and write)
ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V, I2C interface in standby
2 µA
VLOGIC = 1.2V, VCC = 1.7V,I2C interface in standby
0.5 µA
ICC SB VCC Standby Current VLOGIC = VCC = 5.5V,I2C interface in standby
3 µA
VLOGIC = 1.2V, VCC = 1.7V,I2C interface in standby
1.5 µA
ILOGIC SHDN
VLOGIC Shutdown Current VLOGIC = VCC = 5.5V,I2C interface in standby
2 µA
VLOGIC = 1.2V, VCC = 1.7V,I2C interface in standby
0.5 µA
ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V,I2C interface in standby
3 µA
VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby
1.5 µA
ILkgDig Leakage Current, at Pins A0, A1, A2, SDA, SCL
Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA
FN7872 Rev 0.00 Page 6 of 19June 21, 2011
ISL23345
tDCP Wiper Response Time SCL rising edge of the acknowledge bit after data byte to wiper new position (Changes from 10% to 90% FS)W, U, T options specified top to bottom
0.4 µs
1.5 µs
3.5 µs
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit after ACR data byte to wiper recalled position and RH connection
1.5 µs
VCC, VLOGIC Ramp
(Note 21)
VCC ,VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20) TYP (Note 8)MAX
(Note 20) UNITS
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted.
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20)TYP
(Note 8)MAX
(Note 20) UNITS
VIL Input LOW Voltage -0.3 0.3 x VLOGIC V
VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis
VLOGIC > 2V 0.05 x VLOGIC V
VLOGIC < 2V 0.1 x VLOGIC V
VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V
IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V
Cpin SDA, SCL Pin Capacitance 10 pF
fSCL SCL Frequency 400 kHz
tsp Pulse Width Suppression Time at SDA and SCL Inputs
Any pulse narrower than the max spec is suppressed
50 ns
tAA SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window
900 ns
tBUF Time the Bus Must be Free Before the Start of a New Transmission
SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition
1300 ns
tLOW Clock LOW Time Measured at the 30% of VLOGIC crossing 1300 ns
tHIGH Clock HIGH Time Measured at the 70% of VLOGIC crossing 600 ns
tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC
600 ns
tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC
600 ns
tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC
100 ns
tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window
0 ns
tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC
600 ns
tHD:STO STOP Condition Hold Time for Read or Write
From SDA rising edge to SCL falling edge; both crossing 70% of VLOGIC
1300 ns
FN7872 Rev 0.00 Page 7 of 19June 21, 2011
ISL23345
tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V
0 ns
tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns
tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
tSU:A A1, A0, A2 Setup Time Before START condition 600 ns
tHD:A A1, A0, A2 Hold Time After STOP condition 600 ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255
14. for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
19. for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 3 and y = 0 to 3.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255, x = 0 to 3 and y = 0 to 3.
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted. (Continued)
SYMBOL PARAMETER TEST CONDITIONSMIN
(Note 20)TYP
(Note 8)MAX
(Note 20) UNITS
TCV
Max V RW i Min V RW i –
V RWi +25°C ------------------------------------------------------------------------------ 106
+165°C---------------------=
TCRMax Ri Min Ri –
Ri +25°C ------------------------------------------------------- 10
6
+165°C---------------------=
FN7872 Rev 0.00 Page 8 of 19June 21, 2011
ISL23345
DCP Macro Model
Timing DiagramsSDA vs SCL Timing
A0, A1 and A2 Pin Timing
32pF
RH
RTOTAL
CH
32pF
CW
CL
32pF
RW
RL
tSU:STO
tDH
tHIGH
tSU:STAtHD:STA
tHD:DAT
tSU:DATSCL
SDA(INPUT TIMING)
SDA(OUTPUT TIMING)
tF tLOW
tBUFtAA
tRtsp
tHD:A
SCL
SDA
A0, A1, A2
tSU:A
CLK 1
START STOP
FN7872 Rev 0.00 Page 9 of 19June 21, 2011
ISL23345
Typical Performance Curves
FIGURE 3. 10k DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50k DNL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 5. 10k INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50k INL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 3.3V, +25°C
-0.4
-0.2
0.0
0.2
0.4
0 64 128 192 256
DN
L (
LS
B)
TAP POSITION (DECIMAL)
-0.12
-0.06
0.00
0.06
0.12
0 64 128 192 256
DN
L (
LS
B)
TAP POSITION (DECIMAL)
-0.4
-0.2
0.0
0.2
0.4
0 64 128 192 256
INL
(L
SB
)
TAP POSITION (DECIMAL)
-0.12
-0.06
0.00
0.06
0.12
0 64 128 192 256
INL
(L
SB
)
TAP POSITION (DECIMAL)
-0.4
-0.2
0.0
0.2
0.4
0 64 128 192 256
RD
NL
(M
I)
TAP POSITION (DECIMAL)
-0.10
-0.05
0.00
0.05
0.10
0 64 128 192 256
RD
NL
(M
I)
TAP POSITION (DECIMAL)
FN7872 Rev 0.00 Page 10 of 19June 21, 2011
ISL23345
FIGURE 9. 10k RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50k RINL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
FIGURE 13. 10k TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50k TCv vs TAP POSITION, VCC = 3.3V
Typical Performance Curves (Continued)
-0.8
-0.4
0.0
0.4
0.8
0 64 128 192 256
RIN
L (
MI)
TAP POSITION (DECIMAL)
-0.50
-0.25
0.00
0.25
0.50
0 64 128 192 256
RIN
L (
MI)
TAP POSITION (DECIMAL)
0
20
40
60
80
100
0 64 128 192 256
+125°C
-40°C
+25°C
WIP
ER
RE
SIS
TA
NC
E (
Ω)
TAP POSITION (DECIMAL)
0
20
40
60
80
100
120
0 64 128 192 256
+125°CW
IPE
R R
ES
IST
AN
CE
(Ω
)
TAP POSITION (DECIMAL)
+25°C
-40°C
0
100
200
300
400
15 63 111 159 207 255
TC
v (
pp
m/°
C)
TAP POSITION (DECIMAL)
0
20
40
60
80
15 63 111 159 207 255
TC
v (p
pm
/°C
)
TAP POSITION (DECIMAL)
FN7872 Rev 0.00 Page 11 of 19June 21, 2011
ISL23345
FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION, VCC = 3.3V
FIGURE 17. 100k TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100k TCr vs TAP POSITION, VCC = 3.3V
FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH
Typical Performance Curves (Continued)
0
200
400
600
800
15 63 111 159 207 255
TC
r (p
pm
/°C
)
TAP POSITION (DECIMAL)
0
50
100
150
200
15 63 111 159 207 255
TC
r (p
pm
/°C
)
TAP POSITION (DECIMAL)
0
10
20
30
40
15 63 111 159 207 255
TC
v (
pp
m/°
C)
TAP POSITION (DECIMAL)
0
30
60
90
120
15 63 111 159 207 255
TC
r (p
pm
/°C
)
TAP POSITION (DECIMAL)
CH1: 1V/DIV, 1µs/DIVCH2: 10mV/DIV, 1µs/DIV
SCL CLOCK
RW PIN
WIPER
CH1: 20mV/DIV, 2µs/DIVCH2: 2V/DIV, 2µs/DIV
SCL 9TH CLK OF THE
DATA BYTE (ACK)
FN7872 Rev 0.00 Page 12 of 19June 21, 2011
ISL23345
Functional Pin DescriptionsPotentiometers Pins
RHI AND RLI
The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals of the ISL23345 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register.
VCCPower terminal for the potentiometer section analog power source. Can be any value needed to support the voltage range of the DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open drain input/output.
SERIAL CLOCK (SCL)This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output.
DEVICE ADDRESS (A2, A1, A0)The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
SCL 9TH CLOCK OF THEDATA BYTE (ACK)
1V/DIV0.2µs/DIV
WIPER
SCL
0.5V/DIV20µs/DIV
VCC
WIPER
0.5V/DIV, 0.2µs/DIV-3dB FREQUENCY = 1.437MHz AT MIDDLE TAP
CH1: RH TERMINALCH2: RW TERMINAL
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-40 -15 10 35 60 85 110
VCC = 1.7V, VLOGIC = 1.2V
VCC = 5.5V, VLOGIC = 5.5V
ST
AN
DB
Y C
UR
RE
NT
IC
C (
µA
)
TEMPERATURE (°C)
FN7872 Rev 0.00 Page 13 of 19June 21, 2011
ISL23345
pins in order to initiate communication with the ISL23345. A maximum of eight ISL23345 devices may occupy the I2C serial bus (see Table 3).
VLOGICDigital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source.
Principles of OperationThe ISL23345 is an integrated circuit incorporating four DCPs with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions.
Voltage at any of the DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation.
The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the I2C logic source, which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than the DCP analog supply.
DCP DescriptionEach DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RW) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically.
While the ISL23345 is being powered up, all the wipers (WRi) are reset to 80h (128 decimal), which positions RWi at the center between RLi and RHi.
The WRi can be read or written to directly using the I2C serial interface as described in the following sections.
Memory DescriptionThe ISL23345 contains five volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register WR3 and Access Control Register (ACR). The memory map of
ISL23345 is shown in Table 1. The Wiper Register WRi at address i contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is connected to RL through a 2k serial resistor, as shown in Figure 25. The default value of the SHDN bit is 1.
When the device enters shutdown, all current DCP WRi settings are maintained. When the device exits shutdown, the wipers will return to the previous WRi settings after a short settling time (see Figure 26).
In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the wipers will be RESET to their mid positions. This is done to avoid an undefined state at the wiper outputs.
TABLE 1. MEMORY MAP
ADDRESS(hex)
VOLATILEREGISTER NAME
DEFAULT SETTING(hex)
10 ACR 40
3 WR3 80
2 WR2 80
1 WR1 80
0 WR0 80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7 6 5 4 3 2 1 0
NAME/VALUE
0 SHDN 0 0 0 0 0 0
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
2kΩ
RW
RL
RH
FN7872 Rev 0.00 Page 14 of 19June 21, 2011
ISL23345
I2C Serial InterfaceThe ISL23345 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23345 operates as a slave device in all applications.
All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol ConventionsData states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23345, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23345 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device.
All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode.
An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28).
The ISL23345 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23345 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs, and the following three bits are matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
POWER-UP
USER PROGRAMMED
MID SCALE = 80H
SHDN ACTIVATED SHDN RELEASED
AFTER SHDN
WIP
ER
VO
LTA
GE
, V
RW
(V
)
SHDN MODE
TIME (s)
WIPER RESTORE TO THE ORIGINAL POSITION
0
1 0 1 0 A2 A1 A0 R/W
(MSB) (LSB)
LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY
SDA
SCL
START DATA DATA STOPSTABLE CHANGE
DATASTABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
FN7872 Rev 0.00 Page 15 of 19June 21, 2011
ISL23345
Write OperationA Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23345 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels via a single Write operation. The command is initiated by sending an additional Data Byte after the first Data byte instead of sending a STOP condition.
Read OperationA Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23345 responds with an ACK; then the ISL23345 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30).
SDA OUTPUT FROMTRANSMITTER
SDA OUTPUT FROMRECEIVER
81 9
START ACK
SCL FROMMASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
STOP
IDENTIFICATIONBYTE
ADDRESSBYTE
DATABYTE
ACK
SIGNALS FROMTHE MASTER
SIGNALS FROMTHE SLAVE
ACK
1 010 0
ACK
WRITE
SIGNAL AT SDA 0 0 0A0A1
FIGURE 29. BYTE WRITE SEQUENCE
A2
SIGNALSFROM THE
MASTER
SIGNALS FROMTHE SLAVE
SIGNAL AT SDA
START
IDENTIFICATION BYTE WITH
R/W = 0ADDRESS
BYTE
ACK
ACK
1 010 0
STOP
ACK
1
IDENTIFICATION BYTE WITH
R/W = 1
ACK
START
LAST READ DATA BYTE
FIRST READ DATA BYTE
ACK
0 0 0A0A1 A0A1
FIGURE 30. READ SEQUENCE
ACK
A2 A21 0 1 0
READ
FN7872 Rev 0.00 Page 16 of 19June 21, 2011
ISL23345
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Applications InformationVLOGIC RequirementsVLOGIC should be powered continuously during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23345. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible.
VCC Requirements and PlacementIt is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin.
Wiper TransitionWhen stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to FFh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
Revision HistoryThe revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
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