12

34

PowerFLAT™ 5x6

AM15540v2

5678

1 2 3 4

Top View

D(5, 6, 7, 8)

G(4)

S(1, 2, 3)

FeaturesOrder code VDS RDS(on) max. ID

STL117N4LF7AG 40 V 3.5 mΩ 119 A

• AEC-Q101 qualified • Among the lowest RDS(on) on the market• Excellent FoM (figure of merit)• Low Crss/Ciss ratio for EMI immunity• High avalanche ruggedness• Wettable flank package

Applications• Switching applications

DescriptionThis N-channel Power MOSFET utilizes STripFET™ F7 technology with anenhanced trench gate structure that results in very low on-state resistance, while alsoreducing internal capacitance and gate charge for faster and more efficient switching.

Maturity status link

STL117N4LF7AG

Device summary

Order code STL117N4LF7AG

Marking 117N4LF7

Package PowerFLAT™ 5x6

Packing Tape and reel

Automotive-grade N-channel 40 V, 2.5 mΩ typ., 119 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package

STL117N4LF7AG

Datasheet

DS11591 - Rev 6 - June 2018For further information contact your local STMicroelectronics sales office.

www.st.com

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage 40 V

VGS Gate-source voltage ±20 V

ID Drain current (continuous) at TC = 25 °C 119 A

ID Drain current (continuous) at Tc = 100 °C 84 A

IDM (1) Drain current (pulsed) 476 A

PTOT Total dissipation at TC = 25 °C 94 W

Tj Operating junction temperature range-55 to 175 °C

Tstg Storage temperature range

1. Pulse width limited by safe operating area

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 1.6 °C/W

Rthj-pcb (1) Thermal resistance junction-pcb 32 °C/W

1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.

STL117N4LF7AGElectrical ratings

DS11591 - Rev 6 page 2/17

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Table 3. On/Off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSSDrain-source breakdownvoltage ID = 1 mA, VGS = 0 V 40 V

IDSSZero gate voltage

drain currentVGS = 0 V, VDS = 40 V 10 µA

IGSSGate-body leakage

currentVGS = ±20 V, VDS = 0 V 100 nA

VGS(th) Gate threshold voltage VDS = VGS , ID = 250 μA 1.5 2.5 V

RDS(on)Static drain-source

on-resistance

VGS = 10 V, ID= 13 A 2.5 3.5mΩ

VGS = 4.5 V, ID= 13 A 3.4 5

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitanceVDS = 25 V, f = 1 MHz,

VGS = 0 V

- 1780 - pF

Coss Output capacitance - 517 - pF

Crss Reverse transfer capacitance - 58 - pF

Qg Total gate charge VDD = 20 V, ID = 26 A,

VGS = 0 to 10 V

(see Figure 14. Test circuit forgate charge behavior)

- 27.6 - nC

Qgs Gate-source charge - 5.8 - nC

Qgd Gate-drain charge - 5.7 - nC

Table 5. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 32 V, ID = 13 A,

RG = 4.7 Ω, VGS = 10 V (seeFigure 13. Test circuit forresistive load switching timesand Figure 18. Switching timewaveform)

- 12 - ns

tr Rise time - 11 - ns

td(off) Turn-off delay time - 48.3 - ns

tf Fall time - 18 - ns

Table 6. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current 119 A

ISDM (1) Source-drain current (pulsed) 476 A

VSD (2) Source-Drain voltage ISD = 26 A, VGS = 0 V - 1.3 V

STL117N4LF7AGElectrical characteristics

DS11591 - Rev 6 page 3/17

Symbol Parameter Test conditions Min. Typ. Max. Unit

trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs

VDD = 32 V (see Figure15. Test circuit for inductiveload switching and dioderecovery times)

- 38 ns

Qrr Reverse recovery charge - 36 nC

IRRM Reverse recovery current - 1.9 A

1. Pulse width limited by safe operating area.2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

STL117N4LF7AGElectrical characteristics

DS11591 - Rev 6 page 4/17

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area

GIPD141220160951SOA

10 2

10 1

10 0

10 -1

10 -1 10 0 10 1

ID (A)

VDS (V)

Operation in this area is limited by max. RDS(on)

Tj = 175 °C Tc = 25 °C

single pulse

tp = 10µs

tp = 100µs

tp = 1ms

tp = 10ms

Figure 3. Normalized thermal impedance

GIPD141220160952ZTH

10 -1

10 -2

10 -5 10 -4 10 -3 10 -2

K

tp (s)

0.05

Figure 4. Output characteristics

GIPD141220160953OCH

140

120

100

80

60

40

20

00 1 2 3 4 5 6

ID (A)

VDS (V)

VGS = 5 to 10V

VGS = 3V

VGS = 4V

Figure 5. Transfer characteristics

GIPG250120181158TCH

280

240

200

160

120

80

40

01.5 2 2.5 3 3.5 4

ID (A)

VGS (V)

VDS = 5 V

Tj = 25 °C

Tj = -40 °CTj = 150 °C

STL117N4LF7AGElectrical characteristics (curves)

DS11591 - Rev 6 page 5/17

Figure 6. Static drain-source on-resistance

GIPG290620170943RID

5

4

3

2

1

04 8 12 16 20 24

RDS(on) (mΩ)

ID (A)

VGS = 4.5 V

VGS = 10 V

Figure 7. Normalized V(BR)DSS vs. temperature

GIPD141220161054BDV

1.08

1.04

1

0.96

0.92

0.88-75 -25 25 75 125 175

V(BR)DSS (norm.)

Tj (°C)

ID =1mA

Figure 8. Capacitance variations

GIPD141220161056CVR

10 3

10 2

10 1 0 10 20 30 40

C (pF)

VDS (V)

CISS

COSS

CRSS

f=1MHz

Figure 9. Gate charge vs gate-source voltage

GIPG290620170945QVG

10

8

6

4

2

00 5 10 15 20 25 30

VGS (V)

Qg (nC)

VDS = 20 VID = 26 A

Figure 10. Normalized VGS(th) vs. temperature

GIPG290620171000VTH

1.1

1.0

0.9

0.8

0.7

0.6

0.5-75 -25 25 75 125 175

VGS(th) (norm.)

Tj (°C)

ID = 250 µA

Figure 11. Normalized RDS(on) vs. temperature

GIPD141220161057RON

2

1.5

1

0.5

0-75 -25 25 75 125 175

RDS(on) (norm.)

Tj (°C)

VGS =10VID =13A

STL117N4LF7AGElectrical characteristics (curves)

DS11591 - Rev 6 page 6/17

Figure 12. Source-drain diode characteristics

GIPD141220161102SDF

0.9

0.8

0.7

0.6

0.5

0.44 8 12 16 20 24

VSD (V)

ISD (A)

Tj =-55°C

Tj =25°C

Tj =175°C

STL117N4LF7AGElectrical characteristics (curves)

DS11591 - Rev 6 page 7/17

3 Test circuits

Figure 13. Test circuit for resistive load switching times

AM01468v1

VD

RG

RL

D.U.T.

2200μF VDD

3.3μF+

pulse width

VGS

Figure 14. Test circuit for gate charge behavior

AM01469v1

47 kΩ1 kΩ

47 kΩ

2.7 kΩ

1 kΩ

12 V

IG= CONST100 Ω

100 nF

D.U.T.

+pulse width

VGS

2200μF

VG

VDD

Figure 15. Test circuit for inductive load switching anddiode recovery times

AM01470v1

AD

D.U.T.S

B

G

25 Ω

A A

B B

RG

GD

S

100 µH

µF3.3 1000

µF VDD

D.U.T.

+

_

+

fastdiode

Figure 16. Unclamped inductive load test circuit

AM01471v1

VD

ID

D.U.T.

L

VDD+

pulse width

Vi

3.3µF

2200µF

Figure 17. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDDVDD

VD

IDM

ID

Figure 18. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STL117N4LF7AGTest circuits

DS11591 - Rev 6 page 8/17

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitionsand product status are available at: www.st.com. ECOPACK® is an ST trademark.

STL117N4LF7AGPackage information

DS11591 - Rev 6 page 9/17

4.1 PowerFLAT™ 5x6 WF type C package information

Figure 19. PowerFLAT™ 5x6 WF type C package outline

8231817_WF_typeC_r16

STL117N4LF7AGPowerFLAT™ 5x6 WF type C package information

DS11591 - Rev 6 page 10/17

Table 7. PowerFLAT™ 5x6 WF type C mechanical data

Dim.mm

Min. Typ. Max.

A 0.80 1.00

A1 0.02 0.05

A2 0.25

b 0.30 0.50

C 5.80 6.00 6.10

D 5.00 5.20 5.40

D2 4.15 4.45

D3 4.05 4.20 4.35

D4 4.80 5.00 5.10

D5 0.25 0.40 0.55

D6 0.15 0.30 0.45

e 1.27

E 6.20 6.40 6.60

E2 3.50 3.70

E3 2.35 2.55

E4 0.40 0.60

E5 0.08 0.28

E6 0.20 0.325 0.45

E7 0.85 1.00 1.15

E9 4.00 4.20 4.40

E10 3.55 3.70 3.85

K 1.05 1.35

L 0.90 1.00 1.10

L1 0.175 0.275 0.375

θ 0° 12°

STL117N4LF7AGPowerFLAT™ 5x6 WF type C package information

DS11591 - Rev 6 page 11/17

Figure 20. PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)

8231817_FOOTPRINT_rev16

STL117N4LF7AGPowerFLAT™ 5x6 WF type C package information

DS11591 - Rev 6 page 12/17

4.2 PowerFLAT 5x6 WF packing information

Figure 21. PowerFLAT™ 5x6 WF tape (dimensions are in mm)

1.50 0.0+0.1

Do4.0 0.1(II)Po

1.75 0.1E1

1.50 MIND1

2.0 0.05(I)P2

Y

YR0.30MAX

0.30 0.05T

SECTION Y-Y

Measured from centreline of sprocket holeto centreline of pocket.Cumulative tolerance of 10 sprocketholes is ± 0.20 .Measured from centreline of sprockethole to centreline of pocket.

(I)

(II)

(III)

Base and bulk qua ntity 3000 pcs

P1(8.00±0.1) Ao(6.70±0.1)

F(5.

50±0

.0.0

5)(II

I)

W(1

2.00

±0.1

)

Bo (5

.35±

0.05

)

Ko (1.20±0.1)

8234350_TapeWF_rev_C

Figure 22. PowerFLAT™ 5x6 package orientation in carrier tape

Pin 1 identification

STL117N4LF7AGPowerFLAT™ 5x6 WF packing information

DS11591 - Rev 6 page 13/17

Figure 23. PowerFLAT™ 5x6 reel (dimensions are in mm)

2.20

Ø21.2

∅13.00

CORE DETAIL

2.501.90

R0.60

77

128

ØA

R1.10

∅2.50

∅4.00

R25.00

PART NO.

W1

W2 18.4 (max)

W3

06 PS

ESD LOGO

ATTE

NTIO

NOB

SERV

E PR

ECAU

TION

SFO

R HA

NDLIN

G EL

ECTR

OSTA

TIC

SENS

ITIV

E DE

VICE

S

11.9/15.4

12.4 (+2/-0)

A330 (+0/-4.0)

All dimensions are in millimeters

ØN 178(±2.0)

8234350_Reel_rev_C

STL117N4LF7AGPowerFLAT™ 5x6 WF packing information

DS11591 - Rev 6 page 14/17

Revision history

Table 8. Document revision history

Date Revision Changes

06-Apr-2016 1 First release.

13-Sep-2016 2 Updated Table 4: "On/Off states".

29-Jun-2017 3

Modified Table 4: "On/Off states", Table 5: "Dynamic", Table 6: "Switching times" and Table 7:"Source-drain diode".

Added Section 2.1: "Electrical characteristics (curves)".

Minor text changes.

27-Jul-2017 4Updated title and features in cover page.

Document status updated from preliminary to production data.

02-Feb-2018 5

Removed maturity status indication from cover page.

Modified Figure 6. Transfer characteristics.

Minor text changes.

05-Jun-2018 6 Updated Table 6. Source-drain diode.

STL117N4LF7AG

DS11591 - Rev 6 page 15/17

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.1 PowerFLAT™ 5x6 WF type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 PowerFLAT 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

STL117N4LF7AGContents

DS11591 - Rev 6 page 16/17

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

STL117N4LF7AG

DS11591 - Rev 6 page 17/17