REV. B

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aAD712

CONNECTION DIAGRAMSTO-99

(H) Package

OUTPUT

INVERTINGOUTPUT

NONINVERTINGOUTPUT

OUTPUT

INVERTINGINPUT

NONINVERTINGINPUT

VS

+VS AMPLIFIER NO. 2AMPLIFIER NO. 1

AD712

Plastic Mini-DIP (N) PackageSOIC (R) Package and Cerdip (Q) Package

8

7

6

5

1

2

3

4

OUTPUT

INVERTINGOUTPUT

NONINVERTINGOUTPUT

V+

OUTPUT

INVERTINGINPUTNONINVERTINGINPUTV AD712

AMPLIFIER NO. 2AMPLIFIER NO. 1

FEATURESEnhanced Replacements for LF412 and TL082

AC PERFORMANCESettles to 60.01% in 1.0 ms16 V/ms min Slew Rate (AD712J)3 MHz min Unity Gain Bandwidth (AD712J)

DC PERFORMANCE0.30 mV max Offset Voltage: (AD712C)5 mV/8C max Drift: (AD712C)200 V/mV min Open-Loop Gain (AD712K)4 mV p-p max Noise, 0.1 Hz to 10 Hz (AD712C)Surface Mount Available in Tape and Reel in Accor-

dance with EIA-481A Standard

MIL-STD-883B Parts AvailableSingle Version Available: AD711Quad Version: AD713Available in Plastic Mini-DIP, Plastic SOIC, HermeticCerdip, Hermetic Metal Can Packages and Chip Form

Dual Precision, Low Cost,High Speed, BiFET Op Amp

PRODUCT DESCRIPTIONThe AD712 is a high speed, precision monolithic operationalamplifier offering high performance at very modest prices. Itsvery low offset voltage and offset voltage drift are the results ofadvanced laser wafer trimming technology. These performancebenefits allow the user to easily upgrade existing designs that useolder precision BiFETs and, in many cases, bipolar op amps.

The superior ac and dc performance of this op amp makes itsuitable for active filter applications. With a slew rate of 16 V/sand a settling time of 1 s to 0.01%, the AD712 is ideal as abuffer for 12-bit D/A and A/D Converters and as a high-speedintegrator. The settling time is unmatched by any similar ICamplifier.

The combination of excellent noise performance and low inputcurrent also make the AD712 useful for photo diode preamps.Common-mode rejection of 88 dB and open loop gain of400 V/mV ensure 12-bit performance even in high-speed unitygain buffer circuits.

The AD712 is pinned out in a standard op amp configurationand is available in seven performance grades. The AD712J andAD712K are rated over the commercial temperature range of0C to +70C. The AD712A, AD712B and AD712C are ratedover the industrial temperature range of 40C to +85C. TheAD712S and AD712T are rated over the military temperaturerange of 55C to +125C and are available processed to MIL-STD-883-B, Rev. C.

Extended reliability PLUS screening is available, specified overthe commercial and industrial temperature ranges. PLUS

screening includes 168-hour burn-in, as well as other environ-mental and physical tests.

The AD712 is available in an 8-lead plastic mini-DIP, SOIC,cerdip, TO-99 metal can, or in chip form.

PRODUCT HIGHLIGHTS1. The AD712 offers excellent overall performance at very

competitive prices.

2. Analog Devices advanced processing technology and with100% testing guarantees a low input offset voltage (0.3 mVmax, C grade, 3 mV max, J grade). Input offset voltage isspecified in the warmed-up condition. Analog Devices laserwafer drift trimming process reduces input offset voltagedrifts to 5 V/C max on the AD712C.

3. Along with precision dc performance, the AD712 offersexcellent dynamic response. It settles to 0.01% in 1 s andhas a minimum slew rate of 16 V/s. Thus this device is idealfor applications such as DAC and ADC buffers which re-quire a combination of superior ac and dc performance.

4. The AD712 has a guaranteed and tested maximum voltagenoise of 4 V p-p, 0.1 Hz to 10 Hz (AD712C).

5. Analog Devices well-matched, ion-implanted JFETs ensurea guaranteed input bias current (at either input) of 50 pAmax (AD712C) and an input offset current of 10 pA max(AD712C). Both input bias current and input offset currentare guaranteed in the warmed-up condition.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 Analog Devices, Inc., 1998

AD712J/A/S AD712K/B/T AD712CParameter Min Typ Max Min Typ Max Min Typ Max Units

INPUT OFFSET VOLTAGE1

Initial Offset 0.3 3/1/1 0.2 1.0/0.7/0.7 0.1 0.3 mVTMIN to TMAX 4/2/2 2.0/1.5/1.5 0.6 mVvs. Temp 7 20/20/20 7 10 3 5 V/Cvs. Supply 76 95 80 100 86 110 dB

TMIN to TMAX 76/76/76 80 86 dBLong-Term Offset Stability 15 15 15 V/Month

INPUT BIAS CURRENT2

VCM = 0 V 25 75 20 75 20 50 pAVCM = 0 V @ TMAX 0.6/1.6/26 1.7/4.8/77 0.5/1.3/20 1.7/4.8/77 1.3 3.2 nAVCM = 10 V 100 100 75 pA

INPUT OFFSET CURRENTVCM = 0 V 10 25 5 25 5 10 pAVCM = 0 V @ TMAX 0.3/0.7/11 0.6/1.6/26 0.1/0.3/5 0.6/1.6/26 0.3 0.7 nA

MATCHING CHARACTERISTICSInput Offset Voltage 3/1/1 1.0/0.7/0.7 0.3 mV

TMIN to TMAX 4/2/2 2.0/1.5/1.5 0.6 mVInput Offset Voltage Drift 20/20/20 10 5 V/CInput Bias Current 25 25 10 pACrosstalk @ f = 1 kHz 120 120 120 dB @ f = 100 kHz 90 90 90 dB

FREQUENCY RESPONSESmall Signal Bandwidth 3.0 4.0 3.4 4.0 3.4 4.0 MHzFull Power Response 200 200 200 kHzSlew Rate 16 20 18 20 18 20 V/sSettling Time to 0.01% 1.0 1.2 1.0 1.2 1.0 1.2 sTotal Harmonic Distortion 0.0003 0.0003 0.0003 %

INPUT IMPEDANCEDifferential 3 1012i5.5 3 1012i5.5 3 1012i5.5 ipFCommon Mode 3 1012i5.5 3 1012i5.5 3 1012i5.5 ipF

INPUT VOLTAGE RANGEDifferential3 20 20 20 VCommon-Mode Voltage4 +14.5, 11.5 +14.5, 11.5 +14.5, 11.5

TMIN to TMAX VS + 4 +VS 2 VS + 4 +VS 2 VS + 4 +VS 2 VCommon-ModeRejection Ratio

VCM = 10 V 76 88 80 88 86 94 dBTMIN to TMAX 76/76/76 84 80 84 86 90 dB

VCM = 11 V 70 84 76 84 76 90 dBTMIN to TMAX 70/70/70 80 74 80 74 84 dB

INPUT VOLTAGE NOISE 2 2 2 V p-p45 45 45 nV/Hz22 22 22 nV/Hz18 18 18 nV/Hz16 16 16 nV/Hz

INPUT CURRENT NOISE 0.01 0.01 0.01 pA/HzOPEN-LOOP GAIN 150 400 200 400 200 400 V/mV

100/100/100 100 100 V/mV

OUTPUT CHARACTERISTICSVoltage +13, 12.5 +13.9, 13.3 +13, 12.5 +13.9, 13.3 +13, 12.5 +13.9, 13.3 V

12/12/612 +13.8, 13.1 612 +13.8, 13.1 612 +13.8, 13.1 VCurrent 25 25 25 mA

POWER SUPPLYRated Performance 15 15 15 VOperating Range 64.5 618 64.5 618 64.5 618 VQuiescent Current 5.0 6.8 5.0 6.0 5.0 5.6 mA

NOTES1Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25C.2Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25C. For higher temperatures, the current doubles every 10C.3Defined as voltage between inputs, such that neither exceeds 10 V from ground.4Typically exceeding 14.1 V negative common-mode voltage on either input results in an output phase reversal.

Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and maxspecifications are guaranteed, although only those shown in boldface are tested on all production units.

Specifications subject to change without notice.

AD712SPECIFICATIONS

REV. B2

(VS = 615 V @ TA = +258C unless otherwise noted)

AD712

REV. B 3

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VInternal Power Dissipation2

Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VOutput Short Circuit Duration . . . . . . . . . . . . . . . . . IndefiniteDifferential Input Voltage . . . . . . . . . . . . . . . . . . +VS and VSStorage Temperature Range (Q, H) . . . . . . . 65C to +150CStorage Temperature Range (N, R) . . . . . . . . 65C to +125COperating Temperature Range

AD712J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70CAD712A/B/C . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85CAD712S/T . . . . . . . . . . . . . . . . . . . . . . . . . 55C to +125C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

2Thermal Characteristics:8-Lead Plastic Package: JA = 165C/Watt8-Lead Cerdip Package: JC = 22C/Watt; JA = 110C/Watt8-Lead Metal Can Package: JC = 65C/Watt; JA = 150C/Watt8-Lead SOIC Package: JA = 100C

3For supply voltages less than 18 V, the absolute maximum input voltage is equalto the supply voltage.

ORDERING GUIDE

Temperature Package PackageModel Range Description Option

AD712ACHIPS 40C to +85C Bare DieAD712AH 40C to +85C 8-Lead Metal Can H-08AAD712AQ 40C to +85C 8-Lead Ceramic DIP Q-8AD712BH 40C to +85C 8-Lead Metal Can H-08AAD712BQ 40C to +85C 8-Lead Ceramic DIP Q-8AD712CH 40C to +85C 8-Lead Metal Can H-08AAD712CN 40C to +85C 8-Lead Plastic DIP N-8AD712JN 0C to +70C 8-Lead Plastic DIP N-8AD712JR 0C to +70C 8-Lead Plastic SOIC R-8AD712JR-REEL 0C to +70C 8-Lead Plastic SOIC R-8AD712JR-REEL7 0C to +70C 8-Lead Plastic SOIC R-8AD712KN 0C to +70C 8-Lead Plastic DIP N-8AD712KR 0C to +70C 8-Lead Plastic SOIC R-8AD712KR-REEL 0C to +70C 8-Lead Plastic SOIC R-8AD712KR-REEL7 0C to +70C 8-Lead Plastic SOIC R-8AD712SCHIPS 55C to +125C Bare DieAD712SQ 55C to +125C 8-Lead Ceramic DIP Q-8AD712SQ/883B 55C to +125C 8-Lead Ceramic DIP Q-8AD712TQ 55C to +125C 8-Lead Ceramic DIP Q-8AD712TQ/883B 55C to +125C 8-Lead Ceramic DIP Q-8

METALIZATION PHOTOGRAPHDimensions shown in inches and (mm).Contact factory for latest dimensions.

AD712

REV. B4

SUPPLY VOLTAGE 6 Volts

INPU

T VO

LTAG

E SW

ING

V

olts

20

15

00 5 2010 15

10

5

RL = 2kV258C

Figure 1. Input Voltage Swing vs.Supply Voltage

SUPPLY VOLTAGE 6 Volts

QUIE

SCEN

T CU

RREN

T

mA

6

5

20 5 2010 15

4

3

Figure 4. Quiescent Current vs.Supply Voltage

COMMON MODE VOLTAGE Volts

INPU

T BI

AS C

URRE

NT

pA

100

75

05 100 5

50

25

VS = +15V258C

10

MAX J GRADE LIMIT

Figure 7. Input Bias Current vs.Common Mode Voltage

Typical Performance Characteristics

SUPPLY VOLTAGE 6 VoltsO

UTPU

T VO

LTAG

E SW

ING

V

olts

20

15

00 5 2010 15

10

5

RL = 2kV258C

+VOUT

VOUT

Figure 2. Output Voltage Swing vs.Supply Voltage

TEMPERATURE 8C

INPU

T BI

AS C

URRE

NT (V

CM =

0)

Amp

s

101260 0 14040 40 20 12040 60 80 100

1011

1010

109

108

107

106

Figure 5. Input Bias Current vs.Temperature

AMBIENT TEMPERATURE 8C

SHO

RT C

IRCU

IT C

URRE

NT L

IMIT

m

A

1060

+ OUTPUT CURRENT

OUTPUT CURRENT

40 20 0 20 40 60 80 100 120 140

12

14

16

18

20

22

24

26

Figure 8. Short Circuit CurrentLimit vs. Temperature

LOAD RESISTANCE V

OUT

PUT

VOLT

AGE

SWIN

G

Vol

ts p

p

30

25

010 100 10k1k

15

10

5

20

615V SUPPLIES

Figure 3. Output Voltage Swingvs. Load Resistance

FREQUENCY Hz

OUT

PUT

IMPE

DANC

E

V

0.011k

1.0

0.1

10

100

10k 100k 1M 10M

Figure 6. Output Impedance vs.Frequency

TEMPERATURE 8C

UNIT

Y G

AIN

BAND

WID

TH

MHz

3.060 40 20 0 20 40 60 80 100 120 140

3.5

4.0

4.5

5.0

Figure 9. Unity Gain Bandwidth vs.Temperature

AD712

REV. B 5

FREQUENCY Hz

OPE

N LO

OP

GAI

N

dB

20100 1k 1M10 10k 100k 10M

0

20

40

60

80

100

GAINPHASE2kV100pFLOAD

20

0

20

40

60

80

100

PHA

SE M

ARG

IN

8C

Figure 10. Open-Loop Gain andPhase Margin vs. Frequency

FREQUENCY Hz

CMR

dB

010

100

80

60

40

20

100 1k 10k 100k 1M

VS = 615VVCM = 1Vp-p258C

Figure 13. Common Mode Rejec-tion vs. Frequency

FREQUENCY Hz

THD

d

B

70

100 10k1k

80

90

100

110

120

130100k

3V RMSRL = 2kVCL = 100pF

Figure 16. Total Harmonic Distor-tion vs. Frequency

SUPPLY VOLTAGE 6 Volts

OPE

N LO

OP

GAI

N

dB

125

0 5 2010 15

RL = 2kV258C

120

115

110

105

100

95

Figure 11. Open-Loop Gain vs.Supply Voltage

INPUT FREQUENCY Hz

OUT

PUT

VOLT

AGE

Vo

lts p

p

30

25

0100k 10M1M

15

10

5

20RL = 2kV258CVS = 615V

Figure 14. Large Signal FrequencyResponse

FREQUENCY Hz

INPU

T NO

ISE

VOLT

AGE

nV

/ H

z

1k1

10

100

10k 100k100101

1k

Figure 17. Input Noise VoltageSpectral Density

SUPPLY MODULATION FREQUENCY Hz

POW

ER S

UPPL

Y RE

JECT

ION

dB

110

010

100

80

60

40

20

100 1k 10k 100k 1M

SUPPLY

+ SUPPLY

VS = 615V SUPPLIESWITH 1V p-p SINEWAVE 258C

Figure 12. Power Supply Rejectionvs. Frequency

SETTLING TIME msO

UTPU

T SW

ING

FRO

M 0

V TO

6VO

LTS

8

0.5

6

4

2

0

4

6

8

10

2

100.6 0.7 0.8 0.9 1.0

0.01%0.1%1%

0.01%0.1%1%ERROR

Figure 15. Output Swing and Errorvs. Settling Time

INPUT ERROR SIGNAL mV(AT SUMMING JUNCTION)

SLEW

RAT

E

V/m

s

5

100

10

15

20

25

200 300 400 500 600 700 800 90000

Figure 18. Slew Rate vs. InputError Signal

AD712

REV. B6

TEMPERATURE 8C60 40 20 0 20 40 60 80 100 120 140

25

15

SLEW

RAT

E

V/m

s

20

Figure 19. Slew Rate vs. Temperature

+VS

OUTPUT

VS

100pF2kV

0.1mF

INPUT

0.1mF

1/2AD712

Figure 20. T.H.D. Test Circuit

1/2AD712

CROSSTALK = 20 LOG

1/2AD712

VOUT

VOUT10VIN

20kV 2.2kV+VS

20V p-p

5kV 5kVVIN

VS

12

34

5

67

8

Figure 21. Crosstalk Test Circuit

10090

100%

1ms5V

Figure 22b. Unity Gain FollowerPulse Response (Large Signal)

10090

100%

1ms5V

Figure 23b. Unity Gain Inverter PulseResponse (Large Signal)

100

100%

100ns

90

50mV

Figure 22c. Unity Gain FollowerPulse Response (Small Signal)

100

100%

200ns

90

50mV

Figure 23c. Unity Gain InverterPulse Response (Small Signal)

+VS

VS

RL2kV

0.1mF

0.1mF

1/2AD712 CL

100pFVIN

VOUT

SQUAREWAVEINPUT

Figure 22a. Unity Gain Follower

+VS

VS

RL2kV

0.1mF

0.1mF

1/2AD712 CL

100pF

VINVOUT

SQUAREWAVEINPUT

5kV

5kV

Figure 23a. Unity Gain Inverter

AD712

REV. B 7

OPTIMIZING SETTLING TIMEMost bipolar high-speed D/A converters have current outputs;therefore, for most applications, an external op amp is requiredfor current-to-voltage conversion. The settling time of the con-verter/op amp combination depends on the settling time of theDAC and output amplifier. A good approximation is:

tS Total = (tS DAC )

2 + (tS AMP )2

The settling time of an op amp DAC buffer will vary with thenoise gain of the circuit, the DAC output capacitance, and withthe amount of external compensation capacitance across theDAC output scaling resistor.

Settling time for a bipolar DAC is typically 100 ns to 500 ns.Previously, conventional op amps have required much longersettling times than have typical state-of-the-art DACs; therefore,the amplifier settling time has been the major limitation to ahigh-speed voltage-output D-to-A function. The introduction ofthe AD711/AD712 family of op amps with their 1 s (to 0.01%of final value) settling time now permits the full high-speedcapabilities of most modern DACs to be realized.

In addition to a significant improvement in settling time, thelow offset voltage, low offset voltage drift, and high open-loopgain of the AD711/AD712 family assures 12-bit accuracy overthe full operating temperature range.

The excellent high-speed performance of the AD712 is shown inthe oscilloscope photos of Figure 25. Measurements were takenusing a low input capacitance amplifier connected directly to thesumming junction of the AD712 both photos show the worstcase situation: a full-scale input transition. The DACs 4 k[10 k||8 k = 4.4 k] output impedance together with a10 k feedback resistor produce an op amp noise gain of 3.25.The current output from the DAC produces a 10 V step at theop amp output (0 to 10 V Figure 25a, 10 V to 0 V Figure25b.)

Therefore, with an ideal op amp, settling to 1/2 LSB (0.01%)requires that 375 V or less appears at the summing junction.This means that the error between the input and output (thatvoltage which appears at the AD712 summing junction) must beless than 375 V. As shown in Figure 25, the total settling timefor the AD712/AD565 combination is 1.2 microseconds.

+15V0.1mF

0.1mF

1/2AD712

10pF

OUTPUT10V TO +10V

AD565A

DAC

15V

IOUT = 4 3IREF 3 CODE

IREF

BIPOLAROFFSET ADJUST

IO

0.1mF

R1100V

R2100VGAIN

ADJUST

REFIN

REFGND 20kV

VEE0.1mF

POWERGND MSB LSB

8kV

5kV

5kV10V

19.95kV 0.5mADACOUT

10VSPAN

20VSPAN

VCCREFOUT

BIPOLAROFF

9.95kV

+

Figure 24. 10 V Voltage Output Bipolar DAC

Figure 25. Settling Characteristics for AD712 with AD565A

100

100%

500ns

90

0V

10V

OUTPUT

5V1mV

SUMMINGJUNCTION

a. (Full-Scale Negative Transition)

100

100%

500ns

90

0V

10V

SUMMINGJUNCTION

OUTPUT

5V1mV

b. (Full-Scale Positive Transition)

AD712

REV. B8

OP AMP SETTLING TIME -A MATHEMATICAL MODELThe design of the AD712 gives careful attention to optimizingindividual circuit components; in addition, a careful trade-offwas made: the gain bandwidth product (4 MHz) and slew rate(20 V/s) were chosen to be high enough to provide very fastsettling time but not too high to cause a significant reduction inphase margin (and therefore stability). Thus designed, theAD712 settles to 0.01%, with a 10 V output step, in under1 s, while retaining the ability to drive a 250 pF load capaci-tance when operating as a unity gain follower.

If an op amp is modeled as an ideal integrator with a unity gaincrossover frequency of /2pi, Equation 1 will accurately de-scribe the small signal behavior of the circuit of Figure 26a,consisting of an op amp connected as an I-to-V converter at theoutput of a bipolar or CMOS DAC. This equation would com-pletely describe the output of the system if not for the op ampsfinite slew rate and other nonlinear effects.

Equation 1.

VOIIN

=R

R(Cf = CX )

s2 +GN

+ RC f

s +1

where

2pi

=op amps unity gain frequency

GN = noise gain of circuit

1+ RRO

This equation may then be solved for Cf:

Equation 2.

Cf =

2 GNR

+2 RCX + (1 GN )

RIn these equations, capacitor CX is the total capacitor appearingthe inverting terminal of the op amp. When modeling a DACbuffer application, the Norton equivalent circuit of Figure 26acan be used directly; capacitance CX is the total capacitance ofthe output of the DAC plus the input capacitance of the op amp(since the two are in parallel).

1/2AD712 VOUT

RL CLCF

R

IO RO CX

Figure 26a. Simplified Model of the AD712 Used as aCurrent-Out DAC Buffer

When RO and IO are replaced with their Thevenin VIN and RINequivalents, the general purpose inverting amplifier of Figure26b is created. Note that when using this general model, capaci-tance CX is EITHER the input capacitance of the op amp if asimple inverting op amp is being simulated OR it is the com-bined capacitance of the DAC output and the op amp input ifthe DAC buffer is being modeled.

1/2AD712 VOUT

RL CLCF

R

VIN

RIN

CX

Figure 26b. Simplified Model of the AD712Used as an Inverter

In either case, the capacitance CX causes the system to go froma one-pole to a two-pole response; this additional pole increasessettling time by introducing peaking or ringing in the op ampoutput. Since the value of CX can be estimated with reasonableaccuracy, Equation 2 can be used to choose a small capacitor,CF, to cancel the input pole and optimize amplifier response.Figure 27 is a graphical solution of Equation 2 for the AD712with R = 4 k.

CF

C X

40

30

0100

20

10

GN = 3.0

GN = 2.0

GN = 1.5

GN = 1.0

20 30 40 50 60

50

60

GN = 4.0

Figure 27. Value of Capacitor CF vs. Value of CX

AD712

REV. B 9

The photos of Figures 28a and 28b show the dynamic responseof the AD712 in the settling test circuit of Figure 29.

100

100%

500ns

90

5mV

5V

Figure 28a. Settling Characteristics 0 V to +10 V StepUpper Trace: Output of AD712 Under Test (5 V/Div)Lower Trace: Amplified Error Voltage (0.01%/Div)

100

100%

500ns

90

5mV

5V

Figure 28b. Settling Characteristics 0 V to 10 V StepUpper Trace: Output of AD712 Under Test (5 V/Div)Lower Trace: Amplified Error Voltage (0.01%/Div)

The input of the settling time fixture is driven by a flat-top pulsegenerator. The error signal output from the false summing nodeof A1 is clamped, amplified by A2 and then clamped again. Theerror signal is thus clamped twice: once to prevent overloadingamplifier A2 and then a second time to avoid overloading theoscilloscope preamp. The Tektronix oscilloscope preamp type7A26 was carefully chosen because it does not overload withthese input levels. Amplifier A2 needs to be a very high speedFET-input op amp; it provides a gain of 10, amplifying the errorsignal output of A1.

GUARDINGThe low input bias current (15 pA) and low noise characteristicsof the AD712 BiFET op amp make it suitable for electrometerapplications such as photo diode preamplifiers and picoamperecurrent-to-voltage converters. The use of a guarding techniquesuch as that shown in Figure 30, in printed circuit board layoutand construction is critical to minimize leakage currents. Theguard ring is connected to a low impedance potential at thesame level as the inputs. High impedance signal lines should notbe extended for any unnecessary length on the printed circuitboard.

1

2

3

4

5

6

7

8

8

7

6

54

32

1

TO-99 (H) PACKAGE PLASTIC MINI-DIP (N) PACKAGECERDIP (Q) PACKAGE

AND SOIC (R) PACKAGE

Figure 30. Board Layout for Guarding Inputs

+15V

0.1mF

1/2AD712

10pF

15V

5kV

4.99kV0.47mF

1/2AD712

0.47mF

200V

4.99kV

5-18pF

0.1mF

10kV

10kVVIN

VERROR 3 5

HP2835

HP283520pF1MV

10kV

0.2-0.6pF

1.1kV

5pF TEKTRONIX 7A26OSCILLOSCOPEPREAMPINPUT SECTION

DATADYNAMICS

5109

(OR EQUIVALENTFLAT TOPPULSEGENERATION)

205V

15V +15V

VOUT

Figure 29. Settling Time Test Circuit

AD712

REV. B10

D/A CONVERTER APPLICATIONSThe AD712 is an excellent output amplifier for CMOS DACs.It can be used to perform both 2 quadrant and 4 quadrant op-eration. The output impedance of a DAC using an invertedR-2R ladder approaches R for codes containing many 1s, 3R forcodes containing a single 1, and for codes containing all zero,the output impedance is infinite.

For example, the output resistance of the AD7545 will modu-late between 11 k and 33 k. Therefore, with the DACsinternal feedback resistance of 11 k, the noise gain will varyfrom 2 to 4/3. This changing noise gain modulates the effect ofthe input offset voltage of the amplifier, resulting in nonlinearDAC amplifier performance.

The AD712K with guaranteed 700 V offset voltage minimizesthis effect to achieve 12-bit performance.

Figures 31 and 32 show the AD712 and AD7545 (12-bitCMOS DAC) configured for unipolar binary (2-quadrant multi-plication) or bipolar (4-quadrant multiplication) operation.Capacitor C1 provides phase compensation to reduce overshootand ringing.

+15V

1/2AD712

GAINADJUST

VIN VREF

VDD RFBOUT1

AGNDAD7545

DGND

R2*

*FOR VALUES OF R1 AND R2 SEE TABLE I

DATA INPUTANALOGCOMMON

C133pF 0.1mF

VDD

R1* 1/2AD712 VOUT

0.1mF

15V

R310kV 1%

R520kV 1%

R420kV 1%

12

DB11DB0

Figure 32. Bipolar Operation

+15V

1/2AD712

GAINADJUST

VIN VREF

VDD RFBOUT1

AGNDAD7545

DGND

VOUTA

R2A*

*REFER TOTABLE I

DB11DB0

ANALOGCOMMON

C1A33pF 0.1mF

VDD

R1A*

1/2AD712

GAINADJUST

VIN VREF

VDD RFBOUT1

AGNDAD7545

DGND

VOUTB

R2B*

*REFER TOTABLE I

DB11DB0

ANALOGCOMMON

C1B33pF

0.1mF

15V

R1B*

VDD

Figure 31. Unipolar Binary Operation

R1 and R2 calibrate the zero offset and gain error of the DAC.Specific values for these resistors depend upon the grade ofAD7545 and are shown below.

Table I. Recommended Trim Resistor Values vs. Gradesof the AD7545 for VDD = +5 V

TrimResistor JN/AQ/SD KN/BQ/TD LN/UD GLN/GUD

R1 500 200 100 20 R2 150 68 33 6.8

AD712

REV. B 11

Figures 33a and 33b show the settling time characteristics of theAD712 when used as a DAC output buffer for the AD7545.

100

100%

500ns

90

a. Full-Scale Positive Transition

100

100%

500ns

90

b. Full-Scale Negative Transition

Figure 33. Settling Characteristics for AD712 with AD7545

NOISE CHARACTERISTICSThe random nature of noise, particularly in the 1/f region,makes it difficult to specify in practical terms. At the same time,designers of precision instrumentation require certain guaran-teed maximum noise levels to realize the full accuracy of theirequipment.

The AD712C grade is specified at a maximum level of 4.0 Vp-p, in a 0.1 Hz to 10 Hz bandwidth. Each AD712C receives a100% noise test for two 10-second intervals; devices with anyexcursion in excess of 4.0 V are rejected. The screened lot isthen submitted to Quality Control for verification on an AQLbasis.

All other grades of the AD712 are sample-tested on an AQLbasis to a limit of 6 V p-p, 0.1 Hz to 10 Hz.

DRIVING THE ANALOG INPUT OF AN A/D CONVERTERAn op amp driving the analog input of an A/D converter, suchas that shown in Figure 34, must be capable of maintaining aconstant output voltage under dynamically changing load condi-tions. In successive-approximation converters, the input currentis compared to a series of switched trial currents. The compari-son point is diode clamped but may deviate several hundredmillivolts resulting in high frequency modulation of A/D inputcurrent. The output impedance of a feedback amplifier is madeartificially low by the loop gain. At high frequencies, where theloop gain is low, the amplifier output impedance can approachits open loop value. Most IC amplifiers exhibit a minimum openloop output impedance of 25 due to current limiting resistors.

+15V

1/2AD712

0.1mF

0.1mF

15V

610VANALOG

INPUT

GAINADJUST

ANALOG COM

R2100V

OFFSETADJUST

AD574

12/8

R1100V

CS

AO

R/CCE

REF IN

REF OUT

BIP OFF

10VIN

ANACOM

20VIN

STS

HIGHBITS

+5V

DIGCOM

+15V

15V

MIDDLEBITS

LOWBITS

Figure 34. AD712 as ADC Unity Gain Buffer

A few hundred microamps reflected from the change in converterloading can introduce errors in instantaneous input voltage. Ifthe A/D conversion speed is not excessive and the bandwidth ofthe amplifier is sufficient, the amplifiers output will return tothe nominal value before the converter makes its comparison.However, many amplifiers have relatively narrow bandwidthyielding slow recovery from output transients. The AD712 isideally suited to drive high speed A/D converters since it offersboth wide bandwidth and high open-loop gain.

AD712

REV. B12

100

100%

90

200ns500mV

PD711 BUFF

10V ADC IN

a. Source Current = 2 mA

100

100%

200ns

90

500mV

PD711 BUFF

5V ADC IN

b. Sink Current = 1 mA

Figure 35. ADC Input Unity Gain Buffer Recovery Times

DRIVING A LARGE CAPACITIVE LOADThe circuit in Figure 36 employs a 100 isolation resistorwhich enables the amplifier to drive capacitive loads exceeding1500 pF; the resistor effectively isolates the high frequencyfeedback from the load and stabilizes the circuit. Low frequencyfeedback is returned to the amplifier summing junction via thelow pass filter formed by the 100 series resistor and the loadcapacitance, CL. Figure 37 shows a typical transient responsefor this connection.

1/2AD712

0.1mF

0.1mF

VIN

+VIN

INPUT

TYPICAL CAPACITANCELIMIT FOR VARIOUSLOAD RESISTORS

R1 C1 UP TO2kV 1500pF10kV 1500pF20V 1000pF

C1 R1

4.99kV

4.99kV

30pF

OUTPUT100V

+

+

Figure 36. Circuit for Driving a Large Capacitive Load

10090

100%

1ms5V

Figure 37. Transient Response RL = 2 k, CL = 500 pF

ACTIVE FILTER APPLICATIONSIn active filter applications using op amps, the dc accuracy ofthe amplifier is critical to optimal filter performance. Theamplifiers offset voltage and bias current contribute to outputerror. Offset voltage will be passed by the filter and may beamplified to produce excessive output offset. For low frequencyapplications requiring large value input resistors, bias currentsflowing through these resistors will also generate an offset voltage.

In addition, at higher frequencies, an op amps dynamics mustbe carefully considered. Here, slew rate, bandwidth, andopen-loop gain play a major role in op amp selection. The slewrate must be fast as well as symmetrical to minimize distortion.The amplifiers bandwidth in conjunction with the filters gainwill dictate the frequency response of the filter.

The use of a high performance amplifier such as the AD712 willminimize both dc and ac errors in all active filter applications.

AD712

REV. B 13

SECOND ORDER LOW PASS FILTERFigure 38 depicts the AD712 configured as a second orderButterworth low pass filter. With the values as shown, the cornerfrequency will be 20 kHz; however, the wide bandwidth of theAD712 permits a corner frequency as high as several hundredkilohertz. Equations for component selection are shown below.

R1 = R2 = user selected (typical values: 10 k 100 k)

C1 (in farads ) = 1.414(2pi)( f cutoff )(R1)

C2 = 0.707(2pi)( f cutoff )(R1)

+15V

1/2AD712

0.1mF

0.1mF

15V

VOUTC2280pF

R220kV

R120kV

C1560pF

VIN

Figure 38. Second Order Low Pass Filter

An important property of filters is their out-of-band rejection.The simple 20 kHz low pass filter shown in Figure 38, might beused to condition a signal contaminated with clock pulses orsampling glitches which have considerable energy content athigh frequencies.

The low output impedance and high bandwidth of the AD712minimize high frequency feedthrough as shown in Figure 39.

The upper trace is that of another low-cost BiFET op ampshowing 17 dB more feedthrough at 5 MHz.

REF 20.0 dBm10 dB/DIV RANGE 15.0 dBm

OFFSET .0 Hz0 dB

CENTER 5 000 000.0 HzRBW 30 kHz

SPAN 10 000 000.0 HzST .8 SECVBW 30 kHz

AD712

TYPICAL BIFET

Figure 39.

AD712

REV. B14

+15V

0.001mF

100kV

0.1mF

0.1mF

A2AD711

15V

+15V0.1mF

0.1mF

A1AD711

15V*

D

*

C

*

B

*

A

2800V 6190V 6490V 6190V 2800VVIN

0.001mF 124kV

4.99kV

4.99kV

VOUT4.9395E15 5.9276E15 5.9276E15 4.9395E15

*SEE TEXT

Figure 40. 9-Pole Chebychev Filter

9-POLE CHEBYCHEV FILTERFigure 40 shows the AD712 and its dual counterpart, theAD711, as a 9-pole Chebychev filter using active frequencydependent negative resistors (FDNR). With a cutoff frequencyof 50 kHz and better than 90 dB rejection, it may be used as anantialiasing filter for a 12-bit Data Acquisition System with100 kHz throughput.

As shown in Figure 40, the filter is comprised of four FDNRs(A, B, C, D) having values of 4.9395 3 1015 and 5.9276 31015 farad-seconds. Each FDNR active network provides atwo-pole response; for a total of 8 poles. The 9th pole consistsof a 0.001 F capacitor and a 124 k resistor at Pin 3 of ampli-fier A2. Figure 41 depicts the circuits for each FDNR with theproper selection of R. To achieve optimal performance, the0.001 F capacitors must be selected for 1% or better matchingand all resistors should have 1% or better tolerance.

+15V

0.001mF

4.99kV

0.1mF

0.1mF

1/2AD712

15V

1.0kV

R: 24.9kV FOR 4.9395E1529.4kV FOR 5.9276E15

1/2AD712

0.001mF

R

Figure 41. FDNR for 9-Pole Chebychev Filter

REF 5.0 dBm10 dB/DIV RANGE 5.0 dBm

MARKER 96 800.0 Hz90 dBm

START.0 HzRBW 300 Hz

STOP 200 000.0 HzST 69.6 SECVBW 30 Hz

Figure 42. High Frequency Response for 9-PoleChebychev Filter

AD712

REV. B 15

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

Mini-DIP(N-8)

TO-99(H-08A)

Cerdip(Q-8)

SOIC(R-8)

8

1 4

5

0.390 (9.91)

0.250(6.35)

PIN 1

SEATINGPLANE0.018 60.003(0.460 60.081)

0.035 60.01(0.890 60.25)0.165 60.01

4.19 60.250.18 60.01(4.57 60.76)

0.033 (0.84)NOM

0.100(2.54)TYP

0.125 (3.18)MIN

0.300 (7.62)REF

0.011 60.003(0.204 60.081)

0.195 (4.95)0.115 (2.93)

0.310(7.87)

15808

0.500 (12.70)MIN0.185 (4.70)

0.165 (4.19)

REFERENCE PLANE

0.019 (0.48)0.016 (0.41)

0.021 (0.53)0.016 (0.41)INSULATION

0.05 (1.27) MAX

0.040 (1.01) MAX

BASE & SEATING PLANE

0.33

5 (8.

50)

0.30

5 (7.

75)

0.37

0 (9.

40)

0.33

5 (8.

50)

0.034 (0.86)0.028 (0.71)

0.045 (1.1)0.020 (0.51)

6

2 8

7

54

3

1

0.200(5.1)TYP

0.100(2.54)BSC

458 BSCEQUALLY SPACED

BOTTOM VIEW

8

1 4

5

0.310 (7.87)0.220 (5.59)

PIN 1

0.005 (0.13)MIN

0.055 (1.35)MAX

SEATINGPLANE0.014 (0.36)

0.023 (0.58)

0.200 (5.08)MAX 0.150

(3.81)MIN

0.030 (0.76)0.070 (1.78)

0.125 (3.18)0.200 (5.08)

0.100(2.54)BSC

0.015 (0.38)0.060 (1.52)

0.405 (10.29) MAX

15808

0.220 (5.59)0.310 (7.87)

0.008 (0.20)0.015 (0.38)

0.25R(0.64)

8 5

41

0.1968 (5.00)0.1890 (4.80)

0.1574 (4.00)0.1497 (3.80)

0.2440 (6.20)0.2284 (5.80)

PIN 1

SEATINGPLANE

0.0098 (0.25)0.0040 (0.10)

0.020 (0.51)0.013 (0.33)

0.0688 (1.75)0.0532 (1.35)

0.0500(1.27)BSC

0.0098 (0.25)0.0075 (0.19)

0.050 (1.27)0.016 (0.40)

8808

0.0196 (0.50)0.0099 (0.25) x 458

C10

20c

14/

98P

RIN

TE

D IN

U.S

.A.