Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings universitet

gnipökrroN 47 106 nedewS ,gnipökrroN 47 106-ES

LiU-ITN-TEK-A-15/065--SE

PFC-design for frequencyconverter

David Kantzon

2015-11-30

LiU-ITN-TEK-A-15/065--SE

PFC-design for frequencyconverter

Examensarbete utfört i Elektroteknikvid Tekniska högskolan vid

Linköpings universitet

David Kantzon

Handledare Lars BackströmExaminator Anna Lombardi

Norrköping 2015-11-30

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© David Kantzon

LINKÖPING UNIVERSITY

Abstract

Department of Science and Technology

Master of Science in Electrical Engineering and Design

by David Kantzon

This thesis deals with power factor correction for three-phase systems. A boost-buck

topology was described, modeled and then simulated in MATLAB/Simulink. The sim-

ulation results show that the system provides a power factor over 99% over the tested

power output range. Moreover, the harmonic injection concept was introduced which

reduces the total harmonic distortion to 8.72% at full output power. A prototype system

was also built using an FPGA for the control system. The prototype did not provide the

performance seen in simulation but showed that the method is valid and does provide a

higher power factor when used.

Acknowledgements

I would like to thank Syncore Technologies AB for providing this opportunity to apply

and expand my knowledge in a wide variety of topics. Without the tip from Elias Olsson

I probably would not have ended up here and it is much appreciated. Furthermore,

I would also like to thank Lars Backström, Anna Lombardi and Kjell Karlsson for

providing guidance and support during my work. I would also like to thank the people

at Heltia AB for a warm welcome and lots of tips and tricks for my future work.

My brother has kept my spirits up during the work as well as my friends Rickard Hedlund

and Sebastian Lahti. The latter two also made sure I did not go up in smoke during

testing.

Last but not least, I highly appreciate the input and help I have received from Daniel

Forsberg during my work.

ii

Contents

Abstract i

Acknowledgements ii

List of Figures vi

List of Tables vii

Abbreviations viii

1 Introduction 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4 Scope and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Background Theory 4

2.1 Frequency converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 IEC 61000-3-2 Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Passive rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Active rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4.1 The single-switch DCM boost rectifier . . . . . . . . . . . . . . . . 9

2.4.1.1 Variable frequency PWM . . . . . . . . . . . . . . . . . . 12

2.4.2 Harmonic Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 The buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 Complete system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Modeling and Simulation 20

3.1 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1 Boost converter small signal model . . . . . . . . . . . . . . . . . . 21

3.1.2 Boost converter control-loop . . . . . . . . . . . . . . . . . . . . . 24

3.1.3 Buck converter small signal model . . . . . . . . . . . . . . . . . . 27

3.1.4 Buck converter control-loop . . . . . . . . . . . . . . . . . . . . . . 28

4 FPGA 30

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

iii

Contents iv

4.2 Fixed point representation . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.1 Variable gain controller . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.2 PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.3 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 PC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5 PCB design 37

5.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2 Hardware choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2.1 High power components . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2.1.1 Boost inductance . . . . . . . . . . . . . . . . . . . . . . 38

5.2.1.2 Bus capacitance . . . . . . . . . . . . . . . . . . . . . . . 39

5.2.1.3 Buck inductor . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2.1.4 Buck output capacitor . . . . . . . . . . . . . . . . . . . . 41

5.2.1.5 Power semiconductors . . . . . . . . . . . . . . . . . . . . 41

5.2.2 Low power components . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.2.1 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.2.2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.2.3 Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.2.4 Voltage sensors . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.2.5 Current sensors . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.2.6 OP-amp buffers . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.2.7 Auxiliary power supply . . . . . . . . . . . . . . . . . . . 43

5.2.2.8 Isolated PC interface . . . . . . . . . . . . . . . . . . . . 44

5.2.2.9 Small parallel rectifier . . . . . . . . . . . . . . . . . . . . 44

6 Evaluation 45

6.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2 Low voltage testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.1 Test 1: Aux PSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.2 Test 2: FPGA, ADC and gate-drive function . . . . . . . . . . . . 46

6.2.3 Buck converter control-loop . . . . . . . . . . . . . . . . . . . . . . 47

6.3 High voltage testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3.1 Test 1: Soft-start circuit . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3.2 Test 2: Buck converter with 230/133 V input . . . . . . . . . . . . 48

6.3.3 Test 3: Buck converter with 400/230 V input . . . . . . . . . . . . 48

6.3.4 Test 4: Full system test with boost engaged, 400/230 V input . . . 48

6.3.5 Test 5: Soft-start with higher delay . . . . . . . . . . . . . . . . . . 49

6.3.6 Test 6: Full system test, no harmonic injection . . . . . . . . . . . 50

6.4 Test 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7 Result and discussion 52

8 Improvements 53

9 Conclusion 54

Contents v

A Formulae 55

A.1 Critical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

B Simulation models 57

B.1 PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

B.2 Duty cycle limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

B.3 Main model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

B.4 Variable gain and load model . . . . . . . . . . . . . . . . . . . . . . . . . 61

Bibliography 62

List of Figures

2.1 Simplified schematic of frequency converter . . . . . . . . . . . . . . . . . 4

2.2 Single phase rectifier with LC-filter and resistive load . . . . . . . . . . . . 7

2.3 Phase voltage (blue) and input current (red) . . . . . . . . . . . . . . . . 7

2.4 Three-phase diode bridge with boost converter output stage . . . . . . . . 8

2.5 Different conduction modes in switching converters . . . . . . . . . . . . . 9

2.6 Single switch DCM rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Average current for M=1.5 and 2 . . . . . . . . . . . . . . . . . . . . . . . 11

2.8 Simplified view of harmonic injection . . . . . . . . . . . . . . . . . . . . . 14

2.9 Duty cycle variation during half a line period . . . . . . . . . . . . . . . . 15

2.10 Phase current with no injection . . . . . . . . . . . . . . . . . . . . . . . . 16

2.11 THD with no injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.12 Phase current with injection index m = 0.088π . . . . . . . . . . . . . . . 17

2.13 THD with injection index m = 0.088π . . . . . . . . . . . . . . . . . . . . 17

2.14 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.15 DCM boost rectifier with buck output stage . . . . . . . . . . . . . . . . . 19

3.1 Small signal model of DCM boost rectifier . . . . . . . . . . . . . . . . . . 21

3.2 Duty cycle as a function of output power . . . . . . . . . . . . . . . . . . 23

3.3 Static gain as a function of output power . . . . . . . . . . . . . . . . . . 23

3.4 Fitting curve for Kp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5 Input current waveform at Po = 750 W . . . . . . . . . . . . . . . . . . . 26

3.6 Input current waveform at Po = 1500 W . . . . . . . . . . . . . . . . . . . 26

3.7 Input current waveform at Po = 3000 W . . . . . . . . . . . . . . . . . . . 26

3.8 Buck converter small signal model . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Simplified overview of system layout . . . . . . . . . . . . . . . . . . . . . 31

4.2 Block diagram of variable gain controller . . . . . . . . . . . . . . . . . . . 33

4.3 Block diagram of PI controller . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 Simplified overview of system layout . . . . . . . . . . . . . . . . . . . . . 34

4.5 Converter PC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1 3D view of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

A.1 DC/DC boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

B.1 Sawtooth wave, control voltage (dashed) and resulting PWM signal . . . . 57

B.2 PWM module implementation . . . . . . . . . . . . . . . . . . . . . . . . . 58

B.3 Duty cycle limiter implementation . . . . . . . . . . . . . . . . . . . . . . 59

vi

List of Tables

2.1 IEC 61000-3-2 harmonic limits . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Test of variable gain controller . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 Voltage drop at load transients . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4 Voltage regulation at different loads . . . . . . . . . . . . . . . . . . . . . 28

4.1 PC interface control parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1 Test equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

vii

Abbreviations

LAH List Abbreviations Here

PCB Printed Circuit Board

IGBT Insulated Gate Bipolar Transistor

MOSFET Metal Oxide Semiconductor Field Effect Transistor

ADC Analog to Digital Converter

PSU Power Supply Unit

MATLAB Matrix Laboratory

DCM Discontinuous Conduction Mode

CrCM Critical Conduction Mode

CCM Continuous Conduction Mode

PFC Power Factor Correction

PF Power Factor

THD Total Harmonic Distortion

SMPS Switch Mode Power Supply

FPGA Field Programmable Gate Array

PWM Pulse Width Modulation

OP-amp OPerational Amplifier

viii

Chapter 1

Introduction

1.1 Introduction

Modern power supplies have many requirements that have to be met. Since the advent

of the AC transformer and the switching power supplies that followed much research

has been done in order to improve power capacity, power density, efficiency and voltage

regulation. In later years there has also been an increase in the research regarding clean

power. Clean power in this case does not refer to the method used to produce the power

but to the waveform of the input currents.

Passive rectification using diode bridges is a simple way of achieving AC to DC conversion

but it introduces large amounts of distortion. This is due to the diodes being reverse

biased for a large portion of the line voltage period. The diodes only conduct when the

voltage exceeds that of the output filter capacitors which results in pulsed input currents

used to charge the capacitor.

In order to alleviate this problem power factor correction (PFC) circuits can be intro-

duced. These can be either passive or active. Passive PFC circuits are fairly simple

to design but offer poor performance. Active PFC circuitry on the other hand uses a

switch-mode power supply (SMPS) either after the rectifier bridge or with the switches

integrated into the bridge legs to achieve the desired function. The added circuitry

is controlled in such a way that the line current tracks the input voltage making any

subsequent circuitry appear as a resistive load to the power source. Another important

aspect is that the output voltage can be controlled as opposed to the passive solutions.

1

Introduction 2

Furthermore, the use of a switched power supply allows for smaller filter components

thus increasing the power density. On the other hand, active PFC circuits demand an

increased control complexity in order for the desired functionality to be achieved.

1.2 Purpose

The aim of this project is to design and construct a PFC circuit which will power a

frequency converter. As it stands today, the frequency converter is powered by single

phase AC voltage which is rectified in order to produce the DC voltage used in the

system. Syncore Technologies AB would like the system to be powered from three-phase

AC in order to increase the available power. The three-phase AC/DC converter will

replace the current single phase AC input and rectification circuit and provide the DC

link voltage between the three-phase power input and frequency converter. It should

also provide PFC functionality.

The PFC converter will be powered by standard 400/230 V 50 Hz three-phase mains

and should provide a variable output voltage between 100-500 V. Available power out-

put should be 3 kW over the output range but is subject to change with regards to

the availability of non-custom commercial components capable of handling the required

currents and voltages. Moreover, the control system is to be implemented in an FPGA

in order to facilitate later integration with the frequency converter.

The converter should have a power factor of 99% or better and comply with the IEC

61000-3-2 class A standard regarding line current harmonics.

1.3 Methodology

A literature study is conducted in order to build an understanding of available methods

for power factor correction. One or two of these methods are then selected with respect

to desired functionality and studied further. The circuit chosen for construction is then

implemented first in simulation and then in hardware.

Introduction 3

MATLAB and Simulink SimPowerSystems is used for circuit and control simulation.

Altium Designer will be used to design the circuit board. For writing and testing VHDL

code Quartus II is used.

1.4 Scope and limitations

Some modeling of the chosen converter system will be done in order to obtain necessary

information. Advanced modeling and control methods are beyond the scope of this

thesis. Instead the control methods employed will be ones suggested and evaluated with

successful results in literature. The chosen architecture will be implemented in hardware

and the control system in an FPGA environment.

Modelling of the frequency converter is a whole topic in itself and for the sake of sim-

plicity it will be treated as a load for the AC/DC converter.

1.5 Thesis outline

Chapter 2 deals with general theory on the topic of AC-DC conversion as well as more

detailed analysis of the chosen converter/converters. Chapter 3 details modelling of

the converter/converters and the design of the control system. Chapter 4 gives an

insight into the choice of digital vs analog control as well as how the control system and

other blocks were implemented in code. Chapter 5 describes the process of specifying

components and some segments with light theoretical background. Chapter 6 is a review

and comparison of live and simulated results.

Chapter 2

Background Theory

2.1 Frequency converter

When there is a need to supply a system with alternating current of a different frequency,

a frequency converter is used. The converter utilizes a DC-link voltage and semicon-

ductor switches that are controlled with a sinusoidal PWM pattern. By changing the

frequency of the control signal the frequency of the output voltage is also changed.

Figure 2.1 shows a simplified schematic of a frequency converter. Other common de-

nominations are inverter or variable speed drive.

Figure 2.1: Simplified schematic of frequency converter

4

Background Theory 5

2.2 IEC 61000-3-2 Standard

In later years there has been an increase in the adoption of more stringent standards

governing the effects of power supplies on the mains network. One of these is the IEC

61000-3-2 standard which provides limits on the levels of harmonic currents imposed

by a system which draws up to 16 A per phase. There are several different classes of

equipment and the limits referenced here will be the Class A ones for balanced three-

phase equipment. Table 2.1 shows the limits for individual harmonics up to the 40th

harmonic [1].

Harmonics [n] Limit [A]

3 2.3

5 1.14

7 0.77

9 0.4

11 0.33

13 10.21

15 ≤ n ≤ 39 0.15 x 15/nEven harmonics

2 1.08

4 0.43

6 0.3

8 ≤ n ≤ 40 0.23 x 8/n

Table 2.1: IEC 61000-3-2 harmonic limits

Background Theory 6

2.3 Passive rectifiers

The most common method of obtaining a DC voltage from an AC source is to use a

diode rectifier. The rectifier circuit is commonly followed by an LC-filter which produces

a smoother voltage waveform. Although simple and fairly efficient these circuits distort

the input current introducing a phase displacement relative to the input voltage as well

as harmonics. The harmonics arise from the fact that the diodes only conduct when

the input voltage is higher than the output voltage. This creates peak currents centered

around the peak of the input voltage. Another drawback of these circuits is that there is

no ability to control the output voltage. Figure 2.2 shows a single phase rectifier circuit

with an LC-filter powering a resistive load and Figure 2.3 shows the phase voltage and

input current waveforms.

The power factor of a circuit is the product between displacement- and distortion power

factor where the two parts are defined as:

Displacement PF =P

S=

Real power

Apparent power= cos(φ) (2.1)

Distortion PF =1

√

1 + THD2i

(2.2)

Resulting in a total power factor of:

PF = cos(φ)1

√

1 + THD2i

(2.3)

In equation 2.3 φ denotes the phase displacement between voltage and current. THDi

is the total harmonic distortion of the input current which is defined as

THDi =

√∑

∞

n=2 I2n

I1(2.4)

where I1 is the fundamental component of the current [2].

Background Theory 7

Figure 2.2: Single phase rectifier with LC-filter and resistive load

Figure 2.3: Phase voltage (blue) and input current (red)

A circuit where the voltage and current are in phase with no distortion has a PF of 100%.

In the diode rectifier there is both a phase displacement as well as harmonic currents

which results in a decreased power factor. Single-phase rectifiers with LC-filters can

give a maximum PF of 90%. Three-phase diode rectifiers offer a better inherent power

factor. Although more efficient than the single-phase variant the maximum power factor

is still only around 95% and there is no control of the output voltage [3].

Background Theory 8

2.4 Active rectifiers

To enable a variable output voltage, common DC/DC converters can be connected to

the rectifier output. The addition of a converter improves the voltage regulation and

also enables matching with different mains voltages while maintaining desired output

voltage.

Figure 2.4: Three-phase diode bridge with boost converter output stage

Figure 2.4 shows a three-phase rectifier with a boost converter added to the output as an

example. Depending on the application a step-up or step-down converter may be used

as well as their transformer isolated versions. While solving the problem of variable

output voltage these circuits still suffer from distortion of the input current.

PFC rectifiers utilize switching devices to achieve both PFC function and a variable

output voltage. These can be of a direct three-phase type or phase modular systems

built from three identical single phase circuits. Phase modular systems offer a higher

redundancy in case of failure or unbalance somewhere in the system. On the other hand,

the cost and complexity is higher and one or several isolated downstream converters is

required to fully eliminate undesired interactions between them. This thesis will only

deal with direct three-phase systems.

Background Theory 9

Like their DC/DC counterparts, three-phase variants can be characterized as buck, boost

or buck-boost types. Other types such as the Cúk and transformer isolated versions also

exist. Moreoever, the characterization of the different conduction modes is the same.

Figure 2.5: Different conduction modes in switching converters

In Figure 2.5 the different conduction modes can be seen where D is the duty cycle and

Ts is the switching period. The lower graphs show the inductor current for each mode.

In DCM the current is allowed to reach zero between each switching instant. CrCM,

also know as boundary conduction mode, is achieved by turning on the switch as soon

as the current reaches zero and in CCM the current remains fairly constant.

2.4.1 The single-switch DCM boost rectifier

A simpler way of achieving PFC function and controllable output voltage is to move the

DC side inductance seen in Figure 2.4 into each phase as seen in Figure 2.6.

PFC function is achieved by controlling the switch so that each of the inductor currents

remain in DCM. In each switching cycle the peak current follows the phase voltage and

the average current a sinusoidal envelope. The advantage of this circuit is the simplicity

of control and a high switch utilization due to the use of only one switch. A disadvantage

is the large peak currents appearing in the circuit due to DCM operation. Furthermore,

due to the boost topology the output voltage must be higher than the peak line-to-line

input voltage resulting in a higher voltage stress on the semiconductors.

Under balanced and undistorted input the phase voltages are defined as follows

Background Theory 10

Figure 2.6: Single switch DCM rectifier

Va = Vm sin(ωt)

Vb = Vm sin(ωt−2π

3)

Vc = Vm sin(ωt−4π

3)

(2.5)

where Vm =√2VRMS

Assuming balanced input the currents in each phase will have the same shape. Over

the interval [0, π2 ] the average current in phase A is given by Equation 2.6 [4]. The

results can be extended to cover the range [0, 2π] for all three phases due to symmetrical

properties of the input waveforms.

[0 ≤ ωt ≤ π6] ia =

VoD2

2Lfs

sin(ωt)√M3− 3 sinωt

[π

6≤ ωt ≤ π

3] ia =

VoD2

2Lfs

M sin(ωt) + 12 sin(2ωt− 2π3 )[√M3− 3 sin(ωt+ 2π3 )][M − sin(ωt+ π6 )]

[π

3≤ ωt ≤ π

2] ia =

VoD2

2Lfs

M sin(ωt) + sin(2ωt+ π3 )

[√M3 + 3 sin(ωt+ 2π3 )][M − sin(ωt+ π6 )]

(2.6)

Background Theory 11

Here Vo is the output voltage, D is the duty cycle, L is the inductance in each phase and

fs is the switching frequency. M is the voltage conversion ratio defined as:

M =Vo√3Vm

(2.7)

.

The phase current for two voltage gains is plotted in Figure 2.7 for a converter with

400/230 V input, 800 V output, inductance L=150 uH and switching freuqency fs = 40.

A perfect sine wave is plotted with a dashed line for reference.

Figure 2.7: Average current for M=1.5 and 2

If M is kept constant at varying load only the duty cycle changes. Therefore, the

magnitude of the current changes but retains its shape. Although the current is close to

a sinusoidal shape it still distorted. This distortion is caused mainly by the 5th harmonic

as well as higher harmonics to a lesser degree. Due the presence of these harmonics the

power output of the DCM boost rectifier is limited to around 6 kW at 800 V output

voltage while still complying with the 61000-3-2 limits.

It can be shown through Fourier analysis that the THD of the input current is greatly

dependent on M. As the voltage gain is increased the THD is decreased [5]. While

increasing M is a straightforward way of lowering THD it is not desirable as it puts

further stress on the components.

Background Theory 12

2.4.1.1 Variable frequency PWM

Another way of decreasing THD without increasing the voltage gain is by operating the

converter in CrCM. A current sensor is added after the rectifier bridge and the switch

is turned on the instant the current falls to zero. Operating the converter in CrCM

does reduce THD but results in a variable switching frequency which depends on both

load and input voltage. Variable switching frequency makes designing filters difficult.

Moreoever, the inductor and device selection is complicated [6].

Background Theory 13

2.4.2 Harmonic Injection

A fixed switching frequency is preferred as it simplifies the design of the converter. As

mentioned in section 2.4.1 this results in a large 5th harmonic in the input currents,

limiting the available output power while still remaining in compliance with the 61000-

3-2 standard. The higher order harmonics are well below the limits even for power levels

above 10 kW [7].

Due to the dominant 5th harmonic, the three-phase input current can be approximated

as in Equation 2.8, neglecting higher order harmonics. This equation is valid for fixed

frequency and constant duty cycle operation.

ia = I1 sin(ωt)− I5 sin(5ωt)

ib = I1 sin(ωt−2π

3)− I5 sin(5ωt−

2π

3)

ic = I1 sin(ωt−4π

3)− I5 sin(5ωt−

4π

3)

(2.8)

As the 5th harmonic is the dominant one, it stands to reason that reducing its magnitude

will also reduce THD. Moreoever, reducing the level of the 5th harmonic also allows for

higher power output while complying with the 61000-3-2 standard.

Several methods for reducing the distortion of the input current have been suggested.

In [5] a variable duty cycle is proposed in order to reduce the THD.

d(t) = D[1 +m sin(6ωt+3π

2) (2.9)

Equation 2.9 shows a duty cycle that is modulated by 6th order harmonic with modula-

tion index m. The modulation index indicates the amount of modulating signal added

to the control signal. By injecting a 6th order with proper modulation index the 5th

harmonic in the input current is suppressed. However, at the same time the magnitude

of the 7th harmonic is increased although THD is improved. This reduction in the 5th

harmonic allows operation at higher power levels.

Background Theory 14

To obtain the 6th harmonic the three-phase voltages are fed through a separate rectifier

and then filtered. This could potentially lead to an incorrect phase in the injected signal

with undesired results.

Another method of harmonic reduction exists that also relies on injecting a modulating

signal into the duty cycle. In this method described in [4] the three-phase voltages are

also fed through a parallel rectifier and injected into the control signal. Figure 2.8 pro-

vides a simplified description of the control circuit with the added injection.

Figure 2.8: Simplified view of harmonic injection

In this method there is no need for any filtering of the rectified voltage to obtain the de-

sired signal which is naturally synchronized to the three-phase input voltages. However,

some form of voltage step down and DC-block capacitor is still needed. However, the

injection described in [4] does not include a multiplier and as such the injection does not

scale with the load (duty cycle). Therefore the injection in this thesis is a mixture of the

two. An analog implementation requires quite a few components including some form

of multiplier but in this thesis the control system is digital making the implementation

of inversion and multiplier seen in Figure 2.8 easier.

Equation 2.10 shows the modulated duty cycle and Figure 2.9 shows how the duty cycle

varies during half a line period.

D(t) = D[1 + d(t)]

d(t) =m

π

∞∑

n=1

(−1)n6(6n)2 − 1 cos

(2.10)

Background Theory 15

Figure 2.9: Duty cycle variation during half a line period

Looking at Equation 2.10 it is seen that the modulated duty cycle contains not only the

6th order harmonic but also 12th as well as 18th order harmonics and so on. Compared

to injecting only the 6th order harmonics this contributes to a more improved THD.

The suggested injection was simulated in MATLAB at full output power with and with-

out injection. When using injection the modulation index was set to 0.088π. This results

in the ratio between the 7th and 5th harmonic being 0.675.

0.77 A

1.14 A= 0.675 (2.11)

In Equation 2.11 0.77 A denotes the magnitude of the 7th harmonic and 1.14 A the

magnitude of the 5th. Both of these magnitudes are exactly the limits imposed by the

IEC standard. Keeping this ratio will allow the converter to operate at a higher output

power while still meeting the IEC limits.

Figures 2.10 and 2.11 show the phase current and THD for the converter with no injection

at 3 kW output. The shape of the current is close to the one seen in Figure 2.7 for M=1.5

and as mentioned before, the 5th harmonic is the dominant one. Using MATLABs built

in FFT analysis tool the THD is calculated to be 10.58%.

Background Theory 16

Figure 2.10: Phase current with no injection

Figure 2.11: THD with no injection

After adding injection with modulation index m = 0.088π the shape of the current and

THD is improved. Figure 2.12 shows the phase current when using injection. While it

is not entirely sinusoidal it is much closer than without any injection. As can be seen

in Figure 2.13 the current still contains a modicum of low frequency harmonics but the

5th harmonic has decreased in magnitude while the 7th has increased. With injection

the THD is decreased to 8.72%.

It is worth noting that the IEC-61000-3-2 limits are met both with and without injection.

However, regardless of output power, a reduction of THD is beneficial and helps improve

the power factor.

Background Theory 17

Figure 2.12: Phase current with injection index m = 0.088π

Figure 2.13: THD with injection index m = 0.088π

Background Theory 18

2.5 The buck converter

The desired output of the whole system ranges between 100 and 500 V. Due to the

high output voltage generated by the boost stage to provide PFC function some form

of step-down converter is needed. Step-down converters exist in both isolated and non-

isolated versions where isolated ones use transformers to provide the isolation. Whether

isolation is required depends on the application and environment in which the equipment

is to be used. Due to the time and cost involved in designing and manufacturing of a

transformer suitable for high power applications a non-isolated converter was chosen.

Any communications interface built into the system will require isolation so as not to

harm connected equipment.

Figure 2.14 shows a schematic of a buck converter along with a simplified diagram of

the control-loop. When the switch is in the off-state, the diode provides a path for the

current.

Figure 2.14: Buck converter

A disadvantage of the buck converter is its pulsating input current and need for isolated

gate-drive due to the high-side switch. However, because of the switch lying directly in

the current path, current limiting can be implemented without additional components

as opposed to the boost converter.

Whereas the boost front-end depends on DCM operation for PFC function the buck-

converter can be run in any of the conduction modes. CCM was selected to reduce peak

Background Theory 19

currents and simplify control-loop design [2]. In CCM, the duty cycle is load-independent

and can described by Equation 2.12.

D =VoutVin

(2.12)

2.6 Complete system

Figure 2.15: DCM boost rectifier with buck output stage

Figure 2.15 shows a diagram of the complete system. In the diagram the two control

loops are omitted to provide a clear picture of the circuit. Other external circuitry such

as auxiliary power supply and communications are also omitted. Each converter has its

own loop where one controls the bus voltage, Vbus, which provides PFC function along

with the harmonic injection. The buck converter control loop provides control over the

output voltage Vo.

Chapter 3

Modeling and Simulation

This chapter details how the converters are modeled and controlled.

3.1 Modeling

Small signal modeling is an important tool in understanding and controlling converters.

From the models transfer functions can be obtained which give a view of the converter

behavior with respect to component values and load conditions. When modelling systems

which contain converters in series there are some aspects which need to be taken into

consideration. A buck-boost converter needs to be modeled as whole due to the fact that

there is no capacitor decoupling the two stages. The boost-buck converter on the other

hand can be seen as two separate converters. Viewing the buck converter as effectively

being a variable impedance to the boost converter, the two converters can be modeled

separately, which is done in this project.

There exists several ways of modelling power converters. Among these approaches is

state space averaging described in [8]. Each switching state has its own state space de-

scription. These are then averaged with respect to duty cycle and the transfer functions

are obtained. Although a valid way of modeling power converters it gives less insight

into the function of the actual circuit. A better and more intuitive way is to model only

non-linear elements such as the switch, leaving any time-invariant components as they

are. The resulting model can then be understood through ordinary circuit analysis.

20

Modeling and Simulation 21

3.1.1 Boost converter small signal model

AC/DC converters can be modeled as DC/DC converters on the assumption that the

switching frequency is much larger than the line frequency. Between each switching

instance the change in input voltage is small enough so the converter sees what is ap-

proximately a DC voltage. In [9] a small signal model is developed for the single switch

DCM boost rectifier. Here the circuit is first modeled as two boost converters in parallel,

each with an inductance three times that of the inductance lying in each phase of the

DCM rectifier. These converters are then modelled as one converter with a set of equiv-

alent parameters. The resulting model can be seen in Figure 3.1 with the equivalent

parameters given in equation 3.1.

Figure 3.1: Small signal model of DCM boost rectifier

gi =M(M − 1)

ro

go =M

(M − 1)rogf =

2M

ro

ko =−2Vodro

(3.1)

The equivalent boost inductor is given by Le = 1.5L and the input voltage for the model

is the RMS value of the line-to-line voltage:

Modeling and Simulation 22

VinRMS =

√

π

3

∫ π3

0V 2ab d(ωt) =

√

π

3

∫ π3

0V 2m cos

2(ωt) d(ωt)

=

√

3

2+

9√3

8π= 1.46Vm

(3.2)

From this equivalent circuit a control-to-output transfer function e.g. the effects of

variation in duty cycle on the output can be calculated. This is done with regular

circuit analysis and results in the following transfer function,

Gvd(s) =2(M − 1)Vo(2M − 1)d

(1 + ssz1

)

(1 + ssp1

)

(1− ssz2

)

(1 + ssp2

)(3.3)

where the poles and zeroes are calculated as seen in Equation 3.4

sp1 =2M − 1

(M − 1)roC

sp2 =(M − 1)roM3Le

sz1 =1

rCC

sz2 =ro

M2Le

(3.4)

ro =V 2oPo

(3.5)

As mentioned before, the load resistance ro is seen as a variable impedance imposed by

the buck converter depending on the load. ro can be calculated for any load using the

boost converter output voltage and total power consumption resulting in Equation 3.5.

M = Vo/VinRMS is the voltage gain and d is the duty cycle.

Looking at the static gain of the control-to-output transfer function one can see that it

is load dependent. From Equation A.5 it is apparent that the duty cycle decreases as

the load decreases. The duty cycle and static gain as a function of load are plotted in

figures 3.2 and 3.3 respectively for a converter with parameters seen in Table 3.1. Bus

Modeling and Simulation 23

voltage refers to the boost converter output voltage. Please refer to Appendix B for a

more in-depth description of component choices.

Parameter Value

Input voltage 400/230 V / 50 Hz

Bus voltage 800 V

Output voltage 400 V

Power output 3 kW

Boost inductance 150 uH

Bus capacitance 1200 uF

Buck inductor 560 uH

Output capacitor 680 uF

Switching frequency 40 kHz

Table 3.1: Converter parameters

Figure 3.2: Duty cycle as a function of output power

Figure 3.3: Static gain as a function of output power

Modeling and Simulation 24

In Figure 3.3 it can be seen that as the load decreases the static gain approaches infinity.

Another problem seen in the transfer function is the pole sp1. Like the static gain it is

also load dependent and as the load decreases it approaches the imaginary axis. This

causes a large phase delay at low frequency. The other pole and zeroes stay far away

from the imaginary axis regardless of load.

3.1.2 Boost converter control-loop

Due to the operation of the converter only a single control-loop is needed. A voltage

controller ensures both voltage regulation and PFC function. On the other hand, due to

the load dependence seen in the static gain and a pole, a controller with fixed parameters

will not offer optimum performance over the whole load range. However, since the control

of the system is to be implemented in a digital environment a non-linear controller can

be designed fairly easily.

As an example of the problem with the static gain, using a P-type controller designed

for full load is not be sufficient if the load changes. As the load decreases the output

voltage will increase, potentially leading to failure somewhere in the circuit. To solve this

problem a variable P-type controller is proposed. Controllers where the dynamics are

changed depending on operating parameters are often called gain scheduling controllers.

First, the value of the static gain at full load is divided by the gain at successively lower

loads resulting in the curve seen in Figure 3.4.

Figure 3.4: Fitting curve for Kp

Then, a value for the proportional term in the controller, Kp, is obtained through trial

and error in simulation at full load. The value obtained for Kp in simulation was 8 which

Modeling and Simulation 25

provided an output voltage with a very small overshoot and static error. By multiplying

the value for Kp at full load with the values from the fitting curve in Figure 3.4 a

load-varying gain is obtained.

A simulation was done in order to verify the function of the variable gain controller. In

this simulation the load starts at 25% of full load and doubles at evenly spaced times

until reaching full load. As the load increases, Kp changes to the appropriate value

obtained through fitting. The results can be seen in Table 3.2 and all values were taken

after the controller had stabilized the voltage between load steps. For a view of the

simulation model please refer to section B.4 in Appendix C.

Po (W) Kp Static Error (%) THD (%) PF (%)

750 4 + 0.2 13.19 99.14

1500 5.66 - 0.08 10.34 99.47

3000 8 - 0.3 8.71 99.62

Table 3.2: Test of variable gain controller

For all loads the static error is very small and the controller performance can be con-

sidered good. Although voltage regulation is satisfactory at different loads the THD

increases as the load is decreased. This results in a lower power factor although the

value stays above the desired 99%.

Looking at the static error the difference in voltage gain between loads is very small.

With this in mind the only change in converter operation should be a decrease in duty

cycle along with the decreasing load. According to section 2.4.1, page 11, the duty cycle

only affects the magnitude and not the shape of the input current. Furthermore, the

decreasing duty cycle means a lower control signal and the harmonic injection should

scale along with a decrease in this signal. As such, the reason for an increase in THD

with decreasing load is not easily determined. Looking at Vm in simulation it is seen that

at 750 W of output power it amounts to 325.5 V. At full load it amounts to 317.9 V. For

low and full load M becomes 1.42 and 1.45 respectively according to Equation 2.7. The

smaller M at low load could be a reason for the increased THD although the difference

is very small.

Figures 3.5 through 3.7 show the input current waveforms for the respective loads.

Modeling and Simulation 26

Figure 3.5: Input current waveform at Po = 750 W

Figure 3.6: Input current waveform at Po = 1500 W

Figure 3.7: Input current waveform at Po = 3000 W

Modeling and Simulation 27

3.1.3 Buck converter small signal model

Modelling the buck-converter is done in a similar way to the boost converter. The

time-invariant elements are the same but the switch is modeled in a different way due

to the assumed CCM operation of the circuit. Instead of a set of equivalent resistive

elements the switch and diode is modeled by a fictive transformer which passes both AC

and DC voltages. Duty cycle dependent voltage and current sources are added on the

appropriate sides of the transformer as well. Figure 3.8 shows the model of the buck

converter [2].

Figure 3.8: Buck converter small signal model

Like in the boost converter model the control-to-output transfer function can be ob-

tained through circuit analysis. The buck converter transfer function can be seen in

Equation 3.6 where D is the duty cycle.

Gvd(s) =VoD

1

1 + sQω0

+ ( sω0)2

(3.6)

The quantities Q and ω0 are defined in Equation 3.7.

Q = R

√

C

L

ω0 =1√LC

(3.7)

Modeling and Simulation 28

There is a certain load dependence in this transfer function also. However, assuming

CCM operation, the load only affects the placement of the poles. Furthermore, even

though the duty cycle changes with the output voltage as seen in Equation 2.12 the

static gain remains constant. This is easily proven through simple analysis. The static

gain is defined in Equation 3.6 as Vo/D. Moreover, D is defined as Vo/Vin where Vin in

this case is the boost converter output voltage Vbus Substituting the expression for D

into the one for static gain one obtains a static gain which equals a static gain which

equals Vin = Vbus. As the boost converter output/bus voltage is to be kept constant the

static gain should also remain constant. Of course, some fluctuations during operation

occur but in the steady state they should be small and can be considered negligible.

3.1.4 Buck converter control-loop

To control the buck-converter output voltage a PI-type controller was chosen. The

proportional and integral gains Kp and Ki were adjusted in simulation to obtain good

reference following at full load. After that the same simulation as in section 3.1.2 was

run where the load is increased at evenly spaced times. This was to investigate how the

controller handles the load steps and what kind of voltage drops might be encountered.

These voltage drops are the effect of the capacitor having to supply the load current

while the controller adjusts to the sudden change in load. In Table 3.3 ∆Po denotes the

change in output power between the three different loads. ∆t denotes the time elapsed

between a load transient and the output voltage regaining the desired value.

Po (W) ∆t (s) Voltage drop (V)

750 7 5.2

1500 5 2.8

Table 3.3: Voltage drop at load transients

Po (W) Static error (%)

750 ∼ 01500 ∼ 03000 ∼ 0

Table 3.4: Voltage regulation at different loads

Modeling and Simulation 29

As is seen in Table 3.3 the largest voltage drop occurs when the load is increased from

750 to 1500 W. A 5.2 V drop in comparison to 400 V is not a problem and neither is 2.8

V. During all loads the controller followed the reference with no observable static error.

The only difference between the different loads is an increase voltage ripple which is to

be expected when the load increases.

Chapter 4

FPGA

This chapter describes the implementation of the digital control system in an FPGA

environment.

4.1 Overview

Control of power converters can be realized by either analog or digital circuits. Analog

control loops do not require any sampling but are susceptible to variations in compo-

nents. Moreover, tuning of the analog circuits is tedious as components need to be

replaced.

Digital control loops implented in a DSP or in this case, an FPGA, offer easier tuning

of parameters. Furthermore, the parameters can be changed while the system is online.

Monitoring of converter performance as well as safety functions such as current limiting

can also be implemented in code. A disadvantage is the need to sample the signals used

in the control loops. When using an FPGA this requires the addition of an external

ADC.

In this project the control system is implemented on a DE0-Nano development board.

The same board was also used to control the frequency converter previously designed

by Syncore. On the board is an FPGA from the Cyclone IV family made by Altera

along with headers for connecting to peripheral devices. Figure 4.1 shows a simplified

overview of the connection between power conversion circuits and control logic.

30

Digital Control 31

Figure 4.1: Simplified overview of system layout

4.2 Fixed point representation

The physical signals are converted by the ADC and sent to the FPGA via serial interface.

Although a parallel interface is also possible it was not used because of a lack of input

pins on the FPGA. Once converted, the signals are in 16-bit two’s complement format.

The MSB denotes the sign of the sampled data with 1 being negative and vice versa.

All the lower bits contain info about the magnitude of the signal.

In order to re-obtain the signals sampled by the ADC the data is converted into a fixed

point format known as Qm.n. A Qm.n number is also a sort of two’s complement number

but includes fractional bits along with the sign and integer bits . This was done to gain a

higher resolution but also have the signal magnitudes resemble the ones in control-loops

used in simulation.

A Qm.n format number is defined by the quantities m and n where m denotes the

amount of integer bits and n the fractional bits. The number of bits equals m+n+1 as

the sign bit is also included. The range and resolution of a Qm.n number is defined in

Equation 4.1.

Digital Control 32

Range : [−2−m , 2m − 2−n]

Resolution : 2−n(4.1)

Q15.16 (32-bit) format was chosen in this project as a simple design choice. The resolu-

tion of a Q15.16 number is an order of magnitude higher than the LSB from the ADC

and the range is more than enough for any signal that might occur in the control-loops.

Other formats were explored during work but Q15.16 seemed to give results closest to

the ones in simulation. The range and resolution of a Q15.16 number can be seen in

Equation 4.2.

Range : [−32768 , 32767.9]

Resolution : 1.5259 · 10−5(4.2)

Digital Control 33

4.3 Block description

This section describes the more important blocks responsible for primary functions in

the system. Blocks implemented for reading from ADC, communications interface and

PWM signal generation are omitted.

4.3.1 Variable gain controller

Figure 4.2: Block diagram of variable gain controller

Figure 4.2 shows a block schematic of the variable gain controller. The output voltage,

in this case the 800 V bus voltage, is subtracted from the reference voltage to create an

error signal. Furthermore, the buck output voltage and current is multiplied to indicate

at what power the system is operating. This product is sent to a look-up table which

selects the appropriate gain depending on the output power. The error is then multiplied

by the selected gain and the product, Vctrl, is sent to the mixer.

Digital Control 34

4.3.2 PI controller

Figure 4.3: Block diagram of PI controller

In Figure 4.3 the internal structure of the PI regulator is seen. The error signal is sent to

two multipliers where it is multiplied by Kp and Ki respectively. A latch is implemented

that adds the previous integral error KiErrorD for the integrator every time the ADC

signals that a new value is coming byt setting Update to 1. The proportional and integral

errors are then added together and the result sent to the PWM module controlling the

buck converter.

4.3.3 Mixer

Figure 4.4: Simplified overview of system layout

The mixer seen in Figure 4.4 is responsible for the harmonic injection. Vctrl is sent from

the variable gain controller and multiplied by the modulation index m. This product is

then multiplied by the inverted signal coming from a small rectifier which also contains

Digital Control 35

a DC block capacitor. The unmodified Vctrl and the mixed signal is added to created

the control signal which is sent to the PWM module controlling the boost stage.

Digital Control 36

4.4 PC interface

Figure 4.5: Converter PC interface

A PC interface was written in C# to allow control over converter parameters during

operation. The user may change several parameters which are listed in Table 4.1.

Slider Control parameter

Boost voltage Boost stage output voltage

Buck Voltage Buck stage output voltage

Boost PWM Frequency Boost converter switching frequency

Buck PWM Frequency Buck converter switching frequency

Buck Kp Buck feedback propoprtional gain

Buck Ki Buck feedback integral gain

Table 4.1: PC interface control parameters

Chapter 5

PCB design

This section details the choice of main power components and low power electronics.

5.1 Layout

Figure 5.1: 3D view of PCB

In Figure 5.1 the whole PCB can be seen. All high power components were placed in the

upper areas of the board with the exception of the buck inductor and output capacitor.

37

PCB design 38

5.2 Hardware choices

In the converter it was desired that as many components as possible should be surface

mounted. Components made to withstand large stresses on the other hand are usually

through-hole mounted or in some cases, chassis-mounted. When choosing components

for use in the project some components had to be through-hole mounted such as large

capacitors and inductors. Chassis-mounted components were preferably avoided because

of the associated cost and size. However, if one would want to evaluate or switch to a

chassis-mounted component it is easily done even after fabrication as these are connected

to the circuit via wires.

5.2.1 High power components

5.2.1.1 Boost inductance

The boost inductance is a critical component in the converter. To ensure DCM operation

under all conditions the results from Appendix A.1 can be used. If the inductor is

selected so that Pc is always greater than Po the converter will operate in DCM. Due

to the periodic nature of the input voltages the duty cycle, critical power and delivered

power will vary with time. In some instant the critical power will be at a minimum and

the inductor should be chosen with this in mind.

Assuming balanced input voltages the converter seen in Figure A.1 can be said to have

the following input voltage

Vin = max[|Vab(ωt)|, |Vbc(ωt)|, |Vca(ωt)|] (5.1)

which repeats every 60◦and has a maximum at ωt = n x 60◦, n = 0, 1, 2... with an

equivalent inductor Le equal to 2L. The equivalent inductor stems from the fact that at

each maxima one phase voltage is zero and the other voltages see two inductors in series.

When the input voltage reaches the maximum, the duty cycle and in turn the critical

power will reach its minimum. Any increase in load this moment will results in the

converter operating in CCM. If the inductor is selected so that the converter operates

in DCM in these moments and at full load, the converter will always operate in DCM.

PCB design 39

For a 400/230 V input the input voltage reaches its maximum at ωt = 0◦ and 60◦

resulting in

Vin = |Vab(0◦)| =√3Vm cos(0

◦) = 563.4 V (5.2)

The duty cycle in CCM is D = 1− Vin/Vo = 0.2958. In order to ensure DCM operationthe critical power should be equal to the maximum load. For a boost output voltage of

800 V, maximum output power Pomax = 3kW and switching frequency fs = 40kHz the

equivalent inductor becomes

Le =V 2o

2PomaxfsD(1−D)2 = 391.2 uH (5.3)

The desired boost inductance is half the equivalent inductance, 195.6 uH. An inductance

of 150 uH was selected to provide some margin as well as an increased current handling

capability.

5.2.1.2 Bus capacitance

For selecting the bus capacitance between stages equation 5.4 can be used. Here I is

the average current flowing between the boost and buck stage calculated by dividing the

maximum output power with the bus voltage seen inbetween converters. Since the bus

voltage is to be kept at 800 V and full output power is 3 kW this results in an average

current of 3.75 A. The term 6ωl comes from the AC component of the rectified voltage

which is of sixfold frequency compared to the line frequency fl which is 50 Hz.

Max voltage ripple ∆v was set to 2 V which can be considered small in relation to the

bus voltage.

C =I

6ωl∆v

ωl = 2πfl

∆v = Desired voltage ripple

(5.4)

PCB design 40

With the specified values for the parameters the calculated value for the bus capacitance

is 995 uF. Due to the high voltage and current stress imposed on the bus capacitance

the value was scaled up to 1200 uF. Four 1200 uF capacitors connected in series-parallel

gives an equivalent of one 1200 uF capacitor but also handles the high voltage and

current. Since there is a tolerance to the capacitance in each capacitor some unbalances

in voltage over them may occur. Therefore, balancing resistors were also included.

5.2.1.3 Buck inductor

The buck inductor value is usually specified with a certain ripple current in mind. Ripple

current is an AC variation around the output current with amplitude ∆iL. Common

values for for the ripple current are typically in the range of 10-30% . With an output

current of 7.5 A at 400 V output, 800 V input and an allowed ripple of 20% (1.5A) the

required inductor value can be calculated as in equation 5.5 [2].

L =(Vin − Vout)D

2∆iLfsw

D =VoutVin

=400

800= 0.5

∆iL = 1.5A

fsw = 40kHz

⇒ L = 1.7mH

(5.5)

Commercially available inductors of this rating are chassis mounted and a choice was

made to go with a smaller through-hole mounted inductor. The largest through-hole

mounted inductor found at resellers had an inductance of 560 uH. Using equation 5.5 and

solving for ∆iL with L set to 560 uH the ripple current would amount to approximately

4.5 A or 60% of the output current. This was deemed unacceptable but the desired ripple

current can be obtained with the smaller inductor if switching frequency is increased.

The boost- and buck converter do not have to operate at the same switching frequency.

Due to each converter having its own switch it is possible to set separate switching

frequencies in software. Once again, using equation 5.5 with the same parameters as

before but solving for fsw , one can see that the desired inductor ripple can be obtained

at a switching frequency of 120 kHz.

PCB design 41

5.2.1.4 Buck output capacitor

Another important component in the buck converter stage is the output capacitor. It is

responsible for filtering the ripple current in the inductor as well as providing a smooth

output voltage. Furthermore, in the event of increased load it should supply the required

current while the control system responds to the change.

Cbuck =1−D

∆VoutVout

8Lfsw2 (5.6)

Equation 5.6 gives a minimum capacitance value for achieving the required voltage ripple.

For a switching frequency of 40 kHz , output voltage of 400 V and an accepted ripple

voltage of 1 V the minimum capacitance becomes 28 uF. On the other hand, capacitors

need to be able to handle the ripple current from the inductor as well. Capacitors that

can handle voltages up to 500V need to have their capacitance increased in order to

handle larger ripple currents.

ICrms =∆iL√12

= 1.3 A (5.7)

Equation 5.7 gives the capacitor ripple current with fsw at 40 kHz and previously selected

inductor of 560 uH. A capacitor with 680 uF was selected to accommodate this current

with some added margin.

5.2.1.5 Power semiconductors

All the switches and diodes in the system responsible for power conversion need to handle

large voltages and currents. The reverse blocking voltage of the semiconductors have

the following requirement:

VR = Vbus = 800V (5.8)

For the required current handling an average forward current capability for all semicon-

ductors was selected to equal or be larger than the maximum peak current appearing

PCB design 42

in the system. The various currents are obtained through a graphical process detailed

in [10]. With the required voltages and currents in mind SiC devices where chosen.

Furthermore, these are all of the same package size to facilitate mounting on the same

heatsink.

5.2.2 Low power components

5.2.2.1 FPGA

As mentioned in Chapter 4 the FPGA used in the project is an Altera Cyclone IV housed

on the DE0-Nano development board. It was chosen to facilitate later integration with

the previously built frequency converter which uses the same board.

5.2.2.2 ADC

An analog-to-digital converter is necessary to sample the required signals for use in

the control-loops. In this project an AD7656-1 from Analog Devices is used which is

capable of simultaneously sampling six different channels at 250 kS/s (kilosample/s).

The sampled 16-bit data is sent to the FPGA via serial interface.

5.2.2.3 Gate Drive

The FPGA output pins do not have sufficient voltage or power to drive the large power

transistors used in the converter. To interface with and protect the control circuitry

gate drivers are used. The chips contain isolated DC-DC converters boosting the control

signal to a level suitable for driving the switches. Another reason for the isolation is the

fact that the buck switch is at a potential much higher than that of the FPGA.

On the output of each gate driver is an NPN/PNP transistor pair responsible for buffer-

ing the driver output current. Large power transistors have higher gate capacitance and

supplying a higher drive current leads to lower switching losses. On the other hand,

when driving large inductive loads such as in the buck converter, faster switching leads

to higher voltage spikes in the inductor. These could potentially damage the switch and

surrounding circuitry.

PCB design 43

5.2.2.4 Voltage sensors

Resistive dividers are used to convert the rectifier, bus and output voltage down to a

level appropriate for interfacing with the ADC.

5.2.2.5 Current sensors

Three current sensors are employed on the board. One measures the output current

whereas the other two measure buck inductor current and boost switch current. Most

important is the output current since it is used in the boost stage control loop. Sensing

the output current also enables the implementation of current-limiting the output. The

sensors also provide isolation from the high current paths and convert the sensed current

into a voltage signal.

5.2.2.6 OP-amp buffers

Two quad operational amplifiers are used to buffer all the sensor signals. This provides a

low impedance source for the ADC. Two of the OP-amp outputs are also used as buffers

for the signals going from the FPGA to the gate drivers. Should any sensor or drive

signal chain fail and impose large voltages or currents in the copper paths the OP-amp

buffers also provide a degree of isolation.

5.2.2.7 Auxiliary power supply

To allow the low voltage electronics to operate without having to connect additional

cables apart from the three-phase mains a power supply connected to the 800V bus

voltage is used. The main converter is of a flyback topology stepping down the voltage

to 24 V. Since the transformer in the reference design used is not available two standard

transformers were connected with their windings in series.

The lower voltage is further stepped down with buck converters and one LDO regulator

to 15, 12, 5 and -5V respectively. Negative voltage is needed for the ADC.

PCB design 44

5.2.2.8 Isolated PC interface

Since the whole board is not isolated connecting to a PC via serial interface could cause

serious damage. The serial interface is therefore isolated to enable communication with

the FPGA.

5.2.2.9 Small parallel rectifier

There are two three-phase rectifiers on the board. One is responsible for the main power

processing while the other is used to extract the rectified voltage AC-waveform. The

latter is connected to a resistive divider and a DC-block capacitor which feeds the ADC

the required signal for use in the control loop.

Chapter 6

Evaluation

This chapter details all the tests done and a brief explanation of equipment used during

testing.

6.1 Equipment

Equipment Description

Terco MV1300 Powerpack Three-phase power supply with fixed/-variable 230/133 V output and 10 A perphase

Terco MV1100 Load resistor Fan-cooled load resistor capable of sink-ing 3.3 kW

Fluke 43 Power Quality Analyzer Digital multimeter capable of directlymeasuring power factor and THD forsingle- and three-phase systems

FLIR TG165 IR-thermometer and camera

Table 6.1: Test equipment

Table 6.1 provides information about the equipment used during testing. Apart from

the equipment listed in the table, several different multimeters, oscilloscopes and power

supplies were used. Furthermore, a PC with Quartus II, MATLAB, the PC interface

and a variety of cabling was used.

45

Evaluation 46

6.2 Low voltage testing

6.2.1 Test 1: Aux PSU

The first test was to verify that the transformer-isolated DC/DC converter responsible

for 800 V to 24 V conversion worked. Since no 0 ohm resistors had been added to the

PCB in order to separate voltage domains for the purpose of testing, a separate board

was soldered together. This board had the same output configuration as the one on

the main PCB and wires were drawn from the main PCB to the board. After applying

31 volts to the testpoints on the main PCB the voltage was measured to be 24.6 V on

the output of the converter. The expected output was 24 V but an error of 0.6 V was

considered acceptable.

With the main upstream converter working components were soldered back to the board.

Then voltage was applied to the testpoints once again in order to verify function of all

downstream DC/DC converters. All smaller converters gave the right voltage with very

minor errors and some ringing on the -5 V supply. Ringing is common when using

charge-pump type converters.

6.2.2 Test 2: FPGA, ADC and gate-drive function

This test was done mainly to see that the code written for reading from the ADC worked.

The code worked perfectly on the first try.

After this test a dummy signal was sent to the output of the PWM-module. The dummy

signal was supposed to give a 40 kHz square wave with 50% duty cycle. From the output

of the OP-amps used for level-shifting only a triangle wave could be seen. Evidently

the OP-amps in question did not have a high enough slew rate and faster ones with

the same footprint were ordered. After switching out the OP-amp for a faster one the

square wave appeared as it should with a nice shape even at 120 kHz.

One thing discovered during the testing was that the current sensors used had a 2.5 V

bias. This was missed by the designer of the board but did not pose a big problem.

Code was written that constructs a mean value of 218 samples during start-up when no

current flows in any sensor. This is then subtracted from any new values read by the

Evaluation 47

ADC. The code worked but still a small error appeared in the value sent to the rest of

the system. After investigating the voltage applied to the ADC input it was shown that

a small ringing occurs every time the ADC takes a new sample. ADCs often have a

capacitor in the input stage and OP-amps do not do well driving capacitive loads. This

could be the source of the small error. A solution to the problem is to insert a small

resistor in the range of 20-200 ohms between the OP-amp and the ADC input. However,

due to the routing of the board this was not possible to do post production.

6.2.3 Buck converter control-loop

With 31 V connected to the testpoints the buck-converter control loop was tested. A

command was sent from the PC-interface to the FPGA to slowly ramp up the output

voltage in steps of 1 V. The controller performed as it should and differences in speed

could be seen clearly when changing parameters such as Kp and Ki. One thing changed

in code after the test was made to handle the fact that the error voltage could become

negative.

Another thing discovered during the tests was that even with Ki at zero there was still

some form of regulator wind-up. The precise reasons why are unknown and more tests

have to be conducted on the matter.

6.3 High voltage testing

6.3.1 Test 1: Soft-start circuit

The first thing to endure any high voltages or currents is the soft-start circuit. Thus,

this circuit was tested first without engaging either the boost- or buck-stages. After

connecting necessary cabling the main power was connected, applying 400/230 V to the

system. All status leds on the board lit up indicating that the Aux PSU was working at

a voltage of at least 565 V. 565 V is the peak voltage obtained from the input rectifier

when the boost-stage is off.

After disconnecting the power cord the board status LEDs were still on. This is due to

the bus capacitors still containing charge after having voltage applied to them. A feature

Evaluation 48

on the board not thought of by the designer was that the auxiliary PSU drained the

capacitors after pulling the power cord. This provides a measure of safety even though

the board was still live for around 30 seconds after power was cut.

6.3.2 Test 2: Buck converter with 230/133 V input

After concluding that the soft-start circuit was operational the buck output stage was

tested. The boost function was left off and a power box supplying 230/133 three-phase

power was connected to the input. When the soft-start circuit disengaged the output

voltage was slowly ramped up using the PC interface. The static error was a constant

0.8 V regardless of output voltage.

Maximum output voltage that was tested in this test was 280 V. This is the DC compo-

nent of the rectified input voltage. At 7.5 A of output current this results in an output

power of 2.1 kW.

6.3.3 Test 3: Buck converter with 400/230 V input

After testing the buck converter with 230/133 V input, 400/230 V mains was connected

to the board. This was to test the buck converter at higher output voltages that are

also in the range of the desired ones. A maximum of 490 V output can be obtained with

400/230 V input and no boost function engaged.

At the higher input voltage it seemed that the static error of the regulator increased to

about 1.8 V. Moreover, when attempting to go above 400 V e.g. 402 V the regulator

did not stop at the desired voltage and instead kept going. This is despite only the P

part of the PI regulator being used.

6.3.4 Test 4: Full system test with boost engaged, 400/230 V input

The last test was supposed to have shown whether the boost function and its control

loop functioned properly. Before starting this test the system was once again connected

to mains in order to ensure everything else was in order. When connecting the mains

nothing on the board lit up and mains once disconnected.

Evaluation 49

After probing the board with a multimeter it was discovered that both diode pairs in

the input rectifier for phases B and C were broken. Furthermore, the boost diode was

also broken. This suggests that the soft-start circuit had malfunctioned during start-up.

Power was also connected to the 800 V test-points to see if the rest of the system was

still functioning. The board lit up but as soon as the relay closed it short-circuited.

Everything else turned off and the problem is either that the external power supply

current limit turned on or the 24 and 12 V converters have also broken.

New diodes, relays and other components for the 24 and 12 V converters were ordered

the next day.

6.3.5 Test 5: Soft-start with higher delay

Because the diodes in phases B and C as well as the boost diode was broken, when the

relay closed, the test points for 800 V were short circuited. This was the cause of the

system shutting down.

The damaged components were replaced with more powerful and in some cases less

expensive versions. Furthermore, the amount of time that the soft-start circuit is active

was doubled. At first the active time was 10 seconds which equates to 5 time-constants

for the RC-circuit which is formed by the soft-start resistors and the bus capacitors.

According to calculations this should be more than enough but in reality there was still

a considerable gap between the current and final voltages when the relay closed. The

remaining charge needed for the capacitors to attain their final value probably caused a

large enough inrush current to damage the diodes. With a soft-start time of 20 seconds

the circuit worked without any problems.

Apart from the soft-start circuit nothing else seemed to have broken on the board.

However, the previous system failure had tripped the circuit breakers protecting the

lab. After rectifying this problem a local circuit breaker and residual-current device was

installed to further protect both the user and mains network.

Evaluation 50

6.3.6 Test 6: Full system test, no harmonic injection

With the soft-start working again the buck converter was tested again without engaging

the boost stage. The output voltage was taken up to 401.6 V with an output current of

3.12 A resulting in an output power of 1.25 kW. Using the power quality analyzer the

recorded power factor was 0.54 with a THD of 85.5%. These measurements were made

to provide a comparison between power quality with and without PFC function.

After engaging the boost stage the output voltage was slowly ramped up in order to

ensure that the variable gain controller did in fact function properly. Moreover, no

harmonic injection was activated at the time. This was also done in order to provide

a reference for system performance with and without harmonic injection. It seemed to

apply too much gain too early and the output current read by the ADC was a bit higher

than the actual value. The system was powered down and the scaling was changed to

provide a value closer to the real one. Furthermore, the overall gain in the variable gain

controller was halved to ensure no excessive voltages were applied in the system.

With the software changes made, the system was powered up and the output voltage

and current slowly ramped up. Output voltage was ramped up to 401.6 V again and

the current to 3.3 A indicating an output power of 1.33 kW. The newly made changes

resulted in a boost stage output voltage of 711 V over the recorded range of output

power.

With the boost engaged and no harmonic injection the power factor had increased to 0.88

and THD decreased to 38.7%. When looking at the power quality analyzer the inductor

current showed signs of entering CCM in parts of the mains period. This is undesirable

in this type of system and causes a degradation of power quality. It is probable that

power quality would have increased even more had the boost output voltage been at the

desired 800 V.

Some time during operation the multimeter used for measuring output current started

to show nonsensical readings. When going past the first range of 0-3 A on the screen it

fluctuated between the 0-3 and 0-10 A ranges. It was assumed that the output current

needed to be increased a little to make the multimeter stay in the higher range and show

the correct value. The load resistance was decreased a little but the multimeter readings

Evaluation 51

showed no signs of improvement. After some time without changing any operational

parameters the current sensor in line with the boost transistor exploded.

The reason for this fault is unknown and if any arcing between device legs took place

this should have happened earlier as the boost output voltage stayed at 711 V the entire

time. For the current sensor to explode in such a fashion there had to have been a

massive surge in current since it only provides a resistance of 1 mΩ. Other reasons

could be a software error or simply a faulty component.

6.4 Test 7

After repairing the board again and optimizing some of the software the board was

tested with low voltage to ensure proper functionality before connecting to the mains

network. It was discovered that the variable gain regulator gave its maximum duty cycle

even with no output voltage or current present. After troubleshooting the root cause

seemed to be the ADC not providing the proper values to the FPGA. All inputs gave

-5 V on the digital side even though the measured analog values were correct.

Due to time constraints it was decided that the project be put on hold and any further

experiments would be done at a later time, if at all.

Chapter 7

Result and discussion

Looking at simulation results the system performed quite well. As mentioned in Sec-

tion 2.4.2 the proposed circuit achieves power factor correction with harmonics well

within the IEC limits. This is with or without harmonic injection and these limits

start to matter more when higher output power is desired. Voltage regulation for both

the boost- and buck stages were satisfactory even though the boost controller could be

improved given more time.

The proposed control system detailed in chapter 3 seemed to work although not quite

with desired level of performance. After some software modifications the system was

run at a voltage somewhat lower than desired. The system showed that there was a

definitive improvement in power factor and THD. Had the system worked as intended

the improvement would probably have been even bigger.

An interesting thing to note is that in simulation the buck converter required a PI

controller to achieve the correct output voltage. When testing the system only a P type

controller was required and it gave only a slight static error which can be considered

negligible in relation to the high output voltages. However, the controller started to

behave erratically when pushing the output voltage higher than 400 V. This could lead

to potentially dangerous component failures such as exploding capacitors and this needs

to be corrected if there is a future version to be built.

The reason for the exploding current sensor is still unknown. If the ADC was damaged

before the test it could potentially have led to the system providing faulty control signals

resulting in catastrophic failure.

52

Chapter 8

Improvements

Apart from making sure the system works there are some improvements that can be

made.

When looking at the input filter the configuration and capacitor values were chosen due

to satisfactory function in simulation. However, depending on the environment that the

system is to be used in, different regulations apply. These impose different restrictions

on filtering and would need to be studied in order to construct the appropriate filter.

The boost stage could have its drive circuitry switched to a two-level solution [6]. This

means that two transistors are used in the boost converter and each transistor regu-

lates the voltage over each of the two bus capacitors. With a two-level solution the

voltage balancing of the capacitors is built in and as such no balancing resistors are

needed and efficiency is increased. Furthermore, due do the two-level topology smaller

semiconductors with lower RDSon can be used. This also increases efficiency and other

semiconductors can be reduced in size as well. A smaller footprint increases power

density and lowers component and production costs.

To enable full output power at all output voltages would require a very large inductor

in the buck output stage. On the other hand, the inductor can be split in two with one

inductor in the positive end and one in the negative. The resulting output stage would

still be quite large but would also reduce common mode currents as well as peak and

ripple currents. Depending on the application the output stage could also be transformer

isolated.

53

Chapter 9

Conclusion

This project dealt with power factor correction for use with a frequency converter.

Originally several different topologies were to be investigated and tested. Due to the

time and complexity involved in designing direct three-phase PFC systems only one was

simulated and built.

The chosen system is one of the simpler active PFC circuits. Compared to more advanced

systems the performance is not quite as good but cost and complexity is much lower.

Even though it is not a state of the art system it is still an enormous improvement

compared to not having any PFC at all.

In simulation a minimum of 99% power factor was observed which is in line with the

desired values. THD also showed an improvement when implementing the harmonic

injection described in Section 2.4.2. While tests of the system did not provide the desired

values most parts still worked fairly satisfactory and also showed an improvement over

using no PFC at all. The look-up table used in the variable gain controller could be

extended to include more values with less of a step between them. This would results

in a smoother curve more reminiscent of the one obtained in MATLAB.

54

Appendix A

Formulae

A.1 Critical power

The steady-state analysis is the basis of design for any converter. In [2] the analysis of

several converters is presented. For this thesis an AC/DC boost converter front-end is

considered but results from the DC/DC version can still be used in analysis. Since the

conversion factors differ between conduction modes it is important to know how they

are related.

Figure A.1: DC/DC boost converter

In the boundary conduction mode (CrCM) the converter can be said to deliver the

critical power Pc. Po is the power delivered in any of the modes and d is the duty cycle.

Looking at the inductor waveform in the boundary conduction mode this limit can be

55

Appendix B 56

calculated. Even though the converter is in CrCM it can still be said to operate in CCM

giving the relationship between input current Iin, duty cycle D and switching frequency

fs in A.1 where ip is the peak current:

Iin =1

2ip =

VinD

2Lfs(A.1)

Due to the CrCM/CCM operation the input and output relations are as in equation

A.2.

Vin =