DC FEM FDR

Charles E. PancakeThomas K. HemmickJulia VelkovskaVlad Pantuev

ASD/TMC Card

•The ASD/TMC card has two sections (Analog and Digital) which are isolated using moted grounds and communicate via differential discriminator signals.

•The Analog section has as its primary functions the amplification, shaping, and discrimination of the small charge signals from the wires.

•The Digital section has as its primary functions the time digitization, trigger latency, and multiple event FIFO (5 event stack) required for all PHENIX electronic systems.

ASD/TMC Analog

•The Analog section is implemented mostly in a single ASIC, the ASD8 or “Penn Chip”.

•ASD= Amplifier, Shaper (6 nsec), Discriminator (individually settable) in a package of 8 channels.

•The ASD’s feature fully differential inputs and outputs.

•Sufficient DAC channels are provided on the ASD/TMC board to supply every channel’s threshold individually.

• The DACs are set via ARCNet.

•The ASD grounding and power distribution are critical to ensuring low noise operation (see next slide).

•The Analog section additionally has the ability to supply a pulse to the chamber.

ASD/TMC Digital

•The Digital section is primarily implemented using a monolithic ASIC, the TMC designed by Yasuo Arai.

•The TMC’s receive the differential discriminator outputs of the ASD8’s.

•The TMC uses an internal 256-deep dual-port memory (DPM) clocked by the 4X clock to provide latency (~6.4 sec).

•During normal operation, the DPM runs continuously, thereby keeping a time history.

•Trigger application causes a region of the memory to be copied to an output FIFO pending “ENDat” requests for transmission to DCM.

TMC operation: Memory Contents

•Each cell in the DPM is 10 bits wide and records data from two ~13 nsec “time bins”.

•Hit times in any time bin are recorded to a precision of 0.8 nsec.

•Both of these criteria exceed by better than a factor of two the requirements.

•The TMC is not the limiting factor in detector performance.

TMC Output FIFO

•Upon receipt of a trigger, the TMC copies the contents of the “Write Pointer” into a TFIFO.

•Two TMC registers (“OFFSET”, “DEPTH”) control the readout as follows:

•The read pointer is initialized toTFIFO - OFFSET.

•DEPTH words are copied into the output FIFO pending readout.

•The output FIFO is deep enough so that >5 events can be stored and read out in the order they were triggered.

FEM Card

•The FEM card acts as the interface of the ASD/TMC card to the slow controls, timing control, and data output stream of the PHENIX DAQ.

•Slow controls are implemented via an ARCNet daughter card as designed by J. Fried of BNL.

•Timing inputs and Data outputs are carried over fiber using the BNL-designed Glink receiver and transmitter daughter cards (F. Heistermann).

•Data output is sent over 2 fibers on Day N and one fiber on Day 1.

•The Heap manager implements the data collection cycle.

ARCNet in DCFEM

•The DC FEM has connectors which accept a BNL-design ARCNet daughter card which is the source of slow-controls.

•The BNL-supplied code (Fried) supplies to all users the following:

•Simple in/out parallel and serial commands.

•Software hooks for new commands.

•The Drift Chamber requires an enhanced set of commands to individually address more than 350 CSRs.

•The ARCNet board is assisted by a small FPGA used for address decoding.

Timing Input

•The Timing Glink supplies clocks, trigger, EnDats, and mode bits to the FEM.

•We have added the ability to run the DC FEM without the Timing Glink.

•The 4X clock can be generated by an onboard crystal.

•The user may assert triggers and ENDats asynchronously from an external input.

•After the external trigger is synched with the local clock a “trigger applied” output is generated to inform the user of the trigger delay.

DATA Output

•PHENIX has globally set the standard for total time necessary to transmit one event at 40 sec.

•Data from one FEM consists of two 972 word transmissions, each of which contains a header, time-data, and a trailer.

•Including transmission setup, one FEM transmission takes ~26 microseconds, well within PHENIX spec.

•Each TMC reports only 10 bits per clock cycle, thus, we read 2 TMCs per clock.

•These two streams are input to a bank of 10-bit FIFOs.

•The FIFOs serve to sort the data from the two TMCs into a separate 20-bit output streams.

DC/DCM Data Format

Sequence 20 bit format CAV DAV

1 all bits “ON” on off2 Detector ID (loaded from ArcNet) off on3 Event Number (16 bit internal counter) off on4 Module Address (loaded from ArcNet) off on5 Flag Word (loaded from ArcNet) off on6 FEM BeamCount (8 bit BeamClk Ctr.) off on7 ASD/TMC bd. 1(or 3), Ch. 0, Words 1, 2 off on --------------------------------------------------------------18 ASD/TMC bd. 1(or 3), Ch. 0, Words 11, 12 off on19 ASD/TMC bd. 2(or 4), Ch. 0, Words 1, 2 off on --------------------------------------------------------------30 ASD/TMC bd. 2(or 4), Ch. 0, Words 11, 12 off on31 ASD/TMC bd. 1(or 3), Ch. 1, Words 1, 2 off on --------------------------------------------------------------42 ASD/TMC bd. 1(or 3), Ch. 1, Words 11, 12 off on --------------------------------------------------------------966 ASD/TMC bd. 1(or 3), Ch. 39, Words 11, 12 off on967 User Word #1 (loaded from ArcNet) off on968 User Word #2 (loaded from ArcNet) off on969 User Word #3 (status word) off on970 User Word #4 (all bits “OFF”) off on971 Parity Word ( XOR of seq. 2 - 971) off on972 all bits “OFF” on off

HeapMgr CSRs (1)

Status1 Register 00 (Read only)

00 -- Endat[0] Error01 -- Endat[1] Error02 -- TMC Error 03 -- Rx Link Error Latched04 -- Tx0 Lock Error (reset via RstCtrl[6])

05 -- Tx1 Lock Error 06 -- 5Event Error07 -- Run/Halt

Status2 Register 01 (Read only)

00 -- TMC Error (Board 1)01 -- TMC Error (Board 2)02 -- TMC Error (Board 3)03 -- TMC Error (Board 4)04 -- LSB05 -- -- 5Event Ctr.06 -- MSB07 -- Spare

HeapMgr CSRs (2)

RstCtrl Register 02 (Read/Write)

00 -- Spare01 -- Rx Reset (R/W)02 -- Tx0 Reset (R/W)03 -- Tx1 Reset (R/W)04 -- TMC Reset (R/W) 05 -- FIFO Reset (R/W) 06 -- Error Reset (R/W) 07 -- 5Event Reset (R/W)

GlinkCtrl Register 03 (Read/Write)

00 -- Tx0 ED (R/W)01 -- Tx1 ED (R/W)02 -- Tx0 Lock(Read only)03 -- Tx1 Lock(Read only)04 -- RxDAV (Read only)05 -- RxRdy (Read only)06 -- Spare07 -- Spare

HeapMgr CSRs (3)

TestCtrl Register 04 (Read/Write)

00 -- Trigger RxGlink[09] 01 -- Endat0 RxGlink[11] 02 -- Endat1 RxGlink[12] 03 -- UsrBit0 RxGlink[13] 04 -- UsrBit1 RxGlink[14] 05 -- UsrBit2 RxGlink[15]06 -- TimingEn RxGlink[10]07 -- TestMode

ModeBit Register 05 (Read/Write)

00 -- ModeBit[00] RxGlink[00]01 -- ModeBit[01] RxGlink[01]02 -- ModeBit[02] RxGlink[02]03 -- ModeBit[03] RxGlink[03]04 -- ModeBit[04] RxGlink[04] 05 -- ModeBit[05] RxGlink[05]06 -- ModeBit[06] RxGlink[06] 07 -- ModeBit[07] RxGlink[07]

HeapMgr CSRs (4)

LEDReg Register 06 (Read/Write)

00 -- LED[0] + Test Header HDR2[16] 01 -- LED[1] + Test Header HDR2[18] 02 -- LED[2] + Test Header HDR2[20] 03 -- LED[3] + Test Header HDR2[22] 04 -- LED[4] + Test Header HDR2[24] 05 -- LED[5] + Test Header HDR2[26] 06 -- Test Header HDR2[28] 07 -- Test Header HDR2[30]

Spare Register 07

ModuleAddress Register 08, Register 09, Register 0A

DetectorID Register 0B, Register 0C, Register 0D

FlagWord Register 0E, Register 0F, Register 10

UserWord1 Register 11, Register 12, Register 13

UserWord2 Register 14, Register 15, Register 16

Mode Bits (1)

ModeBit Reset Group:Bit[01] Bit[00] 0 0 NoOp 0 1 ReSync 1 0 FIFO Reset 1 1 NoOp

ModeBit Pulse Group:Bit[03] Bit[02] 0 0 NoOp 0 1 Pulse Board 1 0 Pulse All 1 1 NoOp

In Pulse Board mode, ModeBit[05]and ModeBit[06] are used to specifywhich board to pulse.

Mode Bits (2)

ModeBit[04]: Bit[04] 0 Halt 1 Run - enable timing

on all TMCs. EnableBeamCtr.

TestPulse Decode:Bit[06] Bit[05] 0 0 Board 1 0 1 Board 2 1 0 Board 3 1 1 Board 4

ModeBit[7]: Not implemented

FEM FPGAs

HeapMgr - 2, Altera, EPF8118AQC240-21. Primary state machines, FIFO/TMC control logic, test logic, ArcNet interface. 71% usage - 48 MHz simulation2. Data flow pipeline registers, Event Ctr., Trigger logic, Beam crossing counter and registers. 45% usage - 45 MHz simulation.

ArcNet Decoder - 1, Altera, EPM7128QC100-15

80% usage.

Tests Performed-1

Noise-related Tests:

•The analog section of the ASD/TMC card has been tested thoroughly on chamber using an earlier prototype board.

•Cosmic rays are measured with high efficiency (>99% per wire) and high resolution (<150 m).

•The full board (analog and digital has been tested on bench for clock pickup:

•TMC clock: Invisible until 2 fC.

•Readout Cycle: Invisible until 3-4 fC.

•The full board was tested on a non-functioning chamber to be operate noise-free w/ 3-5 fC thresholds.

•These results are within spec.

Tests Performed-2

•Noise with linear and switching supplies.

•Triggering system up to 25 kHz.

•All ARCNet functions tested.

•DPM tested via “pre-load” with known data (ALSO tests the sorting FIFOs).

•Chain Test to DCM.

•Triggers and ENDats supplied by GTM over fiber.

•Threshold curves measured using PDAQ data acquisition system.

•Electronics presently on chamber for cosmics.

ASD/TMC Status(after 2 prototype runs)

• TMC Differential Clock Input - could not accept differential PECL levels.• TMC “No Header” Function - not working … TMC header words eliminated by HeapMgr.• TMC “End of Data Detector” affected by excessive input noise - vdd rasied to 3.8V. Replaced fixed regulators with adjustable LDO regulators.• TMC “DPM Error Circuit” - 1.5% error rate for random triggers. Added clock to RPUP (test pin).• Vias too close to adjustable regulators.• Vias for DAC control signals shorted - wrong footprint used.• TMC output buffer latch wired in pass-through mode.Next prototype run = 30 boards.

FEM Status(after 1 prototype run)

• Add pullup resistors to FIFO REN* (read enable)• Add pullup resistors to Glink Receiver RxReady* and RxDAV*• ArcNet connector pinouts reversed.• HeapMgrRst wiring error - pervented reloading the HeapMge FPGA code on “software reset”.• Add additional mounting holes.

Next prototype run = 10 boards

SUMMARY

•The design of the DC FEE is complete.

•Tests of prototype have been dominated by “typical” errors, all of which seem to be fixed.

•Designs are up-to-date with all known fixes applied.

•Troubles have centered on the TMC chip, but seem to be bypassed.

•Chamber tests with one fully instrumented keystone looking at cosmic rays will be used as the last round verification of the design.

•Cooling needs to be addressed more thoroughly, but conceptual designs look OK.