De 2 Logic Gate Comparison

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Digital Logic Families

Gates perform one or more operations. simply electronic circuits composed of resistors, diodes

and transistors

Originally gates were composed just from resistors anddiodes, due to expense of transistors.

Due to fabrication procedures, all gates are nowconstructed exclusively from transistors.

The style in which transistors are connectedcharacterises each logic familyor libraryand

gives it its unique name.


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DIGITAL LOGIC FAMILIES

Integrated Injection Logic (I2L)

standard I2

L Schottky I2L

Schottky Transistor I2L

NMOS

CMOS Logic

standard CMOS

4000 Series CMOS Logic Family 4000B and 74C Series

74HC/HCT Series

74AC/ACT Series

BiCMOS


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Metrics for Logic Gate Comparison

How do you compare these differentlogic families ?

Comparison on the application ?

Comparison on the cost ?

Any other ?


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Metrics for Logic Gate Comparison

Before a discussion of the basic logicfamilies, several metrics must bedefined to allow comparison of

different families.


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Metrics for Comparing Logic

Families Logic Level

Noise Margin

Fan out

Power Dissipation

Propagation Delay


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METRIC 1: Logic Levels

Circuit behaviour explained very well in terms of voltagelevels measured in volts (V)

but not necessarily in terms of Boolean values 0 and 1.

To accommodate these Boolean values, gate circuits aredesigned in such a way that only two voltage levels, high (H) andlow (L) are observable in steady state at gate inputs and outputs.

Thus a mapping exists from 0 and 1 to voltage levels H and L.

Mapping can be accomplished in two different ways

Results in two different logic systems:

positiveand negative.


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Logic Levels

Example :

The gate circuit whose output is L only whenboth inputs are H

Performs the NAND operation in positive logic Performs the NOR operation in negative logic

Similarly gate circuit whose output is L onlywhenever one input is H Performs the NOR operation in positive logic

Performs the NAND operation in negative logic


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New Symbol

To distinguish between positive and negative logic

a small triangle as a polarity indicator for negative logic in anyinput and output signal line.

Negative logic NAND (positive logic NOR)

The mixing of logic levels was practised frequently in the

past when designers mixed gates from different logicfamilies on the same board.

Since the mid-eighties or so, all new ICs have been made withthe CMOS logic family, which uses positive logic.

Negative logic has fallen out of fashion.


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Noise Margin


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METRIC 2: Noise Margins

Gate circuits are constructed to sustain variationsin input and output voltage levels.

variations are usually result of several different factors.

1. Batteries lose their full potential, causing the supplyvoltage to drop

2. High operating temperatures may cause a drift in

transistor voltage and current characteristics

3. Spurious pulses may be introduced on signal lines bynormal surges of current in neighbouring supply lines.


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Noise Margins

All these undesirable voltage variations that aresuperimposed on normal operating voltage levels are

called noise.

All gates designed to tolerate a certain amount of noise ontheir input and output ports.

The maximum noise voltage level that is tolerated by agate is called a noise margin.

Noise margin derived from I/P

O/P voltage characteristic Measured under different operating conditions

Normally supplied in documentation about gate frommanufacturer.


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Noise Margins

Typical input/output voltage characteristic for (TTL) family

the output voltage is plotted as a function of the input voltage.

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Input Voltage, VI

OutputVoltage,VO


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Noise Margins

The input/output voltage characteristic drifts

under different operating conditions also showthe drifting range by the shaded area.

From the figure we can see that the given gateoperates in 3different modes

High output

Transition

Low output

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Input Voltage, VI

Output

Voltage,VO


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Noise Margins

High Mode :

When VI is between 0 and 0.8 V

the output voltage VO is greater than 2.4 V

and

less than the supply voltage VCC, which is usually 5.0 V.

i.e 2.4V< VO< 5.0V

Transition Mode :When VI is between 0.8 and 2.0 V

the gates switches from H to L


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0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Input Voltage, VI

Out

putVoltage,VO


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Noise Margins

Low Mode :

When VI is greater than 2.0 V

the output voltage VO is greater than 0 V

and less than 0.4 V.

i.e 0V< VO< 0.4V


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How to determine noise margins? Compare input and output voltage ranges of gates in same family.

output voltage range of a driving gate on LHS input voltage rangeof the driven gate on RHS

Any voltage between VOHand VCCis considered H.

any voltage between 0and VOL is considered L.

H H

L L

High Noise

margin

Low Noise

margin

VCC

(5.0) VCC (5.0)

VOH

(2.4)

VOL

(0.4)

VIL (0.8)

VIH

(2.0)

GND(0) GND

(0)

Input Voltage

range

Output Voltage

range


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How to determine noise margins?

Similarly

Any voltage between VIHand VCCis considered H Any voltage between 0and VIL is considered L

The voltage difference VOH- VIHcalled high-level

noise margin

Any noise voltage smaller than VOH- VIHwill be toleratedand will not change the output value of the driven gate.

For the same reason, the voltage difference VIL - VOLis called thelow-level noise margin.


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How to determine noise margins?

In the example of transistor-transistor logic (TTL):

VOH= 2.4 V

VIH= 2.0 V

VIL = 0.8 V

VOL = 0.4 V

Thus both high and low level noise margins are 0.4 V.

Thus any noise smaller than 0.4 V will not disturb gateoperation.

Such high noise margins, which are not available inanalog circuits, make digital designs superior to analog.


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Fan-Out


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METRIC 3: Fan-out

To date have understood that each gate can drive

several other gates.

The number of gates that each gate can drive, whileproviding voltage levels in the guaranteed range is

called the standard loador fan-out.

The fan-out really depends on the amount of electriccurrent a gate can source or sink while driving othergates.


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Fan-out

When the gate output is H

Gate behaves as a currentsource since IOHflows out

of the driver gate and intothe set of driven gates.

The current IOHequals the

sum of all input currentsindicated by IIH, flowing intothe driven gates.

IOH

IIH

IIH

IIH

to other gates


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Fan-out

When the gate output is L

Gate behaves as a currentsink since IOL flows into the

gate and out of the drivengates.

The current IOL is again

equal to the sum of all inputcurrents IIL, flowing out of allthe driven gates.

IOL

IIL

IIL

IIL

to other gates


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Fan-out

Since all gates in a logic family are constructed in

such a way that each gate requires the same IIHandthe same IIL,

can compute fan-out in the following way:

)fanoutoutputLLogicfanout,outputHLogicmax(

,max_

IL

OL

IH

OH

I

I

I

IoutFan


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Fan-out

Example

Input and output current for the transistor-transistorlogic (TTL) family are the following:

IOH= 400AIOL = 16AIIH= 40AIIL = 1.6A

Therefore the fan-out is ?


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Fan-out

This means that each gate can drive 10 other gates in

the same family without getting out of its guaranteed range of operation.

In cases where more than 10 gates are connected to

the output of a single gate of this family, the outputvoltage levels will degrade and the gate will slowdown.

Modern MOS logic families have a fan-out of about 50, since each gate must source or sink a current only during the

transition from H to L or L to H.


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Power Dissipation


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Metric 4: Power Dissipation

Each gate is connected to a power supply VCC

Draws a certain amount of current during its operation.

Since each gate can be in a High state, Transition orLow state.

can distinguish 3 different currents drawn from power supply.

ICCH

ICCT

ICCL


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TTL

In some older logic families, such as TTL, the transition

current ICCT is negligible in comparison to ICCHand ICCL.

Assuming that gate spends an approximately equal amount oftime in the high and the low states and approximately no time in

the transition state

Thus the average power dissipation(product of average current

and power supply voltage)

Power dissipation is measured in mW

for the TTL family 10mW

2CurrentAverage

CCLCCHII

2Paverage

CCLCCH

CC

IIV


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CMOS

In more modern technologies such as the CMOS family

the steady-state currents ICCHand ICCL are negligible

in comparison with ICCT.

Since ICCTis relatively small the typical power

dissipation of CMOS gates is small.

But the power dissipation increases with the frequency withwhich the gate output is changing

CCTCC IV Paverage


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Power Dissipation

Power Dissipation is an important metric for two

reasons.

1. Amount of current and power available in a battery is nearlyconstant.

power dissipation of a circuit or system defines battery life.

The greater the power dissipation, the shorter the battery life.

2. Power dissipation is proportional to the heat generated by thechip or system.

Excessive heat dissipation may increase operatingtemperature and cause gate circuitry to drift out of its normaloperating range

will cause gates to generate improper output values.

Thus power dissipation of any gate implementationmust be ke t as low as ossible


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Propagation Delay


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Metric 5 Propagation Delay

Propagation delay definedas:

Average time needed for

an input change topropagate to the output

Typically nanoseconds.

The propagation delay canbe obtained from gateinput and outputwaveforms.

90%

90%

10%

50%

10%

50%

Input

Output

Rise

timeFall

time

tPHL

tPLH


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Propagation Delay

1. Input and consequently output signal do not switch theirvalues instantly

2. H L and L Hchanges can be delayed for differentamounts of time

Since the signal values do not change instantly, define risetime

delay for a signal to switch from 10% to 90% of its nominalvalue.

Similarly define the fall time. delay for a signal to switch from 90% to 10% of its nominal

value.


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Propagation Delay

Since H L and L Htransitions are not delayed equally, candefine

tPHL H L propagation delaytPLH L Hpropagation delay

tPHL is defined as

time necessary for output signal to reach 50% of its nominal value onHL transition after input signal reached 50% of its nominal value.

tPLH is defined similarly.

Propagation delay tPdefined as average value of tPHL and tPHL.

2

PLHPHL

P

ttt


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Propagation Delay

2-input NAND in the TTL family

tPHL = 7 nsectPLH= 11 nsec tp= 9 nsec (7+11/2)

2-input NAND in the CMOS family tp= 1 nsec

As manufacturers cannot guarantee the same nominalvalue on every gate they fabricate

Usually give the maximum delay values (not thatinterested in the minimum delay) no gate will exceed this maximal value.

2-input NAND in the TTL family, the maximalpropagation delaystPHL = 22 nsec

tPLH= 15 nsec

tp= 18.5 nsec (22+15/2)


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Summary

Need to have metrics to allow DigitalDesigners compare different designs.

So either the cost effective or fastestdesign can be implemented for each

application.

Lecture tonight

Date post:	06-Apr-2018
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De 2 Logic Gate Comparison

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