Dealing with HazardsMite 3

Ellen Spertus

MCS 111

November 13, 2003

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Review: Hazards

• What’s a control hazard?

• What’s a data hazard?

Stages– IF– ID(RR)– EX– MEM– WB

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Sample code

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

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Interpreting the diagram

• Time axis

• Instruction axis

• Stages

• What does it mean when– a colored line goes to the right?– a colored line goes straight down?– a colored line goes to the left?

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How can we run sample code?

• Inserting nops (“no operation”s)– sll $0, $0, 0–

• Adding new datapaths to speed value to where it is needed

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sub $2,$1,$3and $12,$2,$5

$5

$2

25

lw $5, 3($0)

Figure 6.43 (p. 488)

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Summary: Forwarding

• Hazards that forwarding can solve

• Hazards that can’t be solved by forwarding

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Hazard requiring stalling

Figure 6.44 (p. 489)

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What should happen on a stall?

• Instructions further through the pipeline should keep going

• The stalled instruction should stay at the same stage

• Instructions earlier in the pipeline should

11From Figure 6.47 (p. 493)

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Dealing with hazards

• Data hazards– Reordering code– Forwarding or bypassing– Stalling

• Control hazards

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Control hazards

Reg

Reg

CC 1

Time (in clock cycles)

40 beq $1, $3, 7

Programexecutionorder(in instructions)

IM Reg

IM DM

IM DM

IM DM

DM

DM Reg

Reg Reg

Reg

Reg

RegIM

44 and $12, $2, $5

48 or $13, $6, $2

52 add $14, $2, $2

72 lw $4, 50($7)

CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9

Reg

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Dealing with control hazards

• Add hardware to determine earlier whether a branch is taken

• Static prediction– Assume branch not taken– Assume branch taken

• Dynamic prediction

• Branch delay slots

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Branch delay slots

b = c + d;

if (a == 0) ...

add $s1, $s2, $s3

beq $s0, $r0, foo

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Mite 3

• Add conditional branch• New instruction format:

• LS163 functionality– reset– enable (count)– load

Format i7 i6 i5 i4 i3 i2 i1 i0 Meaning ALU 0 f3 f2 f1 f0 c’ m LD0 Perform the specified ALU function CONST 1 0 c4 c3 c2 c1 c0 LD0 Load the sign-extension of c4..c0 BEQ 1 1 b5 b4 b3 b2 b1 b0 If a=b, jump to the address in b5..b0

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LS163: 4-bit synchronous counter

• If reset’, set outputs (Q3..Q1) to zero

• If load’, set outputs to inputs (P3..P1)

• If enable and Cin, increment outputs

enable

Cin

load'

reset'

P3 P0P2 P1

Q3 Q0Q2 Q1

Cout

1

2

7

6 5 4 3

9

10

1411 12 13

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LS163counter

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Lab 6

• Design (pages 1-3) due at beginning of class Thursday, Nov. 20.

• Lab due 5 PM, Tuesday, Dec. 2.

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