DecodersBCD/DEC
0123456789
1248
74HC42
(11)(10)(9)(7)(6)(5)(4)(3)(2)(1)
(15)(14)(13)(12)
A1
A0
A2
A3
Assume the inputs to the 74HC42 decoder are the sequence 0101, 0110, 0011, and 0010. Describe the output.
All lines are HIGH except for one active output, which is LOW. The active outputs are 5, 6, 3, and 2 in that order.
This decoder is a BCD-to-seven segment display with active LOW outputs.
LogicLogicDiagram
BCD-to-7-segement decoder
BCD-to-7-segement decoder
TruthTruthTable
BCD Decoder/DriverThe 74LS47 is a BCD-to-seven segment display with active LOW outputs.
The a-g outputs are designed for much higher current than most devices (hence the word driver in the name).
abcdefg
1248
(16)
(4)
(13)(12)(11)(10)(9)
(15)(14)
(1)(2)(6)
(7)
(3)(5)
(8)
BCD inputs
Outputs to seven segment device
GND
VCC
BCD/7-segBI/RBO BI/RBO
LTRBI
LT
RBI
74LS47
BCD Decoder/DriverHere the 7447A is an connected to an LED seven segment display. Notice the current limiting resistors, required to prevent overdriving the LED display.
VCC
GND
+5.0 V
+5.0 V
R's =330 �
abcdefg
abcdefg
MAN7274LS47
LTBI/RBORBI
1.0 k�
1
1 22
3, 9, 143456
7
7
8
8
9
1010
11
1112 1313
1415
16BCD/7-seg
BCDinput
DCBA
Leading Zero SuppressionThe 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBIinput of the next decoder.
Trailing Zero SuppressionTrailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBIinput is connected to the BI/RBO output of the following decoder.
EncodersAn encoder accepts an active logic level on one of its inputs and converts it to a coded output, such as BCD or binary. Decimal-to-BCD encoder
Encoders
The decimal to BCD is an encoder with an input for each of the ten decimal digits and four outputs that represent the BCD code for the active digit. The basic logic diagram is shown. There is no zero input because the outputs are all LOW when the input is zero.
A3=8+9A2=4+5+6+7A1=2+3+6+7A0=1+3+5+7+9
Encoders
A1
A0
A2
A3
Show how the decimal-to-BCD encoder converts the decimal number 3 into a BCD 0011.The top two OR gates have ones as indicated with the red lines. Thus the output is 0011.
1
2
3
45678
9
0
0
0
000
0
0
1
0
0
1
1
EncodersThe 74HC147 is an example of an IC encoder. It is has ten active-LOW inputs and converts the active input to an active-LOW BCD output.
This device is a priority encoder. This means that if more than one input is active, the component responds to the highest numbered input.
EncodersThe 74HC148 Octal-to-Binary Encoder
An Encoder Application
A keypad encoder
Code converters
There are various code converters that change one code to another. The first example is the BCD-to-binary conversion.
BCD-to-Binary Conversion
1000 01118 7
Code convertersConvert the BCD numbers 00100111 (decimal 27) to binary.
001001110000001 10000010 20000100 4
+0010100 200011011 Binary number for decimal 27
Code convertersConvert the BCD numbers 10011000 (decimal 98) to binary.
100110000001000 80001010 10
+1010000 801100010 Binary number for decimal 98
Code convertersThere are various code converters that change one code to another. Two examples are the four bit binary-to-Gray converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
00
0
1
1
1
Binary-to-Gray Gray-to-BinaryMSB
LSB
MSB
LSB
1
0
0
0
1
0
0
1
1
1
MultiplexersA multiplexer (MUX) selects one of several data (D) inputs and routes data from that input to the output. The data line that is selected is determined by the select (S) inputs.
The multiplexer shown has two select (S) inputs that are used to select one of four data (D) inputs.
Which data line is selected if S1S0 = 10?
The select input (10) connects data line 2 to the output.
MUX
12
0
3
10Data
select
Data inputs
Data outputD1
D0
D2D3
S1
S01
0
Multiplexers (Data Selectors)
Y=D0S1S0Y=D1S1S0Y=D2S1S0Y=D3S1S0 Y=D0S1S0+D1S1S0+D2S1S0+D3S1S0
Here is the logic diagram for a 4-input multiplexer.
Multiplexers (Data Selectors) The data-input and data-select waveforms in the following figure (a) are applied to the multiplexer. Determine the output waveform in relation to the inputs.
Multiplexers (Data Selectors) Expanded multiplexers
Use 74151s and any other logic necessary to multiplex 16 data lines onto a single data-output line
Multiplexers (Data Selectors) Implement the logic function in the following Table by using a 74151A 8-input data selector/multiplexer. Compare this method with a discrete logic gate implementation.
INPUTS OUTPUT
A2 A1 A0 x0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Multiplexers (Data Selectors)
Implement the logic function in the following Table by using a 74151A 8-input data selector/multiplexer. Compare this method with a discrete logic gate implementation.
INPUTS OUTPUT
A3 A2 A1 A0 Y0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
A demultiplexer (DEMUX) performs the opposite function from a MUX. It switches data from one input line to two or more data lines depending on the select inputs.
Demultiplexers
Demultiplexers2-line-to 4-line demux
Demultiplexers
Data is applied to one of the data input pin, and routed to the selected output line depending on the select variables. Note that the outputs are active-LOW.
The 74LS138 can serve as a DEMUX. When connected as a DEMUX, data is applied to one of the enable inputs, and routed to the selected output line depending on the select variables. Note that the outputs are active-LOW as illustrated in the following example…
Demultiplexers
74LS138
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
DEMUXAAA
0
1
2
GGG
1
2A
2B
Data select lines
Enable
inputs
Data outputs
DemultiplexersThe serial-input waveform (Data in) and data-select input (S0 and S1) are shown in following figure. Determine the data-output waveforms on D0 through D3 for the demultiplexer.
Determine the outputs, given the inputs shown.
Demultiplexers
74LS138
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
DEMUXAAA
0
1
2
GGG
1
2A
2B
Data select lines
Enable
inputs
Data outputs
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A1
A2
G1
G2A
G2B
LOWLOWThe output logic is opposite to the input
because of the active-LOW convention. (Redshows the selected line).
Parity Generators/CheckersParity is an error detection method that uses an extra bit appended to a group of bits to force them to be either odd or even. In even parity, the total number of ones is even; in odd parity the total number of ones is odd.
11010011S with odd parity =S with even parity = 01010011
The ASCII letter S is 1010011. Show the parity bit for the letter S with odd and even parity.
Parity Generators/CheckersA 9-bit parity checker/generator can be used to generate a parity bit or to check an incoming data stream for even or odd parity. Checker: The even output will normally be HIGH if the data lines have even parity; otherwise it will be LOW. Likewise, the odd output will normally be HIGH if the data lines have odd parity; otherwise it will be LOW.
Generator: To generate even parity, the parity bit is taken from the odd parity output. To generate odd parity, the output is taken from the even parity output.