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DLLs and PLLs 1

Delay Locked Loopsand

Phase Locked Loops

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DLLs and PLLs 2

Motivation: System

B3B1

B2

FF1G1 FF2

B4

U1 U2

CLK

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DLLs and PLLs 3

AnalysisSetup Time Calculation

The setup time at FF2 is calculated from the common point CLK.Use the maximum delay to set up FF2:D (G1 output)

Use the minimum delay to drive FF2:CLK (B4 output)

To drive the data we add (max)

B1

B2FF1 (CLK -> Q)G1FF2 (tsu)

If the CLK at FF1 would occur at exactly the same time as CLKon the board, then the delays for B1 and B2 would effectivelybe zero.

Note that this technique relies on the max delays beingeliminated being greater then losing the minimum delays in theclock path.

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Setup Time Flow

B3B1

B2

FF1G1 FF2

B4

Use max for data path

U1 U2

CLK

Use min for clock path

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AnalysisHold Time Calculation

The hold time at FF2 is calculated from the common point CLK.Use the minimum delay to set up FF2:D (G1 output)

Use the maximum delay to drive FF2:CLK (B4 output)

To drive the clock we add (max)

B3

B4FF2 (th)

If the CLK at FF2 would occur at exactly the same time as CLKon the board, then the delays for B3 and B4 would effectively

be zero.

Since the delay through U1 and U2/G1 can not be zero, then ifFF2:th = 0, we can design the system as if flip-flops in U2have a zero hold time at the device’s input pins. That istypically how we designed with “good” SSI and MSI devices.

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Hold Time Flow

B3B1

B2

FF1G1 FF2

B4

Use min for data path

U1 U2

CLK

Use max for clock path

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Motivation: Clock Control

• Locking to external signals• Phase control

• Frequency Multiplication• Frequency Division

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Basic Phase Locked Loop

PhaseDetector

Low

PassFilter

VoltageControlled

Osc.

Analog Circuit

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Example: PLL Multiplication

PhaseDetector

Low

PassFilter

Voltage

ControlledOsc.

Divide by

n

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Example: PLL Multiplication

PhaseDetector

Low

PassFilter

Voltage

ControlledOsc.

Divide by

n

Single Event UpsetHeavy Ion or Proton

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DLL Another Technique

Goal: System Clock Matches Clock at F-F

FF1

U1

CLK

Ideal0 ns

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Buffer Tree Delays Not Negligible

CLK

FF1:CLK

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DLLs and PLLs 13

Buffer Tree Delays Not NegligibleSo Add A Delay

CLK

FF1:CLK

Delayed CLK

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DLLs and PLLs 14

Buffer Tree Delays Not NegligibleAdd A Bit More Delay

CLK

FF1:CLK

Delayed CLK

More Delay

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Buffer Tree Delays Not NegligibleAdd Just A Bit More Delay

CLK

FF1:CLK

Delayed CLK

More Delay

A Bit More

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DLLs and PLLs 16

What Did We Do?

CLK

FF1:CLK

Delayed CLK

More Delay

A Bit More

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DLLs and PLLs 17

DLL Another Technique

Insert “Proper” Delay

FF1

U1

Goal: Insert Delay to Make The Difference Zero If We DelayThings “Enough” To Line Up Corresponding Edges of Different Cycles.

CLK

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DLL Principle Of Operation

Delay Line

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DLLs and PLLs 19

DLL Principle Of Operation

Single Event UpsetHeavy Ion or Proton

Delay Line

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DLLs and PLLs 20

Manufacturers’ Selections

• Actel

– AX: PLL – ProAsic, ProAsic+ ???????

• Xilinx Virtex: DLL• Chip Express

– QYH500: DLL – CX2000: PLL – CX3000: PLL

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Virtex Architecture Overview

IOB = I/O BlockDLL = Delay-locked loopBRAM = Block RAM

(4,096 bits ea.)CLB = Configurable Logic

Block

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Virtex DLL

• Uses discrete digital delay line

• Latency: 1 to 4 clock periods• 4 Quadrature phases

• Can double frequency – quadruple if two DLL’s used

• Divide by 1.5, 2, 2.5, 3,4,5,8, or 16• Deskew board clock • Multiple FPGAs, other devices

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DLLs and PLLs 23

Board Level Clock De-Skewing

Note: Can include

multiple Virtex devices.

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Chip Express QYH500 DLL

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Chip Express QYH500 DLL

Single Event UpsetHeavy Ion or Proton

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AX PLL Architecture

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AX PLL

• Fout = Fin * i / j – 1 ≤ i,j ≤ 64

• Programmable delays – 250 ps steps, Range ± 3.75 ns

• Can cascade up to 8 PLLs

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AX PLL: External Components

+1.5V

Board FPGA

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Key Parameters

• Minimum and Maximum Frequencies

• Tolerance on input signals – Frequency – Jitter

• Lock Time• Output Phase Offset• Output Jitter

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DLLs and PLLs 30

Timing Analysis

CLK

With a crystal clock oscillator, the time from rising edge to

rising edge (or falling edge to falling edge) is quite stable,with crystal clock oscillators having relatively low jitter andgood short term stability.

l

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DLLs and PLLs 31

Timing AnalysisMax

Min

CLK

• With DLL and PLL, one must check the jitter specifications carefully, to assure that worst-case timing

must be met.• Analysis must include the time before the loop locks.• Analysis must include the effects of SEU’s on the loop’s

control circuits.