Demonstration of 2µm RDL Wiring Using Dry Film Photoresists and 5µm RDL Via by
Projection Lithography for Low-cost 2.5D Panel-based Glass and Organic Interposers
Ryuta Furuya*, Hao Lu**, Fuhan Liu**, Hai Deng***, Tomoyuki Ando***, Venky Sundaram** and Rao Tummala**
Ushio Inc.*
6409 Motoishikawa-cho, Aoba-ward, Yokohama city, Kanagawa Prefecture, Japan
3D Systems Packaging Research Center, Georgia Institute of Technology**
Atlanta, GA USA
TOK Corporation***
Email: [email protected]
Abstract
High-density packages and 2.5D interposers require 2µm
trace widths and gaps, and less than 10µm ultra-small
microvias to achieve 20-40µm I/O pitch interconnections.
Silicon interposers with through-silicon-vias (TSVs) have
been used for such ultra-high density interconnections
between logic and memory chips with sub-micron multi-layer
copper wiring. However, the high cost of silicon interposers
coming from back end of line (BEOL) processes have limited
their applicability to mobile systems like smart phones and
wearables. Glass and organic interposers have been
investigated as a lower cost solution coming from large panel
processes and dry film lithography for semi-additive copper
metallization. However, achieving high wiring density with
low-cost package substrate processes remains a challenge.
This paper presents the first demonstration of high resolution
photo-lithography processes to achieve 2µm copper line
widths and 5-10µm microvias with panel-based processes
using newly developed large field projection lithography tools
and advanced dry film photoresists. A two-metal layer re-
distribution layer (RDL) structure integrating 2µm line and
space wiring and less than 10µm ultra-small microvias was
demonstrated on ultra-thin glass and organic substrates.
Introduction
The demand for logic-memory bandwidth continues to
escalate due to the data growth in smart phones, tablets,
wearable devices and sensors for Internet of Things (IoT)
applications. Ultra-high density interposers address high
bandwidth interconnections with very small copper trace
widths and ultra-small re-distribution layer (RDL) microvias
to connect multiple wiring layers. A typical high performance
logic device will require approximately 2,000 connections to
one high bandwidth memory (HBM) stack, with four to eight
HBM stacks in one interposer. The bump pitch for such a
wide I/O channel is currently at 40µm, requiring 2µm copper
traces and RDL vias at less than 10µm diameter and at the
same pitch as the bumps. Silicon interposers with sub-micron
width copper wiring have been developed to interconnect
graphics and logic ICs to HBMs [1] [2]. Such silicon
interposers use back end of line (BEOL) semiconductor wafer
processes, where copper traces are formed by damascene or
dual-damascene processes and RDL vias are dry etched using
reactive ion etching (RIE) processes [3]. Although silicon
interposers meet the I/O pitch targets for 2.5D integration,
they suffer from high cost, driven by expensive processes
such as chemical-mechanical polishing (CMP) and deep
reactive ion etching (DRIE), thus limiting their use for a
broader set of applications, especially mobile devices.
Panel-based glass and organic interposers provide a
compelling lower cost alternative to silicon interposers, due to
the higher number of unit interposers from large panels, as
well as lower cost processes that use dry film materials and
higher throughput tools. Such panel-based interposers use
semi-additive processes (SAP) for RDL fabrication. Organic
interposers have been reported by SEMCO Korea, combining
thinfilm high-density RDL layers with conventional build-up
layers, allowing for direct mounting of the interposers to
mother boards, resulting in improved reliability from fewer
levels of solder bump interconnections [4]. Shinko Japan, in
partnership with Global Foundries, successfully demonstrated
organic interposers with 2µm copper wiring and 10µm
diameter vias using liquid photosensitive dielectric and liquid
photoresist [5]. However, the poor dimensional stability of the
organic laminate cores limits the scaling of I/O pitch.
Georgia Tech and other groups have demonstrated glass
interposers as an ideal solution to address the cost and loss
limitations of silicon interposers, as well as the warpage
induced thickness limits and pitch scaling of organic
interposers [6]. This paper demonstrates 2µm width copper
wiring with 2µm spacing, and 5µm diameter ultra-small
microvias using dry film photosensitive materials using panel-
based double-side processes on both glass and organic cores.
Such an approach is expected to further reduce the interposer
cost compared to the thinfilm wiring based organic interposers
discussed earlier. The first section of this paper describes the
panel-based process for 2µm copper wiring with a newly
developed advanced lithography tool. The second section
describes the processes used to achieve 5µm ultra-small
microvias in photosensitive dry film dielectric materials. The
third section discusses the demonstration of an integrated
multi-layer RDL structure combining very small copper traces
and RDL vias using an SAP process.
Panel Processing to Achieve 2 µm Copper Wiring
The only industrialized process for less than 5µm trace
widths is the wafer-based damascene process. In the
damascene process, liquid photoresist is coated on the
dielectric layer and patterned with a small reticle lithography
tool, followed by trench formation in the dielectric layer by
plasma etching. Subsequently, the trenches and vias are
metallized by sputtering a Ti-Cu seed layer and electrolytic
copper plating until they are fully filled. Excess copper plated
on the surface is then removed using a CMP step to achieve a
978-1-4799-8609-5/15/$31.00 ©2015 IEEE 1488 2015 Electronic Components & Technology Conference
Fig. 1. Conventional semi-additive process (SAP) flow.
planar surface, ready for next layer processing. Although such
damascene processes can make sub-micron features, they are
limited by high cost due to vacuum and polishing processes
and small wafer size. On the other hand, organic package
substrates utilize SAP, where a thin copper seed layer is
formed by electroless plating or sputtering, followed by dry
film photoresist lamination on the substrate and lithographic
patterning, and copper electrolytic plating to the final
thickness. The last step involves removal of the photoresist
and wet chemical etching of the seed layer, as shown in Fig.
1. Semi-additive process using dry film materials is a double-
side process and scalable to larger panel sizes, thus providing
a more cost effective path to ultra-small bump pitch than
wafer-based damascene or thinfilm processes. Traditional
SAP processes have several challenges associated with the dry
film photoresists, including lower resolution and weaker
adhesion to the surface copper compared to liquid
photoresists. The current state-of-the-art using dry film
photoresists on organic substrates is around 6µm width and
space wiring in development [7], while 3µm resolution has
been demonstrated in limited research studies [8] [9].
The objective of this study was to fabricate 2µm wide
copper traces and gaps using advanced dry film resists and a
newly developed panel scale lithography tool. The core used
was a 400µm thick FR-4 laminate with ZEONIF ZS-100
(ZIF) dry film dielectric material as RDL dielectric. The ZIF
material is unique due to its very low surface roughness
(Ra<100 nm). ZIF with a thickness of 22.5µm was laminated
on both sides of the FR-4 core by vacuum lamination at 93°C,
followed by a very short hot press cycle at low pressure and at
115°C to planarize the surface. Then, conventional wet
desmear process was done for 20 min to improve the
electroless plated copper adhesion and a 0.3-0.5µm thick
copper seed layer was formed by low stress electroless
plating. For lithography, a new advanced dry film photoresist
with 7µm thickness was laminated on the copper seed layer,
and lithography was performed using a projection aligner UX-
44101 from Ushio Japan [10].
Fig. 2. Picture of the projection lithography tool
UX-44101 in square 70 series at Georgia Tech.
UX-44101 is a specialized projection lithography tool for
panel-based fabrication process, which has a 2µm resolution
and 70mm x 70mm large exposure area. This large exposure
area enables high throughput step-and-repeat exposure,
suitable for high-volume manufacturing of full-panel size
interposers in the near future. Another unique feature of this
tool is the +/- 10µm depth of focus, essential to accommodate
non-planarity, and warpage of the organic panels and
variation of work thickness. Table 1 summarizes the key
specifications of this lithography tool.
Table 1. UX-44101 projection lithography tool
specifications
Resolution < 2µm L/S
Effective exposure
field
70mm x 70mm
Wavelength 365nm (i-line)
Depth of Focus (DOF) +/- 10µm
Alignment accuracy <1µm
After the exposure, CF4 / O2 plasma treatment and wet
cleaning processes were performed to remove resist residues
and clean the surface, followed by electrolytic plating for
copper metallization. Then, a wet chemical stripping process
at 50°C was used to remove the dry film photoresist. Finally,
a flash wet etching process was used to remove the copper
seed layer. With the conventional seed layer etching process,
strong side etching occurs, causing damage to fine copper
wires. Therefore, the isotropic wet etching process for seed
layer removal faces severe challenges in achieving less than
5µm width and space copper wiring. To address this
challenge, a new chemistry and process from Atotech GmbH
Germany was used. This differential etching process has a
high etch selectivity for seed layer etching over electrolytic
plated copper when used in a spray etch tool, enabling the
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removal of the copper seed layer without destroying the ultra-
small copper wires.
Fig. 3 shows the resist trench pattern after development,
demonstrating sharp feature definition down to 2µm widths.
Fig. 4 shows the top view of the copper wires after copper
electroplating, resist removal and seed layer etching. The
cross section of these copper traces is shown in Fig. 5. From
this figure, it can be observed that 2 to 5µm wide copper
wiring was successfully achieved using a panel-based SAP
process. However, since the copper thickness was not uniform
between coarse wires and fine wires, the copper plating
process needs to be improved further for better thickness
uniformity. Fig. 6 shows an escape routing pattern test
structure on a glass panel, with a pad pitch of 40µm, pad size
of 15µm and 3 lines escape routed within this bump pitch.
Fig. 3. Resist trench patterns after development.
Fig. 4. 2µm L/S wires successfully formed by panel-based
semi-additive process after electrolytic plating and seed layer
etching on FR-4 substrate.
Fig. 6. SEM image of escape routing patterns with 2µm lines
and spaces copper wires and 15µm pads on glass.
Ultra-small Photovia Formation
The current method of via formation in organic package
substrates is laser drilling through the polymer dielectric
layers. CO2 lasers have been used for 20 years for this
purpose because of their low cost, compatibility with a wide
variety of materials, and high throughputs. However, since the
wavelength of the CO2 laser is large and causes strong heating
in the dielectric, it is difficult to form less than 40µm diameter
vias. Solid state lasers and excimer lasers with shorter
wavelength are being investigated for this purpose. Via
diameters of 20µm by Nd-YAG laser ablation [11] and 10µm
by excimer laser ablation in thin polymer dielectric films [12]
have been reported. The lower throughput and higher cost of
operation of these newer types of lasers remains a concern for
manufacturing, although advances are being made by tool
manufacturers in improving the productivity of such systems.
Fig. 5. A Cross section image of copper wires from
2µm to 5µm L/S on FR-4 substrate.
15 um 20 um
20 um
20 um
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Photovias are an alternative solution for forming ultra-
small microvias below 10µm. In this approach, a
photosensitive polymer is used as the dielectric layer and
dense via patterns are formed on the entire panel by UV
exposure and development. Such photovia processes can be
scaled to much higher via counts, since the process time does
not have a strong dependence on the number of vias on the
panel. The photovia method also has advantages in via
miniaturization due to the elimination of thermal damage to
the dielectric material. However, photovias have not been
used widely so far in package substrates due to the limited
availability of high resolution and dry film photosensitive
materials. With the advent of fine pitch interposers, requiring
smaller diameter RDL microvias, there has been a renewed
interest in developing advanced photosensitive dielectric
materials.
In recent work, Shinko demonstrated 40µm I/O pitch
organic and glass interposers with 10µm diameter photovias
[11] [13], and Samsung showed 50µm pitch organic
interposers with 6µm diameter photovias [12]. Liquid
photosensitive materials deposited using single sided spin
coating using wafer tools was used in both cases. This paper,
however, focuses on dry film dielectric materials, specifically
TMMF S2014 from Tokyo Ohka Kogyo Co., Ltd (TOK).
TMMF S2014 is based on epoxy resins with chemical
amplification to form photosensitive films with high Tg and
capable of high aspect ratio structures greater than 8:1 [14].
This material is also compatible with double-side panel
processes, with the potential to significantly reduce the cost
compared to spin-on wafer processes. Table 2 lists the
thermo-mechanical and electrical properties of the TMMF
S2014 photosensitive dry film dielectric.
Table 2. Property of Dielectric material TMMF S2014
Tg 230 °C
Coefficient of thermal expansion 65 ppm /°C
Young Modulus 2.1 GPa
Dielectric Constant 3.8
Thickness 14µm
TMMF S2014 with 14µm thickness was laminated on
copper clad FR-4 laminate core using a hot roll laminator at
110°C, followed by drying and UV exposure with 270 mJ/cm2
dose. The same projection aligner, UX44101 from Ushio,
shown in the previous section, was used for UV exposure.
After exposure, the samples were baked for 20 minutes at
90°C, followed by developing with propylene glycol
monomethyl ether acetate (PGMEA) and rinsing with
isopropyl alcohol (IPA). After development, the dielectric
film was cured in a convection oven at 200°C for one hour.
Fig. 7 shows the scanning electron micrograph images of
fabricated microvias from 5 µm to 20 µm diameter. The via
edges were sharp and showed no signs of damage and
residues in adjacent areas, which is essential for placing
copper traces close to the vias for fine pitch routing. For high
density interposers, it is important to reduce the space
between microvias and routing copper wires, in addition to
miniaturizing the microvias themselves. Therefore, the sharp
definition of vias in this material is a key benefit.
Fig. 7. Formed photo microvias from 5µm to 20µm.
Thickness of the TMMF S2014 film is 14µm.
Two-Layer RDL with Fine Wiring and Small RDL Vias
The processes described in the previous two sections were
integrated to form a two-metal layer RDL structure with 2µm
L/S fine features and 10µm ultra-small microvias, for 40µm
I/O pitch. For the first demonstration, a simple two-metal
layer escape routing structure was designed, as shown in Fig.
8. The design consists of 2µm L/S copper wiring between
15µm diameter pads that are located at 40 µm pitch.
Fig. 8. Design for demonstration of two-layer RDL structure
with 2µm L/S copper traces and 10µm vias.
5µm
8µm
10µm
20µm
5µm
8µm
10µm
20µm
14um TMMF
2um L/S
2um L/S
15 um pad
15 um pad
10 um via
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In the fabrication process, 22.5µm thick ZIF films were
laminated on both sides of 400µm thick FR-4 substrate at
first, followed by copper-polymer RDL fabrication using the
materials and processes described in the previous sections.
After the formation of copper lines, a non-etching type
adhesion promoter, NOVABOND ITTM
from Atotech GmbH,
Germany, was used to enhance the adhesion between the
copper structures and the second layer dielectric film [15]
[16]. This process forms nano-scale copper structures to
increase the surface area, leading to higher bonding strength
between the dielectric film and copper without adding
significant roughness to the interface. The substrate was bake
dried for 10 minutes at 90°C and TMMF S2014 (14µm thick)
was laminated on the first copper layer. After lamination of
the photosensitive film, UV exposure was conducted using
projection aligner UX-44101 from Ushio with 270 mJ/cm2
dose, followed by post-exposure bake, development and
thermal cure. After via formation and curing, a 50nm thick
titanium adhesion layer and a 250nm thick copper seed layer
were sputtered on the dielectric film to cover the surface and
microvia walls. The next step was to laminate 7µm thick dry
film photoresist on the surface, followed by lithographic
patterning using UX-44101 from Ushio. Semi-additive
electrolytic copper plating with a specialized chemistry from
Atotech was used to metallize the vias and copper tracks. This
unique via filling chemistry uses organic additives to increase
the plating rate inside the vias preferentially over the surface
lines, resulting in complete copper filling of the RDL blind
vias with minimal copper overburden on the surface [17]. The
second layer copper wires and vias were plated
simultaneously, followed by dry film resist removal and seed
layer etching.
Fig. 9 shows the cross-section micrographs of the
fabricated two-metal layer RDL structure with 2µm width
copper wires at 2µm spacing, and 10µm diameter vias.
Although this first demonstration does not include
connections between copper wires and pads, the feasibility of
multi-layer RDL at 40µm bump pitch was achieved using low
cost panel processes for 2µm fine copper lines and 10µm vias
applicable to glass and organic interposers.
Fig. 9. Cross section image of fabricated 2 layer structure
on FR-4 substrate illustrated in Fig. 8.
Conclusions
This paper demonstrated 2µm width and spacing fine
copper wiring using advanced semi-additive processes with
dry film photoresists, and 5µm small photovias using newly
developed high resolution dry film photosensitive polymer
dielectrics. Additionally, a fully integrated two-metal layer
RDL structure was demonstrated consisting of 2µm width and
spacing copper wires and 10µm interlayer microvias. Double-
side and large panel processes were utilized with dry film
photoresists and photosensitive dielectrics, providing a path
for low cost interposers. Such an approach is expected to
enable the use of high-density 2.5D organic and glass
interposers for cost sensitive, smart mobile, and emerging
wearable electronics and IoT applications.
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