The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND. Design & Build Ka Band Transceiver Chipset Final Report ESTEC Contract Number 4000117173/16/UK/ND ESA Technical Officer(s): Valérie Dutto, ESTEC, Noordwijk Author(s) Arralis, Limerick, Ireland Date: 26 th November 2018 Document ref. DE-21 Final Report (Revised) EUROPEAN SPACE AGENCY CONTRACT REPORT The work described in this report was done under ESA contract. Responsibility for the contents resides in the author or organisation that prepared it.
Transcript
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
Design & Build Ka Band Transceiver Chipset
Final Report
ESTEC Contract Number 4000117173/16/UK/ND
ESA Technical Officer(s): Valérie Dutto, ESTEC, Noordwijk
Author(s)
Arralis,
Limerick, Ireland
Date: 26th November 2018
Document ref. DE-21 Final Report (Revised)
EUROPEAN SPACE AGENCY
CONTRACT REPORT
The work described in this report was done under ESA contract. Responsibility for the contents
resides in the author or organisation that prepared it.
Document ref.: DE-21 Final Report (Revised)
Page 2 of 20
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
Table of Contents
1. Objective of Activity....................................................................................................... 3 2. Key Issues ....................................................................................................................... 4
3. Results of Work .............................................................................................................. 4 i. 17-21GHz Power Amplifier ............................................................................................ 4 ii. 17-21GHz Mixer Design................................................................................................. 5 iii. 17-31 GHz Low Noise Amplifier Design ................................................................... 6 iv. 27-31 GHz Power Amplifier Design ........................................................................... 7
v. 27-31GHz Mixer Design................................................................................................. 8 vi. 24GHz Voltage Controlled Oscillator Design ............................................................ 9 vii. 17-21GHz Transmitter (TX) Design ......................................................................... 11 viii. 27-31GHz Transmitter (TX) Design ......................................................................... 12 ix. 17-21GHz Receiver (RX) Design ............................................................................. 14
xi. Transceiver Board ..................................................................................................... 18 4. Main Benefits ................................................................................................................ 20
5. Further Technical and Commercial Evolution .............................................................. 20
Document ref.: DE-21 Final Report (Revised)
Page 3 of 20
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
1. Objective of Activity
The activity of this work was to design and build 5 x Ka-Band Core Chip MMICs which would
then then be packaged into QFN cases (Quad Flatpack No Leads). To ensure identifiable
deficiencies, the design process followed a step by step procedure where basic MMIC circuit
functionality was tested before combining these into multifunction core chips and finally the
packaged versions of these core chips were tested. For ease of demonstration, a Transmit (TX)
and Receive (RX) demonstrator transceiver reference board was also developed on a space
qualified material which incorporated these packages. The full list of the design deliverables is
given in Table 1 below: -
ID Description
DE - 2 Individual MMICs: -
17-21 GHz Power Amplifier
17-21 GHz Mixer
24GHz VCO
17-31 GHz Low Noise Amplifier
27-31 GHz Power Amplifier
27-31 GHz Mixer
DE - 5 Core Chip MMICs: -
Transmitter (TX) at 17-21 GHz
Transmitter (TX) at 27-31 GHz
Receiver (RX) at 17-21 GHz
Receiver (RX) at 27-31 GHz
DE - 7 Packaged QFN MMICs: -
Transmitter (TX) at 17-21 GHz
Transmitter (TX) at 27-31 GHz
Receiver (RX) at 17-21 GHz
Receiver (RX) at 27-31 GHz
DE - 10 Demonstrator Transceiver Board
Table 1:- Deliverables
The MMICs were designed on the UMS PH25 foundry process as it offered a good compromise
between available output power and noise figure, which was necessary for the core chip
designs. Two wafer runs were sent for fabrication (LEONIS1 and LEONIS2), with enough
circuits fabricated to allow different design options for each circuit function, which allowed
the project to be completed.
Document ref.: DE-21 Final Report (Revised)
Page 4 of 20
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
2. Key Issues
To implement a multifunction MMIC with parameters as varied as NF, phase noise and power,
the choice of MMIC foundry process which offered a compromise between all these parameters
was difficult. Likewise, the avoidance of detrimental coupling between the different sections
of the core chip MMICs was also difficult and required a considerable amount of simulation
effort to ensure that the chips worked acceptably.
3. Results of Work
The follow sections show the results of the work.
i. 17-21GHz Power Amplifier
The results of the 17-21GHz Power amplifier test circuit are shown below: -
Figure 1:- 17-21GHz Power Amplifier MMIC Test Results
The measured performance which was as simulated, meant that a re-design was not required
and the circuit was incorporated in the 17-21 GHz Transmitter (TX) core chip design.
Document ref.: DE-21 Final Report (Revised)
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The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
ii. 17-21GHz Mixer Design
The results of the 17-21GHz mixer test circuit are shown below: -
Figure 2:- 17-21GHz Mixer MMIC Test Results
The performance allowed this circuit to be integrated into the 17-21GHz core chip designs.
Document ref.: DE-21 Final Report (Revised)
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The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
iii. 17-31 GHz Low Noise Amplifier Design
The performance of the bare die MMIC LNA is shown in Figure 3:-
Figure 3:- 17-31|GHz Low Noise Amplifier MMIC Test Results
As can be seen the performance of the circuit is excellent, although the gain flatness was
inadequate over the 27-31GHz band. As a result, the LNA in the 27-31GHz downconverter
core chip was redesigned.
Document ref.: DE-21 Final Report (Revised)
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The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
iv. 27-31 GHz Power Amplifier Design
The results of the 27-31GHz Power amplifier test circuit are shown below: -
Figure 4:- 17-21GHz Power Amplifier MMIC Test Results
As for the case of the low frequency version, the measured performance, which was as
simulated, meant that a re-design was not required and the circuit was incorporated in the 27-
31 GHz Transmitter (TX) core chip design.
Document ref.: DE-21 Final Report (Revised)
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The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
v. 27-31GHz Mixer Design
The higher frequency mixer test circuit was found to have good performance and was integrated
into the 27-31GHz upconverter (TX) and downconverter (RX) core chips. The test circuit
measured performance is shown in Figure 5:-
Figure 5:- 27-31GHz Mixer MMIC Test Results
The results and circuits described in Section 3(i)-(v) were used to design the integrated core
chips discussed in the following sections. To allow the mixers to work at a lower LO drive
level, a further LO amplifier circuit was added at the LO port in each circuit and thus each of
the frequency conversion core chips were comprised of three sub-circuits i.e. LO amplifier,
mixer and PA/LNA.
Document ref.: DE-21 Final Report (Revised)
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The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
vi. 24GHz Voltage Controlled Oscillator Design
The results of the 24GHz VCO test circuit are shown below, the resulting good performance
allowed the chip to be packaged using a QFN case: -
Figure 6:- 24GHz VCO MMIC Test Results
The chip was placed within a 6 x 5mm QFN package in such a way that the RF bond wires
were kept as short as possible, with the bond wire reactance ‘removed’ by matching on the test-
board. The VCO had good performance with less than 3.5MHz / degree frequency shift over
temperature: -
Figure 7:- 24GHz VCO (6 x 5mm QFN Package) Test Results
Document ref.: DE-21 Final Report (Revised)
Page 10 of 20
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
The resulting specification table for the packaged DE-2C part is: -
Parameter Min Type Max Unit Comments
Frequency 23 24.25 GHz
Pout
12 dBm
Supply Voltage 3 V
VTUNE
0 1.6 V
Supply Current 90 mA
Phase Noise @1MHz -80 dBc/Hz
REFIN
Output Frequency 11.5
11.75 GHz
PREF
4 dBm
Table 2:- Specification Table for the DE-2C Packaged Core Chip
Document ref.: DE-21 Final Report (Revised)
Page 11 of 20
The copyright in this document is vested in Arralis. This document may only be reproduced in whole or in part, or stored in
a retrieval system, or transmitted in any form, or by any means electronic, mechanical, photocopying or otherwise, either
with the prior permission of Arralis or in accordance with the terms of ESTEC Contract no 4000117173/16/UK/ND.
vii. 17-21GHz Transmitter (TX) Design
The measured results for the 17-21GHz upconverter transmitter (TX) circuit, are shown in
