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Design and Analysis of PWM-Based Two-Stage Current-Mode Multiphase Voltage Doubler
By
Yuen-Haw Chang
Department and Graduate Institute of
Computer Science and Information Engineering,
Chaoyang University of Technology, Taichung, Taiwan, Republic of China.
Address: 168 Gifeng E. Rd., Wufeng, Taichung County,
Taiwan, R.O.C.
Post Code: 413
Tel No.: 886-4-2332-3000 Ext.4411
Fax No.: 886-4-2374-2375
E-mail: [email protected]
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Abstract: A new closed-loop switched-capacitor (SC) converter of two-stage current-mode multiphase voltage
doubler (CMPVD) is presented by combining multi-phase operation and pulse-width-modulation (PWM) technique
for low-power DC-DC step-up conversion and output current regulation. This proposed CMPVD is composed of two
voltage doublers and one constant current source in series connection. The voltage doublers are applied in charge of
boosting output voltage, and combined with multi-phase operation for the higher voltage gain under the least number
of pumping capacitors. The current source is adopted for supplying a constant current at output terminal, and
combined with PWM technique so as to reinforce output regulation capability as well as robustness against
source/loading variation. Further, the relevant theoretical analysis and control design are included as: CMPVD model,
steady-state/dynamic analysis, power efficiency, conversion ratio, output ripple, source lower bound, capacitance and
current source selection, closed-loop control and stability. Finally, the closed-loop CMPVD is designed and simulated,
and the hardware implementation of CMPVD is realized and experimented. All the results are illustrated to show the
efficacy of the proposed scheme.
Keywords: switched-capacitor, current-mode, multiphase voltage doubler, step-up, pulse-width-modulation.
1. Introduction
With the coming age of portable electronic equipments, some features of power modules are emphasized, such as
small volume, light weight, high power density/efficiency, and good regulation capability. The SC-based power
converter, possessed of the power stage based on charge pump structure, is one of the good solutions to low-power
DC-DC conversion because it has only semiconductor switches and capacitors. Unlike the traditional ones, the SC
converter needs no magnetic element, e.g. inductor and transformer, so such an inductor-less converter always has
light weight, small volume, and low EMI.
A charge pump SC converter is usually designed to obtain an output higher than times the voltage of supply or a
reverse-polarity voltage. Such a step-up/reverse function is suitable for many applications, e.g. power-transistor, op-
amp power, flash EEPROM, white light emitting diode (WLED), fluorescent lamp, and liquid crystal display (LCD)
drivers [1]. In fact, the SC idea has existed over half a century. In 1932, Cockroft and Walton implemented a
capacitor-diode voltage multiplier in the particle accelerator of the nuclear reaction. In 1971, Brugler suggested SC
voltage multiplier [2], and then Lin and Chua presented the relevant topological analysis [3]. Recently, many SC
applications are expanding, e.g. transformerless large-conversion-ratio converter [4], and bidirectional SC converter
[5]. Up to now, the various types of SC converters have been suggested for power conversion, and the well-known
topologies are as follows: (i) Dickson charge pump, (ii) Cheong SC converter, (iii) Ueno charge pump, (iv) Makowski
charge pump. In 1976, Dickson charge pump was proposed, and it is composed of a diode chain connected with two-
phase clocks via pumping capacitors [6]. Via two-phase operation, it provides the voltage gain proportional to the
stage number of pumping capacitors, and its dynamic model and efficiency analysis were discussed [7-8]. But, its
drawbacks include the fixed voltage gain and the larger device area. In 1993, Cheong et al. suggested a voltage-mode
SC configuration with two symmetry capacitor cells working complementarily, and the PWM technique was used for
the flexible voltage gain [9-10]. In 1994, Ngo et al. first proposed a current control of SC converters by using a
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saturated transistor as a controllable current source [11]. In 1996, Chung et al. suggested a new current-mode SC
scheme [12]. In fact, this new scheme is similar to [9], but the difference is to charge capacitors by a current source,
not by a voltage source. Such a current-mode scheme has a continuous current at supply terminal, so the EMI could be
improved. In 1997, Zhu and Ioinovici performed a comprehensive and accurate steady-state analysis of step-up SC
converter [13]. Following this, Chang proposed an integrated SC step-up/down DC-DC/DC-AC converter [14-16].
Recently, Axelrod et al. suggested a hybrid switched-capacitor/inductor converter [17], and Tan et al. proposed a low-
EMI SC by interleaving control [18]. However, Cheong SC converter still provides the voltage gain proportional to
the number of pumping capacitors, so it could need the larger device area for the high voltage gain.
In 1991, Ueno proposed much of the new known structures: series-parallel, Fibonacci, etc. The 4-stage SC
transformer idea was proposed for the step-up ratio of Fibonacci series to realize an emergency power supply [19], and
then a low-ripple or low-input-current SC converters were presented [20-21]. However, their converters were suffering
from a very limited line regulation capability. In 1997, Makowski suggested a canonical structure of multiplier charge
pump with two-phase cascaded voltage doublers [22]. Via two-phase operation, an n-stage Makowski charge pump
can obtain the voltage gain limited by the (n+1)-th Fibonacci number. The relevant steady-state analysis, voltage/
power loss are discussed [23]. In the two-phase SC, it has been proved just to require the least number of pumping
capacitors [24]. Following this idea, Starzyk proposed a new charge pump scheme of multiphase voltage doubler [25],
and suggested multi-phase operation different from two-phase control before. Further, the relevant analysis and
performance limits were discussed, and the relationship between voltage gain and phase number was presented by
generalized Fibonacci number [26-27]. An n-stage Starzyk charge pump can boost the voltage gain up to n2 at most.
In other words, the number of pumping capacitors in Starzyk is required fewer than that in Makowski for the same
voltage gain. Nevertheless, some improved spaces still exist as follows. (i) Since the battery voltage is decreasing with
time, or it has the impure DC component, such a source variation often occurs. In addition, loading variation arises
from unexpected failure or adding/removing the load. They always affect the output current. To keep output current
stable and constant, we employ a constant current source here so as to reinforce output robustness. (ii) Since Starzyk’s
circuit is fixed, the output voltage is also a constant value. In fact, the more flexible output is needed for the different
desired outputs. Here, to enhance output regulation, we adopt PWM technique for the closed-loop current control [28].
Our main purpose is to propose a closed-loop CMPVD for step-up conversion and output current regulation.
2. Configuration of CMPVD:
2.1 Structure of CMPVD:
Fig. 1(a) shows a closed-loop two-stage CMPVD with PWM control, and it contains two major parts: “power
part” and “control part”. The power part in the upper half of Fig. 1(a) is called two-stage CMPVD, which is based on
Starzyk charge pump [25]. The proposed CMPVD is composed of two voltage doublers and one constant current
source DI in series connection between source SV and output oV . For more details, it includes 2 pumping
capacitors 21, CC and 8 MOSFET switches 4p2n1p1n , SS ,SS , where each capacitor has the same capacitance C
( CCC 21 ) with equivalent series resistance (ESR) Cr , and the output capacitor has capacitance oC , and
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4p2n1p1n , SS ,SS are operated as static switches with on-state resistance Tr . Here, one current source DI is added
for expecting a stable and constant output current. DI consists of one current reference and two current mirrors. First,
V is assumed an ideal voltage, and we can set the current reference mI by changing resistor mR (If needed more
precise, the bandgap reference should be employed for mI realization). Then, with the help of two current mirrors
with the current ratios of 1a , 2a , DI can be assigned to a constant value of m21 Iaa . When the larger 1a or mR
is used, mI can be chosen smaller. Thus, a small mI will not result in too large power consumption.
Firstly, Fig. 1(b) shows the theoretical waveforms in one switching cycle ST , which is the inverse of switching
frequency Sf ( S1 fTS ). Each ST contains 4 small phases (phase number 4p ), denoted by Phase I, II, III, IV
with the same phase cycle T ( 4STT ). In Phase I ( ],[ 10 ttt ), let 1S ( 1pS , 1nS ) turn on, and the other 42 SS be
off. So, voltage 1Cv across 1C is charged up to SV as Fig. 2(a). In Phase II ( ],[ 21 ttt ), let 2S , 3S turn on, and
2Cv across 2C is charged with SV and 1Cv in series as Fig. 2(b). In Phase III ( ],[ 32 ttt ), it repeats the Phase I
operation. In Phase IV ( ],[ 43 ttt ), let 2S , 4S be on. Under the series of SV , 1Cv , 2Cv as Fig. 2(c), Cov across oC
is charged via DI within ] [ 33 DTt,tt to supply LR , where D is the duty cycle of T ( 10 D ). According
to Phase I IV, output voltage ov and current oi can be regulated with the charging time DT . Since 1Cv / 2Cv are
charged toward the goal values of SV / S2V , ov can be boosted up to 4 times the voltage of SV at most.
Secondly, the control part: PWM controller is shown in the lower half of Fig. 1(a), which is functionally
composed of low-pass filter (LPF), PWM block and phase generator. In view of signal flow, the feedback signal: oi
is sent into LPF for high-frequency noise rejection. Then, the filtered oI is compared with the desired output
reference refI so as to produce the duty cycle D via the PWM block. The main goal is to compensate the error
between oI and refI . In addition, a phase generator can be realized via frequency divider (FD) to generate the driver
signals of 41 SS as shown the waveforms in Fig. 1(b). To realize duty cycle control in Phase IV, signal 4nS in Fig.
1(a) can be generated via logic AND between 4nS and D . Besides, a remark is given about phase number p .
Exactly, the sufficient phase number is 3p for the maximum voltage gain being 4 [26]. In our paper, the phase
number is taken by 4p , and it seems to be a little redundant in time execution. In fact, it does not affect the
performance too much. Some reasons to keep the redundancy are as follows. (i) The timing control circuit (phase
generator) is made easier when 4p . As shown in Fig. 1(b), we need two sets of symmetrical control signals:
1S , 2S and 3S , 4S for multi-phase operation. It is noticeable that their waveforms are symmetrical. In one switching
cycle ST ( 360 ), 1S is leading 90 ahead of 2S , and 3S is leading 180 ahead of 4S . Such a symmetrical
regularity makes the phase generator realization much easier. (ii) When phase number is 3p ( ST has 3 phases),
the capacitor voltage 1Cv across 1C is charged once (Phase I) per 3 phases. But, in our paper of 4p ( ST has 4
phases), 1Cv across 1C is charged twice (Phase I and III) per 4 phases. According to the charge distribution,
charging twice per 4 phases ( 4p ) is more helpful to the boosting response, even though the switching cycle of
4p is 1/4 cycle longer than that of 3p . Of course, we need a larger output capacitor oC when 4p , but not
very large. When 3p , oC has to stand up alone for 2/3 cycle to supply the load. In our paper ( 4p ), oC has to
supply the load alone for 3/4 cycle. By comparing two cases, our output capacitor oC is needed just 9/8 times the
capacitance value of oC for 3p .
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2.2 Formulation of CMPVD:
Firstly, in Phase I, let 1S turn on and other MOSFETs be off, and the topology is shown in Fig. 2(a). So, the
dynamic equation for Phase I can be described as
S
DVI
0000
10
)()()(
100000
001
)(')(')('
2
1
2
1 RC
tvtvtv
CR
RC
tvtvtv
oo C
C
C
oLC
C
C, (1a)
S
D
S
oVI10
00
)()()(
001100
)()(
2
1
Rtvtvtv
Rtitv
oC
C
C, (1b)
where CT rrR 2 is the parasitic resistance of CMPVD, and )(tvo , )(tiS are the output voltage and the current at
supply terminal, respectively. Here, DI is treated as an input variable with the value of m21 Iaa . Secondly, in Phase
II, let 2S , 3S turn on, and the topology is shown in Fig. 2(b). So, the dynamic equation for Phase II is derived as
S
DVI
002
1 02
10
)()()(
100
02
12
1
02
12
1
)(')(')('
2
1
2
1
RC
RC
tvtvtv
CR
RCRC
RCRC
tvtvtv
oo C
C
C
oL
C
C
C, (2a)
S
D
S
oVI
21000
)()()(
02
121
100
)()(
2
1
Rtvtvtv
RRtitv
oC
C
C. (2b)
Next, Phase III repeats the Phase I operation. So, the dynamic equation for Phase III is identical to (1). In Phase IV, let
2S , 4S turn on, and the topology is shown in Fig. 2(c): In the series with SV , 1Cv , and 2Cv , voltage Cov across
oC is charged via DI within ] [ 33 DTt,tt . So, the dynamic equation for Phase IV is derived as
S
DVI
0
0
0
)()()(
100000000
)(')(')('
2
1
2
1
o
C
C
C
oLC
C
C
CDCDCD
tvtvtv
CRtvtvtv
oo
, (3a)
S
D
S
oVI
000
)()()(
000100
)()(
2
1
Dtvtvtv
titv
oC
C
C. (3b)
Based on (1)-(3), the state-space averaged description of two-stage CMPVD can be derived by state-space
averaging technique [10, 14], 4)]3()1()2()1([ , to be formulated as )()()(' tuBtxAtx avav , (4a) )()()( tuDtxCty avav , (4b)
where T
CCC tvtvtvtxo
)()()()(21
, Ttu SD VI)( , T
So titvty )()()( , (5a,b,c)
oL
av
CR
RCRC
RCRCA
100
08
18
1
08
1
85
,
04
8
14
83
4
o
av
CD
RCCD
RCCD
B ,
08
18
3100
RR
Cav ,
RDDav
85
4
00. (5d,e,f,g)
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3. Theoretical Analysis of CMPVD: 3.1 Steady-state and dynamic analysis:
First, let’s look at the steady-state analysis. By substituting 0)(' tx of (4), the steady-state output voltage oV ,
output current oI , and supply-terminal current SI can be derived as
D1,1
1,o I4
V
Lavavavav
RDuDBAC , Do
o I4
VI
DRL
, (6a,b)
D2,1
2,S II DuDBAC avavavav . (6c)
where 1,avC / 2,avC ( 1,avD / 2,avD ) are the matrices with the 1st/2nd row of avC ( avD ). From (6b), it is observed that
oI is not a function of source SV and load LR . When SV is decreasing or LR is varying, oI is not affected
immediately. In other words, such a source/loading variation makes no immediate response on oI . This is an
excellence of CMPVD for the output robustness. Next, let’s look at the dynamic analysis. We set all variables with
two parts as: )(ˆV)(111 C tvtv CC , )(ˆV)(
122 C tvtv CC , )(ˆV)(oC tvtv
oo CC , )(ˆV)( o tvtv oo , )(ˆD)( tdtD ,
where D ,V ,V ,V ,V oCCC o21 are static operating signals, and dvvvv oCCC o
ˆ ,ˆ ,ˆ ,ˆ ,ˆ21
are dynamic small signals. By the
small-signal technique around static operating point, the small-signal equation of CMPVD can be derived as shown in
(7), and consequently the transfer function is also suggested in (8).
)(ˆ
4I
4I4I
)(ˆ)(ˆ)(ˆ
100
08
18
1
08
1
85
)('ˆ)('ˆ)('ˆ
D
D
D
2
1
2
1
td
C
C
C
tvtvtv
CR
RCRC
RCRC
tvtvtv
o
C
C
C
oL
C
C
C
oo
, )(ˆ)(ˆo tvtvoC . (7a,b)
oLo
o
CRsCsd
svG(s)
11
4I
)(ˆ)(ˆ D
. (8)
3.2 Power conversion efficiency:
Based on (6), the steady-state input/output power can be computed as:
DSSSi IVIVP D , Doooo I4
VIVP D . (9a,b)
By combining (9a) and (9b), the power conversion efficiency is derived as
4VV
41
IV
I4
V
PP
S
o
DS
Do
i
o MD
D
, DRM L
S
D
S
oV4
IVV , (10a,b)
where M represents the DC-DC step-up voltage conversion ratio, and it can be regulated by duty cycle D . Based
on (10a), is rising with increasing M . In fact, is not larger than 100% absolutely, so M must be smaller
than 4 in this two-stage scheme, i.e., oV is boosted up to 4 times the voltage of SV at most. For nominal conditions,
the maximum attainable output oV is SV4 voltage drops in the charging and discharging circuits. But, when M
is operating at the value much smaller than 4 ( oV is much lower than S4V ), will be quite bad. For the better
efficiency, it is good to choose oV be close to S4V as much as possible. If not realized, we will change source SV
or reduce the stage number n (from 2 to 1) to fit SV2 n for the output oV as far as we can.
Here, an additional remark is given about comparison to Zhu’s circuit [13]. Basically, Zhu’s circuit belongs to a
voltage-mode SC converter with the maximum voltage gain proportional to stage n , i.e. Smaxo, V)1(V n . Thus,
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the efficiency can be approximated as: Vs))1(Vo/( n . Exactly, some of our results are similar to the conclusions
presented by Zhu and Ioinovici in 1997 [13]. However, our circuit belongs to a current-mode SC converter, so the
current-mode operation here is different from that of Zhu. Besides, because our power stage is based on Starzyk
structure [25], the maximum voltage gain is 2 to the power of stage n , i.e. Smaxo, V2V n (DC analysis). In our
paper, because the two-stage scheme is considered ( 2n ), the voltage gain can be boosted to 4 at most. So, the
efficiency is derived as: /4)V4Vo/( S M as (10a). To conclude, we have two points different from contents of Zhu:
(i) current-mode analysis and design, (ii) MPVD-based power stage.
3.3 Output ripple percentage:
According to Fig. 1(b), output ov across LR is decaying exponentially from max o,V to min o,V during the
discharging interval of TD)(4 cyclically, and then it can be modeled as: TDtetv t
o )4(0 ,V)( maxo, , ( 4STT ) (11)
where the maximum/minimum value in the discharging interval is denoted by max o,V / min o,V , and formulated by
)0(V maxo, ov and T-Do eTDv )(4
maxo,mino, V))4((V , and oLCR is the discharging time constant. So, the
ripple variation of ov can be defined as: ]1[VVV )(4
maxo,mino,maxo,T-D
o ev . (12)
Based on (11) and (12), the averaged output voltage can be calculated as:
oT-D
o vfD
dttvT-D
S)(4
0 o 44 )(
)(41V . (13)
According to (13), the output ripple percentage is presented as:
oL
S
oL
oCR
TDCRf
Df
Dvrp
44
44
44
%100V SSo
. (14)
Here, it is found that rp is worse while the load is heavier, but it can be improved by increasing Sf or oC .
Obviously, when CMPVD is unloaded ( LR ), rp is almost zero. For a desired ripple pr~ and a specified
frequency Sf , based on of (14) and heavy load of 1D , the minimum output capacitor can be estimated as
prRfCC
Loo ~4
3
Smin,
. (15)
4. Control Design of CMPVD: 4.1 Stability and capacitance selection:
Let’s look at the open-loop stability of CMPVD and capacitance selection. Based on (5d), the system
characteristic equation can be derived as (16a), and its three roots are obtained as (16b-d).
016
14
3122
2
CRs
RCs
CRsAsI(s)
oLav . (16a)
oLCRp
11 ,
RCp
853
2
, RC
p8
533
. (16b,c,d)
For the better conversion, LR should be selected much larger than the parasitic Tr , Cr ( TL rR , Cr ). In fact, LR
is about in -level or above, and Tr , Cr is about in m -level. According to Fig. 1(b), the phase time constant RC
must be smaller than phase cycle T ( 4STT ) for the better boosting response. According to (14), the discharging
time constant oLCR is asked much larger than ST for the lower output ripple. Now, let’s summarize a string of
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relationships as above, and then the time inequality is obtained as:
oLSS CRTTTRC 4
. (17)
First, according to (15), output capacitor oC is chosen larger for the lower output ripple. Next, based on (17),
pumping capacitor C should be chosen smaller for the faster boosting response. In other words, (17) provides the
design of C . In general, oC from (15) is taken by 5 times or above greater than C from (17). Thus, it is obvious
that oLCR is really much larger than RC8 ( RCCR oL 8 ), so the system’s dominant pole is 1p in (16b) to
dominate the CMPVD stability. Clearly, because 1p is located in the left half of s-plane, the CMPVD is locally
stable no matter what the duty cycle D is set on ( 10 D ). This almost ensures the global stability of CMPVD.
Thus, the CMPVD has an inherent good stability. Here, an additional remark about capacitors is given. In the non-
interleaved SC, output capacitor oC generally has to stand up alone for 1/2 cycle of ST to supply the load. In our
CMPVD, oC has to supply the load alone for 3/4 cycle. Thus, our capacitor oC is needed 1.5 times the value of
output capacitor used in the non-interleaved SC. Really, we need a larger output capacitor oC , but we still benefits
from reducing the number of pumping capacitors.
4.2 PWM control for CMPVD:
Let’s consider the PWM control design for CMPVD. This PWM controller is shown in the lower half of Fig. 1(a).
First, the phase generator needs to generate driver signals of 41 SS as shown the waveforms in Fig. 1(b). Next,
output oi is sent into LPF for high-frequency noise rejection. In the LPF, there is a parameter of cut-off frequency
Lw , which is chosen according to what range the possible high-frequency noises occur at. Certainly, in order to avoid
affecting the system dynamic response, Lw is generally taken by the value bigger than times the value of dominant
pole 1p ( 1pwL ). And then, the filtered output oI is compared with the desired refI so as to produce duty cycle
D via the PWM block. The goal is to keep oI on following refI by the adjustment of D . Fig. 3 deals with the
closed-loop control diagram of CMPVD, and D can be easily determined by oI and refI as:
)II(II4
)I,I( orefD
reforef
PKfD , (18)
where the first term of (18) is set based on (6b) for building a static operating point Dref II4D , i.e. the static duty
cycle D can drive oI to catch up with the desired refI . The second term of (18) is treated as a simple proportional
compensator of gain PK , which is designed for the performance compensation, e.g. rise or setting time. Next, let’s
look at the design of PK . Around the static D , based on Fig. 3 and (8), the closed-loop characteristic equation can
be derived as
01
14
I1)( D
LoL
PoL
closed
wsCR
KCR
ss . (19)
When we consider the dynamic response at the frequency lower than Lw of LPF, (19) can be approximated as:
04
I11)( D
P
oLclosed
KCR
ss . (20)
Then, the closed-loop setting time St is obtained as:
4I13
D
P
oLS K
CRt . (21)
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Based on (21), PK is designed for keeping St be shorter than the desired St~ , and then the minimum proportional
gain can be estimated as
4I~~3
Dmin,
S
SoLPP t
tCRKK . (22)
4.3 Source lower bound:
Based on (6b), oI is not directly affected by source SV . However, when SV is decreasing, it is getting more
difficult to keep MOSFET DS saturated for the current source DI . Of course, SV has a lower bound limit. When
DS is saturated, the current relationship is 2tSGD )(VI VK , where K is the process parameter and tV is the
threshold voltage. The two saturated conditions of DS are: (i) tSGV V , (ii) tDGV V . In Fig. 1(a), DS is
connected with other PMOS as a current mirror. With the help of mI and current mirrors 1a , 2a , the drain current
DI can be assigned to m21 Iaa as a current source. So, the source-gate voltage SGV can be obtained as:
tm21
SGconIVV V
Kaa
, (23)
where conV is defined by the value of SGV for some m21D II aa . From (23), it is obvious that tSGcon VV V
satisfies the first saturated condition. Next, based on (4), 1CV ,
2CV across 1C , 2C can be computed as DS
11C IV001V DRuBA avav , (24a)
DS1
2C I3V2010V DRuBA avav . (24b)
According to Phase IV in Fig. 2(c), the gate and drain voltages of DS can be obtained as
conDSconDCCSconSourceGate VI6V4VI2VVVVVV21
DRDR , oDrain VV . (25a,b)
From (25), the gate-drain voltage DGV is obtained as )VI6V4(VVVV conDSoGateDrainDG DR . (26)
Based on tDGV V and (26), the source lower bound can be estimated under the heavy load of 1D as:
4I)2(6VVVV Dtcono
minS,S
CT rrV , (27)
where minS,V is the minimum supply voltage for current-mode operation. For some output oV , it is obvious that SV
needs to be higher than 4Vo . The larger parasitic resistances ( Tr , Cr ), the higher minS,V is needed. In other words,
the parasitic will narrow down the effective range of supply voltage for current-mode operation.
4.4 Current source selection:
Let’s estimate the upper bound of current source DI . Based on (10a), it needs 4M because is not higher
than 100%. And by combining (10b) plus the heavy load of 1D , DI requires to satisfy
LRS
DV16
I
. (28)
It is notable that (28) is a result without the parasitic, but it provides a simple way to select DI . Clearly, could be
better while DI is selected closer to the value of LRSV16 . When the parasitic are considered, via substituting (6a)
into (27), the precise upper bound of DI can be derived as
)2(24
)V(4V16II tconS
maxD,DCTL rrRV
. (29)
Obviously, the result (29) with the parasitic still fits in with the inequality of (28). By substituting (29) into (10b), the
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maximum conversion ratio maxM can be suggested as
L
CTR
rrM
)2(241
V
VV4 S
tcon
max
. (30)
Here, if Tr , Cr are small enough to be neglected, and further Stcon VVV , then maxM does approach to 4. By
combining (10a) with (30), (9b) with (6) and (29), the maximum efficiency/output power can be also presented as:
L
CTR
rr )2(241
4V
VV1 S
tcon
max
, 2
2tconS
maxo,)2(241
)VV(V4 P
L
CTL R
rrR
. (31a,b)
5. Example of CMPVD:
In this section, a closed-loop two-stage CMPVD with PWM control is designed and simulated by OrCAD tool
(PSPICE) for the various desired outputs, source or loading variation. Then, the CMPVD hardware implementation is
realized and experimented, and all the results are illustrated to verify the efficacy of the proposed scheme. First,
according to Fig. 1(a), the closed-loop CMPVD is designed by PSPICE for circuit simulation. The basic function is to
boost up output oV to 4 times voltage of source SV ( V6.3 ) at most for supplying the standard load LR ( 310 )
via the constant current source DI at the switching frequency Sf ( 20kHz ). The main goal is to keep output oI on
following the desired refI . By using (28), DI is selected at mA180 ( conV = V224.1 ). According to (15), output
capacitor oC is designed at F50 (ESR 01.0 ) for the desired ripple pr~ of %4.0 . Via (17), pumping capacitor
C is selected at F10 (ESR 01.0 ). In the PWM controller, cut-off frequency Lw is taken by about 1000Hz for
high-frequency noise rejection. The proportional gain PK is designed at 8 by using (22), where the desired setting
time St~ is temporarily assigned to ms35 . Based on the closed-loop CMPVD, several simulation cases are discussed
as: (i) steady-state output, output ripple and power efficiency, (ii) output robustness to source disturbances, (iii) output
regulation for loading variations, and (iv) output ripple and power efficiency for the different output and loading.
Finally, the CMPVD hardware implementation is realized and experimented for the cases of steady-state response,
source or loading variation.
(i) Firstly, let’s consider the steady-state response. The CMPVD is simulated for the two different desired refI
of mA33 and mA41 (assigned arbitrarily), and the results are obtained as shown in Fig. 4. In Fig. 4(a)/4(c), it is
observed that the CMPVD is at the stable work on step-up conversion, and the steady-state outputs oI are really
following the desired refI of mA33 , mA41 . Also, the setting time is observed about ms30 , and it is really shorter
than the desired St~ . From Fig. 4(b)/4(d), the output ripples are measured as: rp %276.0 and %237.0 , and they
are really lower than the desired pr~ . And their power efficiencies are measured as: %2.67 and %4.81 . Really,
these two results can verify the theoretical conclusion of (10): the bigger desired refI , the higher oV becomes, and
then M and are rising. Thus, the results show that the CMPVD has the good output conversion and steady-state
performance.
(ii) Secondly, let’s look at the output robustness to source disturbances. Since the source voltage is decreasing
with the running time of batteries, or varying due to bad-quality ones, the robustness to source disturbances must be
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considered. Here, two cases including exponential and sinusoidal source disturbances are illustrated as follows. (a)
Case 1: SV is assumed at DC V6.3 plus exponential drop from V6.3 to V1.3 , as shown in the upper half of Fig.
5(a). The CMPVD is simulated for the desired refI of mA33 , and then the output current is shown in the lower half
of Fig. 5(a). Obviously, oI is still firmly following the desired refI , even though SV has decreased to V1.3 .
According to (27), the source lower bound minS,V is estimated at V7.2 . Here, since the minimum point of SV
( V1.3 ) is not lower than minS,V , the current-mode operation is still running for the stable output current. (b) Case 2:
SV is assumed at DC V6.3 plus sinusoidal disturbance with peak-peak voltage of V4.0 , as shown in the upper
half of Fig. 5(b). The CMPVD is simulated for the desired refI of mA33 , and then the output current is obtained as
lower half of Fig. 5(b). Clearly, oI is still following the desired refI in spite of sinusoidal disturbance. So, the
results show that the CMPVD has good robustness to source disturbances.
(iii) Thirdly, the output regulation for loading variation is discussed. In the running circuit, perhaps the rising
temperature causes short-circuit failure in the load unexpectedly. It results in a big variation of load resistance. Here,
we have two cases to consider as follows. (a) Case 1: LR is assumed about 310 normally, and it suddenly
changes from 310 to 100 at ms40 due to short-circuit failure. After a short period, the load recovers from
the failure, and LR changes from 100 back to 310 at ms80 . Fig. 5(c) shows the transient output current at
the moment of the two-time load variations ( LR = 310100310 ). From this figure, it is obvious that oI
can still hold on about mA28 ( refI 28mA ). (b) Case 2: The same load is added in parallel at ms40 , and then the
added load is removed away at ms80 . In other words, LR is varying as: 310155310 . Fig. 5(d) shows
the output current versus time, and it is found that the CMPVD can still keep oI on about mA28 ( refI 28mA ) in
spite of loading variations. Of course, during the interval of the heavier load ( ms40 ~ ms80 ), it is found that the curve
shape of oI becomes thicker, i.e., the output ripple becomes bigger at this moment. Thus, the closed-loop CMPVD
has a pretty good regulation capability.
(iv) Here, the output ripple and power efficiency are discussed for the different output and loading. With the
consideration of different LR ( 1260~240 ) and refI ( 40mA~mA10 ), the output ripples and power efficiencies
are simulated and arranged as shown in Fig. 6(a)-(b). In Fig. 6(a), the output ripples are decreasing with increasing
LR , and all the values are smaller than %35.0 . The results are sure to agree with (14) derived theoretically, and all
the ripples are really lower than the desired pr~ of %4.0 . In Fig. 6(b), all the power efficiencies for the various refI
are rising with increasing LR . In view of (10), when LR is increasing, M and are rising theoretically. Truly,
the simulated results in Fig. 6(b) correspond to (10).
Finally, the hardware implementation of CMPVD is realized as shown in the photo of Fig. 7. In the figure, there
are two circuit boards including two-stage CMPVD (lower) and PWM controller (upper). The layout sizes are about
cmcm 615 and cmcm 915 respectively, and the circuit wires are made by the prototype circuit-carving machine.
In addition, the type of capacitors we suggested is a radial low-ESR aluminum electrolytic capacitor. Because its
electrolyte film is made very thin, the large capacitance can be realized in the small volume. Here, we used the low-
ERS character of the capacitors for the better performance. Next, the closed-loop hardware circuit is tested practically
under SV = 3.0V , LR = 2.2k , and DI = 40mA , and experimented for the steady-state response, source/ loading
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variation (oscilloscope: Agilent Infiniium 54830B). (i) Firstly, the steady-state response is experimented. Here, the
desired output is selected by refI = 5mA , i.e. oV is expected at 11.0V ( V112.2kΩmA5IV oo LR ). Fig. 8(a)
shows the measured waveforms of oV and D . From the figure, it is obvious that the implemented circuit is at the
stable work on step-up conversion, and the mean value of oV is measured at 10.9965V , and the value of D is
about 49.9% now. The result shows that oV can really hold on about 11.0V , and the value is verified by (6a). In
addition, this circuit has a small output ripple about 2.27%, and the power efficiency is measured as: = %61.83 . (ii)
Secondly, let’s consider the output robustness to source variation. Here, the desired output is refI = 4.5mA , i.e. oV
is expected at 10.0V . Now, for the two different source voltages SV of V0.3 and V7.2 , the waveforms of oV
and SV are measured as shown in Fig. 8(b)-(c). In Fig. 8(b), oV is measured at 10.0522V when SV = V0348.3 .
In Fig. 8(c), oV is measured at about 9.9823V when SV has decreased to V6956.2 . Obviously, oV still holds
on the value of 10.0V though SV changes from V0.3 to V7.2 , i.e. oI still follows the desired refI = 4.5mA
in spite of source variation ( SV = 2.7V3.0V ). (iii) Thirdly, the CMPVD is tested for loading variations. Fig. 8(d)
shows the waveforms of oV and SV when the same load is added and connected in parallel with the output terminal,
and Fig. 8(e) deals with the waveforms of oV and SV when the added load is removed away. In Fig. 8(d), the
abrupt drop of oV is appearing while the same load is added in, even so, oV is still regulated to follow the value of
11.0V ( refI = 5mA ) soon. In Fig. 8(e), the abrupt jump of oV is turning up while the added load is removed away,
but the output regulation can be also achieved soon. So, the experimental results are really illustrated to verify the
efficacy of the proposed scheme.
6. Conclusions
A new closed-loop two-stage CMPVD is presented by combining multi-phase operation and PWM technique for
low-power DC-DC step-up conversion and output current regulation. Some relevant theoretical analysis and control
design are derived. Finally, the closed-loop CMPVD is designed and simulated, and the hardware implementation is
realized and experimented. Here, we summarize the advantages of the proposed scheme as follows. (i) The SC-based
CMPVD scheme needs no magnetic element, so I.C. fabrication will be promising. (ii) This CMPVD can obtain the
high voltage gain by the least number of pumping capacitors, so it will save the device areas. (iii) Since the current-
mode operation is employed here, the steady-state output current is not a function of supply voltage and load, so
source or loading variation will not make immediate response on the output current. So, the CMPVD has the good
output robustness against source or loading variation. (iv) The system dominant pole is located in the left half of s-
plane, so the open-loop CMPVD is locally stable. So, this scheme has an inherent good stability. Of course, the
disadvantages of our scheme are honestly enumerated as: (i) When output oV is much smaller than the maximum
output S4V , the efficiency will be bad. For the better efficiency, it is helpful to choose oV be close to S4V as much
as possible. If not realized, we will change source SV or reduce the stage number n (from 2 to 1) to fit SV2 n for
the output oV as far as we can. (ii) It is not easy to realize the constant current source DI . After all, it is much easier
to obtain a constant voltage source than a current source. In our paper, DI is realized with one current reference and
two current mirrors. With a view to implementation, some current-source devices, e.g. JFET, DMOST… etc, can
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bring out the more convenient approach. In the future, based on this two-stage scheme, it will be a new direction to
develop the generalized structure of multi-stage CMPVD.
Acknowledgment
The research of converter circuit theory and application of Yuen-Haw Chang is financially supported by the
National Science Council of Taiwan, R.O.C., under Grant NSC 98-2221-E-324-024. References [1] Su F. and Ki W.-H. Component-efficient multiphase switched-capacitor DC-DC converter with configurable conversion
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Symp. Circuits and Systems, Atlanta, USA, 1996; 541-544. [13] Zhu G. and Ioinovici A. Steady-state characteristics of switched-capacitor electronic converters. J. of Circuits, Systems and
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Circuits and Systems-I, 2004; 51(10): 1998-2016. [16] Chang Y.-H. CPLD-based closed-loop implementation of switched-capacitor step-down DC-DC converter for multiple
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Fig. 1(a) Closed-loop configuration of CMPVD
Fig. 1(b) Theoretical waveforms of CMPVD
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(a) Phase I, III
(b) Phase II
(c) Phase IV
Fig. 2 Topologies of CMPVD
Fig. 3 Closed-loop control diagram of CMPVD
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Fig. 4(a) Output current ( mA33Iref )
Fig. 4(b) Output voltage ripple ( mA33Iref )
Fig. 4(c) Output current ( mA41I ref )
Fig. 4(d) Output voltage ripple ( mA41I ref )
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Fig. 5(a) Output robustness to exponential source disturbance ( mA33Iref )
Fig. 5(b) Output robustness to sinusoidal source disturbance ( mA33Iref )
Fig. 5(c) Output current while the load failure occurs ( 28mAIref )
Fig. 5(d) Output current while adding/removing the load ( 28mAIref )
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0.000%0.050%0.100%0.150%0.200%0.250%0.300%0.350%0.400%
240Ω
270Ω
300Ω
320Ω
360Ω
400Ω
490Ω
550Ω
610Ω
1100
Ω11
80Ω
1260
Ω
Rip
ple(
%)
RL(Ω)
2MPVD(Ripple)
10mA
20mA
30mA
40mA
Fig. 6(a) Ripple for different output and loading
40.00%45.00%50.00%55.00%60.00%65.00%70.00%75.00%80.00%85.00%
240Ω
270Ω
300Ω
320Ω
360Ω
400Ω
490Ω
550Ω
610Ω
1100
Ω11
80Ω
1260
Ω
Effi
cien
cy(%
)
RL(Ω)
2MPVD(Efficiency)
10mA
20mA
30mA
40mA
Fig. 6(b) Efficiency for different output and loading
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Fig. 7 Hardware implementation of closed-loop CMPVD
Fig. 8(a) Steady-state output and duty cycle ( mA5I ref )
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Fig. 8(b) Output voltage when V0.3VS ( refI = 4.5mA )
Fig. 8(c) Output voltage when V7.2VS ( refI = 4.5mA )
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Fig. 8(d) Output voltage while the same load is added ( refI = 5mA )
Fig. 8(e) Output voltage while the added load is removed ( refI = 5mA )
