IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013 3931

Design and Control for High Efficiency in HighStep-Down Dual Active Bridge Converters Operating

at High Switching FrequencyDaniel Costinett, Student Member, IEEE, Dragan Maksimovic, Senior Member, IEEE,

and Regan Zane, Senior Member, IEEE

Abstract—A control scheme is developed to maximize efficiencyover a wide range of loads for a dual active bridge converter. A sim-ple control circuit using only phase-shift modulation is proposedwhich considers both the converter conversion ratio and switchingdead times in order to maintain high efficiency in the presenceof varying loads. To demonstrate feasibility of the proposed con-trol method, experimental results are presented for a 150-to-12 V,120-W, 1-MHz prototype converter which has 97.4% peak effi-ciency and maintains greater than 90% efficiency over a load rangebetween 20 and 120 W.

Index Terms—Automatic voltage control, DC-DC power con-verters, energy efficiency, zero voltage switching.

I. INTRODUCTION

THE dual active bridge (DAB) converter in Fig. 1 has beengiven considerable interest in recent years for its favor-

able characteristics, including zero-voltage switching (ZVS) ofall devices, near-minimum voltage and current stresses, andintegrated transformer turns ratio [1]–[5]. The DAB architec-ture has, therefore, been selected to operate as an unregulated,150-to-12 V, 120-W, 1-MHz converter. In this paper, the term“unregulated” refers to the output voltage not being controlledto follow a fixed reference but instead being adjusted in closedloop for the purpose of improving efficiency. This type of con-verter can find many applications, e.g., as a bus converter fordc power distribution [6]–[9], where the presence of subsequentpoint-of-load converters removes the need for tight output volt-age regulation. Additionally, the 1-MHz switching frequency,high efficiency, and relatively low output power allow for asmall overall converter size.

Previous studies have shown methods for offline efficiencyoptimization of the DAB converter that are able to set wideZVS range while maintaining low RMS currents through all de-

Manuscript received May 29, 2012; revised August 13, 2012 and September11, 2012; accepted October 31, 2012. Date of current version January 18, 2013.This work was supported by the Colorado Power Electronics Center. Recom-mended for publication by Associate Editor D. Vinnikov.

D. Costinett and D. Maksimovic are with the Department of Electrical, Com-puter, and Energy Engineering, University of Colorado, Boulder, CO 80309USA (e-mail: daniel.costinett@colorado.edu; maksimov@colorado.edu).

R. Zane is with the Department of Electrical and Computer Engineering, UtahState University, Logan, UT 84322 USA (e-mail:regan.zane@usu.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2228237

Fig. 1. DAB architecture. Linear time-equivalent capacitances Cp and Cs tononlinear device output capacitances on the primary and secondary sides areshown explicitly.

vices [10], [11]. Additionally, online efficiency improvementshave been proposed which alter switch control schemes inorder to extend the ZVS range and improve light-load effi-ciency [12]–[16]. In these methods, multiple switch modulationschemes are used across varying load conditions, resulting inimproved efficiency at the expense of increased control com-plexity. This study takes advantage of the unregulated natureof the application by using the ability to dynamically adjustthe output voltage of the converter to extend ZVS range of thehigh-voltage primary devices and achieve high efficiency whilemaintaining a simple phase-shift modulation control strategyacross the entire range of load conditions.

The DAB converter has been analyzed extensively with out-put power above 1 kW and switching frequency below 100 kHz[1]–[3], [10]–[17]. Under these conditions, resonant intervalsresponsible for achieving ZVS occupy a sufficiently small per-centage of the switching period to allow their exclusion fromconverter analysis. However, at higher frequencies and loweroutput power levels, the resonant interval resulting in primary-side ZVS corresponds to a significant portion of the switchingperiod and must be included in the analysis of converter opera-tion. This study seeks to examine the nature of this ZVS intervalacross a full range of load conditions and use the resulting anal-ysis to develop a simple, high-efficiency control strategy for theunregulated DAB converter.

The different operating modes of the converter across vary-ing output power and voltage are analyzed in Section II; a lossmodel across these operating modes is developed in Section III.Section IV employs the loss model to determine the optimal“trajectory” across which the output voltage should be variedin the presence of load variations. Section V details the pro-posed control architecture to dynamically set both the output

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3932 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

voltage and timing parameters. Section VI presents experimen-tal results confirming the feasibility of implementing this con-trol. Section VII concludes this paper.

II. ANALYSIS OF DAB OPERATING MODES

Analysis, taking into account the resonant ZVS transitions,has been completed in [18] under the condition that outputpower is large enough to achieve ZVS of all devices and Vout =ntVg ; i.e., the conversion ratio is equal to the transformer turnsratio. A new solution is developed for the more general caseof Vout = nctrlVg , where nctrl is the converter conversion ratioand is not necessarily equal to the transformer turns ratio nt .For simplicity, a variable MN is defined as the conversion rationormalized by transformer turns ratio

MN =Vout

ntVg. (1)

Important waveforms of converter operation under operatingsteady-state conditions sufficient to provide ZVS of all devicesare shown in Fig. 2. Input and output capacitances of the con-verter are assumed to be large enough such that Vg and Voutare well approximated as constant over a single switching pe-riod. To reduce control complexity, it is desired to operate withphase-shift modulation at all operating points: Q1 and Q4 areswitched simultaneously at near-50% duty cycle with a smalldead time, and Q2 and Q3 are switched 180◦ out of phase. Sim-ilar drive waveforms are used for secondary-side devices, witha controlled phase shift relative to the primary.

A. Mode 1: Operation With β > 0 and Primary ZVS

As shown in Fig. 2, the converter exhibits four intervals perhalf-period, referred to by their corresponding timing labels. Inthe α-interval, a resonant energy transfer between Ll and theoutput capacitance Cp of the primary-side transistors causesZVS on all primary devices. During the β-interval, the maxi-mum available voltage, Vg + Vout/nt , is applied to Ll to quicklyramp the inductor current. The δ-interval consists of a resonanttransition between Cs and Ll , which obtains ZVS of all sec-ondary devices if I2 is sufficiently large. Finally, the ζ-intervalis the main power delivery interval of the converter, in which theinductor current is slowly ramping according the voltage acrossLl , which is nonzero if MN �= 1.

To simplify analysis of the converter, the effect of theδ-interval is ignored when solving the converter, which allowsthe Mode 1 solution to remain valid for both soft- and hard-switching operation of the secondary devices. Due to the highstep-down ratio, it is expected that the high currents of the sec-ondary side are capable of charging and discharging Cs quickly;further, though the analytical ZVS condition is I2 > 0, stray in-ductances on the high-current secondary are significant, causingringing at vs and significantly affecting the switching losses ofthese transitions, as noted in [11] and [12]. Though the inter-val is negligible in the solution of converter operating mode,the losses associated with the δ-interval are not, and will beconsidered in Section III.

Fig. 2. Operational waveforms of DAB for the case where Vout < nt Vg .

The primary resonant interval is analyzed by looking at thenormalized vp − il state plane in Fig. 3. As in [18], normal-ization is employed with respect to Vbase = Vg and Ibase =Vg/R0 , where R0

2 = Ll/Cp is the characteristic impedanceof the primary-side resonant transition. The resulting normal-ized tank inductor current, jl = il/Ibase , and primary-side volt-age, mp = vp/Vbase , are plotted over one full switching periodin the state-plane diagram in Fig. 3, where the resonant an-gle α is the normalized primary dead time, α = tαω0 , withω0 = 1/

√LlCp . This solution applies only under operating

conditions illustrated by the waveforms shown in Fig. 2. That is,when β and J1 are positive, resulting in ZVS of all primary-sidedevices. The solution breaks down when the operating mode ofthe circuit changes, either due to insufficient current Jp to ob-tain ZVS of primary devices, or due to β decreasing below zero.These modes are analyzed in Sections II-B– II-D, with solutiondetails for all four modes summarized in the Appendix.

COSTINETT et al.: DESIGN AND CONTROL FOR HIGH EFFICIENCY IN HIGH STEP-DOWN DUAL ACTIVE BRIDGE CONVERTERS OPERATING 3933

Fig. 3. Operating waveforms of the DAB converter in Mode 1 as both(a) normalized state plane and (b) corresponding time-domain waveforms.

Fig. 4. State plane and time-domain waveforms of the DAB converter in Mode2, with hard switched primary devices. Because M1 < 1, stored energy in Ll

is insufficient to achieve primary ZVS.

B. Mode 2: Operation With β > 0 and Hard-SwitchedPrimary

As output power decreases or output voltage increases, thecurrent Ip available to obtain ZVS of primary devices decreasesaccordingly. From the state plane diagram in Fig. 3, it canbe seen that this boundary occurs when Jp becomes so smallthat r1 < 1 + MN , resulting in a ZVS condition of operatingmode 1

Jp >√

4MN . (2)

which simplifies to the familiar Jp > 2 for nctrl = nt , i.e., whenZVS is obtained with zero voltage across Ll . Below this bound-ary, the inductor current is reduced to zero before full ZVS canbe achieved. If the primary devices are then switched directlyat il = 0 to obtain minimal switching loss, the state plane ofoperation becomes modified, as shown in Fig. 4. A new vari-able M1 is defined, where (1 − M1) is the normalized voltageremaining on Vp just before devices Q1 and Q4 are turned ON.

Fig. 5. State plane and time-domain waveforms of the DAB converter in Mode3 under β < 0 conditions. Because J2 < 0, the converter loses secondary ZVS.

Thus, for M1 = 1, soft-switching is obtained, and the converteroperates at the boundary of this operating mode and Mode 1.Since J1 = 0, J2 ≥ 0 in this mode, soft-switching is obtainedon all secondary devices.

C. Mode 3: Operation With β < 0 and Soft-Switched Primary

In Mode 3, the secondary devices are hard-switched duringthe dead time of the primary devices, resulting in two distinctresonant intervals whose combined effect is to achieve ZVSon the primary-side devices. Because tβ is defined as the timeinterval between the end of the primary dead time and beginningof secondary dead time, the converter can operate with tβ < 0and still remain in positive power flow operation so long astα + tβ + tδ > 0 remains true.

The state plane diagram for this mode of operation is shownin Fig. 5. To match boundary conditions with other operatingmodes, two new angles are defined as

γ = α + β (3a)

φ = −β. (3b)

Additionally, the value (1 − M2) is the normalized absolutevalue of the voltage vp when the secondary side is switched.Switching the secondary during the primary resonant intervalinverts vs , altering the dc voltage biasing the resonant circuitformed by Ll and Cp , as shown by the altered center of reso-nance in Fig. 5. Therefore, the secondary full bridge is commu-tated with previously conducting devices still having positivedrain-to-source currents, causing hard-switching of secondarydevices; this results in an output current which is now negativefor a significant portion of the switching period. The resultingcirculating current allows sufficient energy to be available forsoft-switching primary devices below normal ZVS boundaries.

D. Mode 4: Operation With β < 0 and All DevicesHard Switched

The final operating mode necessary to define converter oper-ation consists of the area bounded by the J2 = 0 boundary of

3934 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 6. State plane and time-domain waveforms of the DAB converter underβ < 0 conditions, with all devices hard switched.

Mode 2 and the J2 = 0 boundary of Mode 3. The converter issolved by setting J2 = 0 for the entire region and again intro-ducing the variable M1 , at which point all primary transistorsare switched with associated energy loss. By its nature, this re-gion consists of some hard switching on all devices. The stateplane diagram for this mode of operation is shown in Fig. 6.

Further operating modes beyond the four detailed here arepossible, but are not addressed in this paper due to their nec-essary exhibition of either decreased efficiency or increasedmodulator complexity.

III. CONVERTER LOSS MODELING

The ramping of the current during the ζ-interval provides op-portunity for optimization of converter efficiency. By setting theoutput voltage less than the reflected input, Vout < ntVg , theconverter is operated with larger Ip for a given output power,allowing more energy to be stored in Ll at the onset of theα-interval. By increasing this energy, the ZVS range of theconverter is extended, but higher RMS currents result. Becausethe intended application does not require strict output voltageregulation, Vout can be adjusted to obtain maximum efficiencyacross all load conditions—decreased to provide additional en-ergy for ZVS and increased to reduce RMS currents. In orderto ascertain a method for adjusting Vout , as well as for selectingoptimal dead times, a loss model is constructed for the DABconverter for the given application. To simplify analysis, lossesare divided into conduction, switching, and core losses.

A. Conduction Losses

In general, all devices in the DAB converter conduct RMScurrent equal to the input, output, tank, or reflected tank cur-rents. Neglecting the need to reflect impedances through thetransformer, this leaves only ig rms , il rms , and io rms to solve.However, in the case where the δ-interval is neglected and trans-former magnetizing current is negligibly small, the reflectedoutput current is equal in magnitude to the tank current il at all

times, yielding

io rms =il rms

nt(4)

and leaving only ig rms and il rms to solve. These values areobtained independently for each operating mode by finding theRMS contribution of the piecewise linear and sinusoidal seg-ments given from the analysis of Section II, and summing themaccording to the method of [19]. On-resistances of all devicesare included and copper losses of all magnetic windings are con-sidered using finite-element analysis to calculate ac resistancesat the switching frequency and its harmonics [20].

B. Switching Losses

Switching losses in the large step-down DAB converter con-sist of power loss due to the output capacitances of all devices,as well as significant losses due to stray inductances on the high-current secondary side. On the primary side, switching loss dueto the output capacitance of the high-voltage devices occurs onlyin Modes 2 and 4 and consists at each switching transition of twodevices turning ON with a voltage Vg (1 − M1) /2 across them,and two devices being forcedly charged in a nonresonant man-ner from Vg (1 + M1) /2 to Vg . Using the analysis in [21], thenonlinear nature of Cp is included by using a voltage-dependentcapacitance Coss,p(v), whose defining function is taken fromthe datasheet of the primary-side device. Power loss attributedto hard-switching of Cp is obtained as

Psw p= 4fsVg

∫ Vg

Vg (1+M 1 )/2Coss,p(v)dv. (5)

Although the δ-interval has little impact on the solution forconverter waveforms, the switching loss associated with thehigh-current secondary is significant, and must be taken intoaccount. To do so, state plane analysis is carried out for the reso-nance between Ll and Cs at the nominal operating point solvedfor in the previous section; this resonance now has new nor-malization parameters Vbase = Vout and Ibase = Vbase/R0,s ,R0,s

2 = nt2Ll/Cs . Additionally, the state plane is traversed

counterclockwise as opposed to the primary resonance. The δ-interval is assumed to have a programmed-constant dead timeequal to tδ0 , where resonance occurs between Cs and Ll if thetank current is positive during any portion of the interval. Ifthe current remains negative during the entire interval, deviceantiparallel diodes will conduct for the duration of the interval,resulting in full hard switching of secondary device capaci-tances. Otherwise, M1s is calculated as the dual of M1 on theprimary side, and the switching losses due to Cs are given by

Psw s= 4fsVout

∫ Vo u t

Vo u t (1+M 1 s )/2Coss,s(v)dv (6)

where the nonlinear MOSFET output capacitance is againconsidered.

Finally, due to the high currents present on the secondary,switching losses due to stray secondary inductances may besignificant. Generally, these inductances arise due to MOSFETpackaging and component layout. If the FETs are turned OFF

COSTINETT et al.: DESIGN AND CONTROL FOR HIGH EFFICIENCY IN HIGH STEP-DOWN DUAL ACTIVE BRIDGE CONVERTERS OPERATING 3935

TABLE IPROTOTYPE CIRCUIT COMPONENTS

TABLE IIPROTOTYPE CIRCUIT PARAMETERS

with positive drain-to-source current, the energy stored in thesestray inductances is left to ring out until dissipated, resulting ina power loss determined by the value of the stray inductanceLx in series with each device and the current at the switchinginstance I2

Psw s l = Lx

(I2

nt

)2

2fs. (7)

Not considered in this analysis are losses in the gate drive cir-cuitry due to the charging and discharging of device gate chargenor losses in the control circuitry. These losses are constantacross all operating points and are thus not subject to constantswitching frequency optimization.

C. Core Losses

Core losses are calculated according to the NSE/iGSE [22],[23] for both the tank inductance and transformer. Transformervoltage stresses are directly given by vs . Voltage stress on Ll

is given by the difference between vp and vs reflected to theprimary. However, both the primary-referenced leakage induc-tance of the transformer Llk and stray inductances Lx of thesecondary side cause potentially significant division of the volt-age applied to the discrete component implementing the tankinductance. Thus, voltage stress on the inductor core is

vl =(

vp − vs

nt

)Ll

Ll + Llk + 2Lx

nt

(8)

and the waveform from (8) is used in the NSE calculation. Theeffect is less significant in the calculation of transformer stresses,so long as the magnetizing inductance is large in comparison toall other inductances.

IV. ANALYSIS OF OPTIMAL EFFICIENCY TRAJECTORY

In order to further examine converter efficiency across a rangeof operating modes and conditions, a prototype converter is usedto obtain numerical results. Details of this converter are givenin Table I, with derived analytical values in Table II and experi-mental results presented in Section VI. Of considerable interestis determining the boundaries of each operating mode from the

converter solution. These regions are defined by the range ofvalues MN and Pout over which the converter solution remainsinternally consistent, i.e., where the solved voltages, currents,and times are of value that do not violate the form of the stateplanes in the respective operating modes. These boundaries aresolved iteratively, with the results shown in Fig. 7(a), and ex-ample waveforms il and vp corresponding to points A–E givenin Fig. 7(b). The converter is designed for a nominal outputvoltage of 12 V, which occurs when Vout = ntVg , or MN = 1.In this case, without output voltage variation, the converter willcross from Mode 1 to Mode 2 at an output power of 110 W, withhard switching of the high-voltage primary occurring at lowerpowers. However, if the output voltage can be dynamically de-creased as the power falls below 110 W, ZVS can be maintainedon all devices as low as 70 W by tracking the boundary be-tween Mode 1 and Mode 2, and on primary devices to zeropower if MN ≥ 0.88 is permitted, corresponding to an outputvoltage as low as 10.4 V. The extension of ZVS range comesat the cost of increased RMS current. By decreasing the outputvoltage, a higher average output current is needed to maintainoutput power; in addition, any move away from MN = 1 causesincreased ramping of inductor current during the ζ-interval, re-sulting in a higher peak-to-average current ratio, though lowerabsolute RMS currents remain possible by increasing MN aboveunity. Thus, following directly the boundary between Mode 1and Mode 2 for the power range 70 W ≤ Pout ≤ 110 W main-tains primary ZVS with the lowest RMS currents possible.

For Pout > 110 W, larger values of MN result in lower RMScurrents, which help quell the dominance of conduction lossesat high current. However, also of significance are the losses dueto stray inductance Lx , and the inductor core losses, both ofwhich increase at high power due to large phase shift and peakcurrents. Losses due to Lx , particularly, decrease at lower MN ,where the inductor current wave shape during the ζ-intervalallows smaller currents in Lx when the secondary is switched.

Below Pout = 50 W, switching and core losses are dominantdue to the low current levels. Mode 4 can be safely assumed tobe a poor choice for low-power operation, as significant switch-ing losses are contributed from both primary and secondarybridges. Further, hard switching of the secondary is preferableto hard switching of the primary, as the high-voltage input leadsto greater losses from hard switching the primary than the sec-ondary as long as

Cp > Cs (Mnnt)2 (9)

which is true for most device combinations when nt is suffi-ciently small, as is the case in this application. Further, trans-former voltage stresses are only marginally affected by converteroperating point, and the lack of a large phase shift limits volt-age stresses on the inductor. Thus, within Mode 3, efficiency isdetermined largely by constant losses, and output voltage hasonly a minor effect on determining losses.

To verify the efficiency analysis, losses in each operatingmode are calculated to produce the efficiency contour plotin Fig. 8. The optimal efficiency trajectory across all outputpowers follows largely the expected trajectory. A second, pro-posed trajectory is also illustrated, which will be shown in the

3936 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 7. Operating mode locations for prototype converter are shown in (a). Shaded regions indicate primary hard switching, while the dashed region indicateshard switching of secondary devices. The points labeled A–E correspond to the time-domain waveforms of (b).

Fig. 8. Efficiency contours of DAB converter in Modes 1–4. The solid lineindicates the highest efficiency trajectory.

following section to have significant advantage in terms of con-trollability. For now, the proposed trajectory can be seen to bevery near to optimal efficiency across the majority of the loadrange, with some deviation at low and high power. The break-down of the losses on both trajectories is compared to experi-mental measurements with the prototype converter in Fig. 9.

V. AUTOMATIC REGULATION OF CONVERTER DEAD TIMES

AND OUTPUT VOLTAGE

Fig. 10 shows the steady-state dead time α, and total phaseshift

Φab = α + β + δ (10)

along with the normalized conversion ratio required to keep theconverter on either the optimal or proposed trajectories in Fig. 8.In order to regulate the converter onto a given trajectory, aneffective controller must adjust both α and Φab to the specifiedvalues at each output power to obtain the correct conversion

ratio. For the optimal controller, the values in Fig. 10(a) are bothnonlinear and widely varying; in order to accurately track thistrajectory, a controller is likely to require measurement of theoutput power and a lookup table to find the appropriate controlparameters for each power. Conversely, the control parametersin Fig. 10(b), for the proposed trajectory, are quite simple. Onthis trajectory, primary dead time α may be approximated asconstant with only minimal detriment to converter efficiency interms of diode conduction or minor partial hard switching orprimary. Further, it can be seen that both the total phase shiftΦab and conversion ratio MN are very nearly linear functionsof Pout and are thus linear with one another. Therefore, it ispossible to construct a controller for this trajectory which doesnot require measuring the output power, but instead enforces alinear relationship between Φab and MN , of the form

MN = KΦab + C. (11)

For this purpose, the controller of Fig. 11 is employed. Thedead times tα and tδ are set to constants of value slightly lessthan one-quarter of the resonant period of Ll and the respectiveprimary and secondary capacitances. The phase shift is thenset through tβ by a feedback loop consisting of sensed values(through ADC gain H) for Vg and Vout , whose difference isthe input to an integral compensator. Around this integrator, asecond loop adjusts the conversion ratio by adding or subtractingboth a constant offset Cφ and an offset proportional to the totalphase shift, KφΦab . This additive approach allows the controllerto be implemented digitally without the need for floating pointdivision, so long as the 1/nt gain on Vout relative to Vg canbe implemented with resistive voltage dividers in the sensingcircuitry. The controller implements a feedback which, throughthe use of an integral compensator, forces steady-state behavior

MN =(

KΦ

HVg

)Φab +

(CΦ

HVg+ 1

)(12)

COSTINETT et al.: DESIGN AND CONTROL FOR HIGH EFFICIENCY IN HIGH STEP-DOWN DUAL ACTIVE BRIDGE CONVERTERS OPERATING 3937

Fig. 9. Analytical loss breakdown for both (a) optimal and (b) proposed trajectories. Note that Psw ,p is not included, as neither trajectory contains points inwhich any hard switching of the primary devices is incurred.

Fig. 10. Plot of control angles α and phase shift (α + β), in radians, plottedacross a range of output powers for both the ideal efficiency trajectory (a) andproposed control trajectory (b) from Fig. 8.

which appropriately matches the desired form from (11). Properoperation of the proposed controller, as well as verification ofthe loss model, is given in Section VI.

VI. EXPERIMENTAL RESULTS

The converter depicted in Table I is constructed. Becausegate drive losses are considered independent of the proposedoptimization, eight DCH0105 isolated supplies are implementedon a separate printed circuit board (PCB) to provide powerto gate drivers with very low common mode coupling. Theconverter power stage occupies roughly 3 in2 on a dual-sidedPCB, without the isolated supplies or control circuitry. Thecontrol loop in Fig. 11 is implemented using a Xilinx Virtex4 FPGA to demonstrate controller operation. A delay line isimplemented to achieve 3.2-GHz modulator resolution, and 12-bit, 15 MSPS ADCs are used to track input and output voltages.Values for Kφ and Cφ are tuned experimentally, and KI is setto stabilize the loop. The PWM and control circuitry occupy

Fig. 11. Proposed control architecture for DAB converter. Linear feedback ofΦa b is used to set conversion ratio MN .

fewer than 5000 gates on the Virtex 4, verifying that the simplecontrol strategy could be implemented on a low-cost IC.

Conversion ratio and efficiency are measured experimentallyusing two calibrated Agilent 34411A multimeters to measureinput current and output voltage, as well as two Fluke 45 mul-timeters for output current and input voltage, while converterwaveforms are measured using a Tektronix DPO2014 oscillo-scope with TCP0030 current probe. A comparison between theobtained experimental efficiencies and the predicted efficien-cies for both the proposed closed-loop control method, and formanually optimized timing parameters and output voltage formaximum efficiency, is given in Fig. 12. Example waveformsand comparison between experimental and analytical state planediagrams are given in Figs. 13 and 14, respectively, for a sin-gle operating point at 80-W output power and 97.4% efficiency.Note that, like the analysis, the efficiency results presented heredo not include the gate drive losses, which are taken from a

3938 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 12. Comparison of analytical solutions (lines) and experimental data(boxes) for optimal and proposed trajectories.

Fig. 13. Sample waveforms for DAB converter with proposed closed-loopcontrol for Pout = 80 W. The converter efficiency is 97.4%.

Fig. 14. Analytical and experimental results for primary state plane of proto-type DAB operating at 80-W output power.

separate supply, and are estimated analytically to be 2.75 W forthe given device combination.

VII. CONCLUSION

This paper considers the analysis and control of an unregu-lated, high step-down, high-frequency DAB converter. Due tothe combination of the high step-down conversion ratio, highswitching frequency, and modest power level, the duration of

the primary-side ZVS interval becomes significant when deter-mining converter operation and is, therefore, analyzed acrossfour different operating modes of the converter which encom-pass the full range of operating conditions and output powers. Aloss model for the converter is developed, and a simple phase-shift modulation control strategy is proposed to operate the con-verter at near-optimal efficiency across all output power levels.Controller function and loss model accuracy are verified exper-imentally with a 1-MHz, 150-to-12 V, 120-W converter whichobtains 97.4% peak efficiency and is able to maintain greaterthan 90% efficiency above 20 W by continuously varying theoutput voltage in the range 10.4 V < Vout < 12.5 V. This smallvariation in output voltage is expected to have minimal impacton the performance of latter conversion stages, but is a topic forfuture research.

APPENDIX

STATE PLANE CONVERTER SOLUTION

A. Solution in Mode 1

Fig. 3 is obtained using geometric arguments to find the av-erage output current. First, the radii r1 are related to give

J1 =√

Jp2 − 4MN . (13)

The conduction angle of the primary resonance is given by

α = cos−1

(

1 − (Jp − J1)2 + 4

2Jp2 + 2 (1 − Mn )2

)

. (14)

Using this same normalization, the conduction angles for the βand ζ intervals can be found from the time-domain plots as

β =J1 + J2

1 + MN(15a)

ζ =Jp − J2

1 − MN. (15b)

Further, the switching period is Ts = 2(tα + tβ + tζ ) fromFig. 2 which, when normalized, becomes

π

F= α + β + δ (16)

with F = fs/f0 . Finally, the averaged output current is obtainedfrom Fig. 2 by integrating the charge transferred to the outputin each interval to obtain

J =〈io〉Ibase

=F

ntπ

(2 +

Jp + J2

2ζ +

J1 − J2

2β

). (17)

B. Solution in Mode 2

In the mode in Fig. 4, J1 = 0 always and M1 is found byexamining the triangle formed between r1 and the mp axis as

M1 =√

Jp2 + (1 − MN )2 − MN . (18)

COSTINETT et al.: DESIGN AND CONTROL FOR HIGH EFFICIENCY IN HIGH STEP-DOWN DUAL ACTIVE BRIDGE CONVERTERS OPERATING 3939

Equations (15a), (15b), and (16) are unchanged, and the equa-tions for α and J become

α = cos−1

(

1 − Jp2 + (1 + M1)

2

2 (M1 − Mn )2

)

(19)

J =〈io〉Ibase

=F

ntπ

(1 + M1 +

Jp + J2

2ζ − J2

2β

). (20)

C. Solution in Mode 3

The converter solution, as shown in Fig. 5, takes the form ofa set of coupled equations derived from the conduction anglesand from the two radii

γ = cos−1

(

1 − (Jp + J2)2 + (1 + M2)

2

2 (1 − Mn )2 + 2Jp2

)

(21a)

φ = cos−1

(

1 − (J1 + J2)2 + (1 − M2)

2

2 (Mn − M2)2 + 2J2

2

)

(21b)

J22 = (1 − MN )2 + Jp

2 − (M2 + MN )2 (21c)

J12 = − (1 − MN )2 + J2

2 + (MN − M2)2 . (21d)

The equation for the ζ interval is slightly modified due to I2occurring before I1 to get

ζ =Jp + J1

1 − MN. (22)

Because β < 0, (16) becomes

π

F= γ + φ + ζ = α + ζ. (23)

Finally, the averaging of the output current yields

J =〈io〉Ibase

=F

ntπ

(2M2 +

Jp − J1

2ζ

). (24)

D. Solution in Mode 4

The converter solution in the mode of Fig. 6 follows closelythat of Mode 3 with J2 = 0 and notable exceptions

φ = cos−1

(

1 − J12 + (M1 − M2)

2

2 (Mn − M2)2

)

(25)

J =〈io〉Ibase

=F

ntπ

(2M2 + 1 − M1 +

Jp − J1

2ζ

). (26)

REFERENCES

[1] R. De Doncker, D. Divan, and M. Kheraluwala, “A three-phase soft-switched high-power-density DC/DC converter for high-power applica-tions,” IEEE Trans. Ind. Appl., vol. 27, no. 1, pp. 63–73, Jan./Feb. 1991.

[2] S. Inoue and H. Akagi, “A bidirectional isolated DC-DC converter asa core circuit of the next-generation medium-voltage power conversionsystem,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 535–542, Mar.2007.

[3] R. Steigerwald, R. De Doncker, and H. Kheraluwala, “A comparison ofhigh-power DC-DC soft-switched converter topologies,” IEEE Trans. Ind.Appl., vol. 32, no. 5, pp. 1139–1145, Sep./Oct. 1996.

[4] R. Lenke, F. Mura, and R. De Doncker, “Comparison of non-resonant andsuper-resonant dual-active ZVS-operated high-power DC-DC converters,”in Proc. 13th Eur. Conf. Power Electron. Appl., Sep. 2009, pp. 1–10.

[5] Y. Ren, M. Xu, J. Sun, and F. Lee, “A family of high power densityunregulated bus converters,” IEEE Trans. Power Electron., vol. 20, no. 5,pp. 1045–1054, Sep. 2005.

[6] M. Ton, B. Fortenbery, and W. Tschudi, “DC power for improved datacenter efficiency,” Lawrence Berkeley Natl. Lab., Berkeley, CA, Mar.2008.

[7] D. J. Becker, Emerson Network Power, “400 Vdc distribution—beyondthe bus,” presented at the Appl. Power Electron. Conf., Feb. 2009.

[8] R. White, “Emerging on-board power architectures,” in Proc. Appl. PowerElectron. Conf., Feb. 2003, vol. 2, pp. 799–804.

[9] R. Miftakhutdinov, L. Sheng, J. Liang, J. Wiggenhorn, and H. Huang,“Advanced control circuit for intermediate bus converter,” in Proc. Appl.Power Electron. Conf., Feb. 2008, pp. 1515–1521.

[10] M. Kheraluwala, R. Gascoigne, D. Divan, and E. Baumann, “Performancecharacterization of a high-power dual active bridge dc-to-dc converter,”IEEE Trans. Ind. Appl., vol. 28, no. 6, pp. 1294–1301, Nov./Dec. 1992.

[11] F. Krismer and J. Kolar, “Accurate power loss model derivation of a high-current dual active bridge converter for an automotive application,” IEEETrans. Ind. Electron., vol. 57, no. 3, pp. 881–891, Mar. 2010.

[12] F. Krismer, S. Round, and J. Kolar, “Performance optimization of a highcurrent dual active bridge with a wide operating voltage range,” in Proc.IEEE Power Electron. Spec. Conf., Jun. 2006, pp. 1–7.

[13] Y. Wang, S. de Haan, and J. Ferreira, “Optimal operating ranges of threemodulation methods in dual active bridge converters,” in Proc. IEEEPower Electron. Motion Contr. Conf., May 2009, pp. 1397–1401.

[14] M. Ordonez and J. Quaicoe, “Soft-switching techniques for efficiencygains in full-bridge fuel cell power conversion,” IEEE Trans. Power Elec-tron., vol. 26, no. 2, pp. 482–492, Feb. 2011.

[15] A. Jain and R. Ayyanar, “PWM control of dual active bridge: Comprehen-sive analysis and experimental verification,” IEEE Trans. Power Electron.,vol. 26, no. 4, pp. 1215–1227, Apr. 2011.

[16] G. Oggier, G. Garcia anda, and A. Oliva, “Modulation strategy to operatethe dual active bridge DC-DC converter under soft switching in the wholeoperating range,” IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1228–1236, Apr. 2011.

[17] G. Oggier, G. Garcia, and A. Oliva, “Switching control strategy to mini-mize dual active bridge converter losses,” IEEE Trans. Power Electron.,vol. 24, no. 7, pp. 1826–1838, Jul. 2009.

[18] D. Costinett, H. Nguyen, R. Zane, and D. Maksimovic, “GaN-FET baseddual active bridge DC-DC converter,” in Proc. Appl. Power Electron.Conf., Mar. 2011, pp. 1425–1432.

[19] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,2nd ed. New York, Springer-Verlag, Science+Business Media, 2001 (Ap-pendix A: RMS Values of Commonly Observed Converter Waveforms).

[20] D. C. Meeker. (2006, Dec.) Finite element method magnetics, version4.0.1. [Online]. Available: http://www.femm.info

[21] D. Costinett, D. Maksimovic, and R. Zane, “Circuit-oriented modelingof nonlinear device capacitances in switched mode power converters,” inProc. IEEE 13th Workshop Control Modeling Power Electron., Jun. 2012,pp. 1–8.

[22] A. Van den Bossche, V. Valchev, and G. Georgiev, “Measurement and lossmodel of ferrites with non-sinusoidal waveforms,” in Proc. IEEE PowerElectron. Spec. Conf., Jun. 2004, vol. 6, pp. 4814–4818.

[23] K. Venkatachalam, C. Sullivan, T. Abdallah, and H. Tacca, “Accurateprediction of ferrite core loss with nonsinusoidal waveforms using onlysteinmetz parameters,” in Proc. IEEE Workshop Comput. Power Electron.,Jun. 2002, pp. 36–41.

[24] D. Costinett, R. Zane, and D. Maksimovic, “Automatic voltage and deadtime control for efficiency optimization in a dual active bridge converter,”in Proc. Appl. Power Electron. Conf., Feb. 2012, pp. 1104–1111.

Daniel Costinett (S’10) received the B.S. and M.S.degrees in electrical engineering from the Universityof Colorado, Boulder, in 2011, where he is currentlyworking toward the Ph.D. degree in power electronicsin the Department of Electrical, Computer, and En-ergy Engineering, Colorado Power Electronics Cen-ter, while assisting with course development at theDepartment of Electrical and Computer Engineeringat Utah State University in Logan, UT.

His current research interests include high-frequency and soft-switching converter design, RF

energy harvesting, mixed signal IC design for power electronics applications,and power electronics design for electric vehicles.

3940 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Dragan Maksimovic (M’89–SM’04) received theB.S. and M.S. degrees in electrical engineering fromthe University of Belgrade, Belgrade, Yugoslavia,in 1984 and 1986, respectively, and the Ph.D. de-gree from the California Institute of Technology,Pasadena, in 1989.

From 1989 to 1992, he was with the Universityof Belgrade. Since 1992, he has been with the De-partment of Electrical, Computer and Energy Engi-neering, University of Colorado, Boulder, where heis currently a Professor and Director of the Colorado

Power Electronics Center. He has co-authored more than 200 publications andthe textbook Fundamentals of Power Electronics (New York: Springer, 2001).His current research interests include mixed-signal integrated circuit design forcontrol of power electronics, digital control techniques, as well as energy effi-ciency and renewable energy applications of power electronics.

Dr. Maksimovic received the 1997 NSF CAREER Award, the IEEE PowerElectronics Society Transactions Prize Paper Award in 1997, the IEEE PowerElectronics Society Prize Letter Awards in 2009 and 2010, the Holland Excel-lence in Teaching Awards in 2004 and 2011, the University of Colorado Inventorof the Year Award in 2006, and the IEEE PELS Modeling and Control TechnicalAchievement Award for 2012.

Regan Zane (SM’07) received the Ph.D. degree inelectrical engineering from the University of Col-orado, Boulder, in 1999.

He is currently a USTAR Professor in the De-partment of Electrical and Computer Engineering,Utah State University (USU), Logan. Prior to joiningUSU, he was a faculty member at the Colorado PowerElectronics Center, University of Colorado-Boulderfrom 2001 to 2012, and a Research Engineer at GEGlobal Research Center, Niskayuna, NY, in 1999–2001. He has recent and ongoing projects in bidirec-

tional converters for dc and ac microgrids, high step-down power converters fordc distribution systems such as high-efficiency data centers, improved batterymanagement systems for electric vehicles, LED drivers for lighting systems,and low power energy harvesting for wireless sensors.

Dr. Zane received the NSF Career Award in 2004 for his work in energyefficient lighting systems, the 2005 IEEE Microwave Best Paper Prize for hiswork on recycling microwave energy, the 2007 and 2009 IEEE Power Elec-tronics Society Transactions Prize Letter Awards for his work on modeling ofdigital control of power converters, and the 2008 IEEE Power Electronics So-ciety Richard M. Bass Outstanding Young Power Electronics Engineer Award.He received the 2006 Inventor of the Year, 2006 Provost Faculty Achievement,2008 John and Mercedes Peebles Innovation in Teaching, and the 2011 HollandTeaching Awards from the University of Colorado. He currently serves as anAssociate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS, Let-ters, and as the Publicity Chair for the IEEE Power Electronics Society.