DESIGN AND SIMULATION OF

SAYEH PROCESSOR USING VERILOG

Submitted by:Akanksha sharma(11507549)

Jasvir kaur(11507996)Shiwani dogra(11500770)

BASIC PROCESSOR Computer Architecture = Instruction Set

Architecture + Computer Organization.

The processor is the computer's brain. It

allows the processing of numeric data,

meaning information entered in binary form,

and the execution of instructions stored in

memory.

The first microprocessor (Intel 4004) was

invented in 1971. It was a 4-bit calculation

device with a speed of 108 kHz. Since then,

microprocessor power has grown

exponentially.

HISTORY In1823, Baron Jons Jackob Berzelius silicon (Si),

which today is the basic component of processors.

1947 John Bardeen, Walter Brattain, and William

Shockley invent the first transistor at the Bell

Laboratories on December 23, 1947.

1971 Intel with the help of Ted Hoff introduces the

first microprocessor, the Intel 4004 on November

15, 1971. The 4004 had 2,300 transistors,

performed 60,000 operations per second (OPS),

addressed 640 bytes of memory. AND GOES

ON………………………….

BASIC PROCESSOR ARCHITECTURE

SAYEH PROCESSOR The SAYEH processor (Simple Architecture,Yet

Enough Hardware) has been designed for

educational and benchmarking purpose.

It possesses minimum hardware with enough

operations possible on that hardware. The processor has 8 and 16-bit instructions. Short

instructions contain shadow instructions, which

effectively pack two such instructions into a 16-bit

word.

sayeh Interface The CPU has a 16-bit

data bus and a 16-bit address bus, also a 16-bit Instruction Set Architecture (ISA).

It has a register file that is used for data processing instructions.

Sayeh Hierarchical structure The processor has a Datapath

and a Controller.

Datapath components are

Addressing Unit, Instruction

Register, Window Pointer,

Register File, Arithmetic Logic

Unit, and the Flags register.

Controller of SAYEH has

eleven states for reset, fetch,

decode, execute, and halt

operations.

Processor Architecture Layout PC- Program Counter, 16 bits R0, R1, R2, and R3. General purpose registers part of the register file,16 bits Reg file - The general purpose registers form a window of 4 in a register file of 8 registersWP- Window Pointer points to the register file to define R0, R1, R2, and R3, 3 bitsIR. Instruction Register that is loaded with a 16-bit, an 8-bit, or two 8-bit instructions, 16 bitsALU. The ALU that can AND, OR, NOT, Shift, Compare, Add, Subtract, and Multiply its inputs, 16 bit operandsZ flag. Becomes 1 when the ALU output is 0C flag. Becomes 1 when the ALU has a carry output

Instruction Set Architecture The OPCODE field is a 4-bit code that specifies the

type of instruction. The Left and Right fields are 2-bit codes selecting R0

through R3 registers in the Register File for destination and/or source of an instruction.

The 16-bit instructions have the Immediate field and the 8-bit instructions do not.

Instruction Set of SAYEH

Processor Architecture

Addressing unit It consists of Program

Counter and Addressing Logic Unit.

The Addressing Logic is a combinational circuit that is capable of adding its inputs to generate a 16-bit output

The program counter is used as a16 bit address storing register.

Status register, Window pointer and Instruction Register Status Register, is

designed as a Carry and Zero bit storing module.

The Window Pointer is a 3-bit register that is used as the base of the Register File .

Instruction Register is a 16 bit register which takes its input from Databus.

Register File The Register File is a 2-

port memory and a file of 8,16-bit registers.

Specific registers for read and write (R0,R1, R2, or R3) in the Register File are selected by its 4-bit input bus coming from the Instruction Register and 3-bit bus from window pointer.

ALU The Arithmetic Logic

Unit module is able to perform –AND, OR, NOT, Shift, Compare, Add,Subtract, and Multiply .

It interacts with Status register to get the current status of flags from previous computation, gets control signals from controller and sends output to Databus.

Alu operations

The Controller Controller of

SAYEH has eleven states for reset, fetch, decode, execute,and halt operations.

It takes the Instruction from IR and decodes it and sends appropriate control signals to the Datapath Module.