Design CMOS PSCD Circuits and Checkers Stuck-At and Stuck...

VLSI DESIGN1998, Vol. 5, No. 4, pp. 357-372Reprints available directly from the publisherPhotocopying permitted by license only

(C) 1998 OPA (Overseas Publishers Association)Amsterdam B.V. Published under license

under the Gordon and Breach SciencePublishers imprint.

Printed in India.

Design of CMOS PSCD Circuits and Checkers forStuck-At and Stuck-On Faults

YEONG-RUEY SHIEH and CHENG-WEN WU *

Department ofElectrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 300

We present in this paper an approach to designing partially strongly code-disjoint(PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in additionto gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only asmall number of extra transistors for monitoring abnormal static currents, coupled witha simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitrynot only can detect the faults in the functional circuit but also can detect or tolerate faultsin itself, making it a good candidate for checker design. Switch and circuit levelsimulations were performed on a sample circuit, and a sample 4-out-of-8 code checkerchip using the proposed technique has been designed, fabricated, and tested, showing thecorrectness of the method. Performance penalty is reduced by a novel BiCMOS checkercircuit.

Keywords: Bridging fault, Built-in current sensor, Built-in testing, CMOS integrated circuit,Concurrent error detection, Integrated circuit testing, Strongly code-disjoint checker, Stuck-atfault, Stuck-on fault, Totally self-checking checker

1. INTRODUCTION

Investigation of totally self-checking (TSC) check-ers dates back at least as far as 1968 [1] Classicalgate-level single stuck-at fault model has beenadopted by most researchers ever since. Becausethe CMOS technology has become the major VLSItechnology, it is necessary to revise the theory(assumptions and conditions) on totally self-check-ing; circuits and checkers in order to facilitatereliable computing[2]. Fault models especially areamong the targets. For example, a combinationalCMOS circuit may be turned into a sequential oneby a stuck-open fault, which apparently cannot be

modeled by a stuck-at fault. Results have beenpresented on the design of CMOS circuits in whichsingle stuck-open faults are detectable by robusttests[3]. Study of various on-line checkers forswitch-level circuits also has been raised due tothe prevalence of the CMOS technology (see,e.g.,[4-1]), with stuck-on faults on fully complemen-

[1tary gates still relatively untouched 1]

Methods have been proposed towards realizingreliable checkers in CMOS circuits. If the checkersare realized using only CMOS domino gates, thenthey will remain self-testing for all single stuck-atand stuck-open faults, and most stuck-on faults[4].It also was claimed that test invalidation due to

* Corresponding author. Tel.’ + 886-35-731154. Fax: + 886-35-715971. E-mail: [email protected].

357

358 YEONG-RUEY SHIEH AND CHENG-WEN WU

circuit delays can be avoided in CMOS dominologic circuits[4]. In the case of dynamic dominoCMOS circuits, detecting a stuck-on fault in thenMOS portion of any CMOS logic gate does notrequire current monitoring, but clocked transistorsand inverters still need current monitoring fortransistor stuck-on faults. In[1], a new techniquefor designing totally self-checking FCMOS circuitsis presented. The technique also is based ondomino logic. A procedure for multilevel CMOSTSC circuit design for Berger Code inputs ispresented, but stuck-on faults are still not dis-cussed[5]. The standard method of applying testinputs and observing outputs may not be appli-cable to detecting transistor stuck-on faults infull CMOS, and to measure steady-state currentsunder proper test vectors to detect these faults,is currently considered the best way. Detectingstuck-on faults in CMOS circuits by [DDQ monitor-ing has been widely reported (see, e.g.,[12-17]).However, in a system where self-checking circuitsand checkers are implemented for concurrent errordetection, off-chip current monitoring is notpractical.A strongly code-disjoint (SCD) built-in current

sensor for CMOS self-checking circuits have beenproposed recently[18]. In this paper, we also discussconcurrent detection of CMOS stuck-on andbridging faults which induce steady current flow.We first review a novel scheme of detectingtransistor stuck-on faults which was proposed byFavalli, et a/. [19]. Then the circuit is modified tofulfill the requirement of concurrent error detec-tion, and is called the analogfault detection (AFD)circuit. We apply this AFD circuit to an m-out-of-2m TSC checker, and show that the combinedm-out-of-2m checker is two-fault tolerant partiallystrongly code disjoint (2-FT PSCD). A simpleinverter chain and a 4-out-of-8 code checker usingthe proposed technique are presented to justify ourconcurrent detection approach. Switch and circuitlevel simulations were performed and discussed.The 4-out-of-8 code checker chip has beendesigned, fabricated, and tested, showing thecorrectness of our method. Performance penalty

reduction by the BiCMOS technology also hasbeen proposed.

2. BASIC DEFINITIONS

Totally self-checking (TSC) checkers are checkingcircuits capable of detecting errors in the functionalcircuit as well as in the checker itself during normaloperation. We denote the input code space as X,and the output code space as Y. Let C(x) stand forthe fault-free circuit/checker function with input x,and Cf(x) for the faulty circuit/checker function atthe presence of fault f which belongs to a givenfault set F. The effectiveness of TSC circuits isbased on two fundamental fault assumptions[21"

1. each failure can be modeled as a member of agiven fault set F;

2. faults occur one at a time, and between any twofaults a sufficient time elapses so that all inputcodewords are applied to the circuit.

DEFINITION 1: A circuit C isfault-secure (FS) for aset of faults F if Vf E F, Vx E X, either Cf(X)

_Y

or Cf(x)= C(x).DEFINITION 2: A circuit C is self-testing (ST) for aset of faults F if Vf F, x X Cf(x)

_Y.

DEFINITION 3: A circuit is totally self-checking(TSC) if it is both FS and ST.

DEFINITION 4: A circuit C is code-disjoint (CD) ifVx X, C(x) Y, and V2 q[ X, C(2) q Y.

DEFINITION 5: A circuit is a TSC checker if it isboth TSC and CD.

Since there is no redundant fault allowed, theTSC conditions are quite stringent. It is difficult fora circuit to satisfy the TSC checker conditions,especially when we consider fault models at theswitch or transistor level. An alternative conditioncalled the TSC goal therefore is proposed[2]. Itstates that given the fault assumptions, a TSCfunctional circuit under test (CUT) always producesa noncodeword (not an incorrect codeword) as the

first erroneous output due to afault in the CUT, andthe fault(s) in the circuit must either be detected or

DESIGN FOR TESTABILITY 359

not interfere with its capability to produce a noncodeoutput for a noncode input from the CUT. Accord-ingly, a new concept was presented for functionalcircuits[2]

DEFINITION 6: A circuit C is said to be stronglyfault-secure (SFS) for a set of faults F if for everyfaultf E F, either

a) the circuit is ST and FS (i.e., TSC), orb) the circuit is FS, and if a new fault in F occurs,

for the resulting multiple fault a) or b) is true.

It is clear that any SFS circuit achieves the TSCgoal under the two fundamental fault assumptionsgiven above. Naturally, SFS circuits are the largestclass of functional circuits, with which a systemmay achieve the TSC goal, with respect tocombinational faults. In[21], a similar definition iscreated for designing a checker, which is acompanion of the SFS definition.

DEFINITION 7: A circuit (usually a checker) C isstrongly code-disjoint (SCD) for a set of faults F ifbefore the occurrence of any fault, C is CD.Furthermore, for every faultfin F, either

a) the circuit is ST, orb) the faulty circuit always maps noncode inputs

to noncode outputs, and if a new fault in Foccurs, for the resulting multiple fault a) or b) istrue.

SCD checkers seem to be the largest class ofcheckers which may achieve the TSC goal so far ascombinational circuits and faults are concerned.However, in[22], an example is given where anetwork of SCD checkers do not achieve the TSCgoal. Therefore, the largest class of checkers thatachieve the TSC goal in fact is the class of stronglyself-checking checkers[22]"

DEFINITION 8" A circuit C is strongly self-checking(SSC) for a set of fault F if before the occurrence ofany fault, C is CD. Furthermore, for every faultfinF, either

a) the circuit is ST and FS (i.e., TSC), orb) the circuit is FS and the faulty circuit always

maps noncode inputs to noncode outputs, and

if a new fault in F occurs, for the resultingmultiple fault a) or b) is true.

A weaker set of conditions (i.e., partially SCDconditions) which is useful for many practicalsituations also was proposed[7]:DEFINITION 8: Let k be the smallest integer suchthat there exists a fault sequencef= (fl, f2,..., fk)which makes Cf(x) lose the SCD property, and nocodeword can detect the multiple faultf. If C is CDand for any integer m, _< m <_ k 1, and any faultsequence f= (fl, f2,..., fm), either Cf(x) is CD orthe fault sequence f is detectable by code inputs,then C is k-fault-tolerant partially SCD (k-FTPSCD).

3. CONCURRENT ANALOG FAULTDETECTION

Analog faults cover all types of failures giving riseto degraded electrical signals, such as voltages,under static conditions. Such a degradation may becaused by the presence of faulty conducting pathsfrom Vdd to GND. Transistor stuck-on andbridging faults, exemplified in Fig. l(a) and (b),respectively, are among those hard-to-detect ana-log faults. In Fig. (a), if the vector (xl, x2)= (0, 1)is applied to the circuit, then there will be aconducting path from Vdd to GND due to thetransistor stuck-on fault, indicated by a circle. Thisconducting path is highlighted in the figure.Consider the circuit shown in Fig. (b), and assumethere is a bridging fault between nodesfl and f2. Ifthe vector (Xl, x2, x3) (0, 1, 1) is applied, then

fl and f2 0 in the fault free case. However, ifthe bridging fault is present, there is a conductingpath (highlighted in the figure) from Vdd to GNDthrough the pMOS network of function fl and thenMOS network of function f2. Any of theseconducting paths from Vdd to GND may causethe output value to be undetermined, i.e., to fallinto the range (Voz,, Vow). Therefore, detecting theanalog faults concurrently will be critical to areliable self-checking systems.


x fl V, ld

IL_

D

(a) (b)

FIGURE (a) A stuck-on fault example. (b) A bridging fault example.

Vdd

net,

net.

Vdd

IEVdd

FIGURE 2 Analog fault detection circuit proposed inB9].

A design-for-testability (DFT) approach forCMOS analog fault detection is depicted inFig. 2[19], which needs a few extra transistors todetect analog faults without using current monitor-ing. A revised DFT scheme for detecting analogfaults for CMOS circuits was also proposedrecently[23], which requires less hardware overhead.

When the control signal is at logic 1, the circuitis in normal operation mode; when is at logic 0(test mode), the error signal E will indicate whetherthere is a fault (logic 0) or not (logic 1). Our firstthought is that this DFT technique might beapplied to on-line self-checking systems. However,for such a system, this scheme should be modified


to satisfy the on-line detection criterion. Fig. 3depicts our analog fault detection (AFD) circuitwhich will be shown to satisfy the concurrent errordetection requirement.By definition, the output of a simplest TSC

checker must be (1, 0) or (0, 1) in the fault-free case.The error indication signal E in the AFD circuit(Fig. 3) takes the possible values of0 and throughthe switches M1 and M4, respectively, which arecontrolled by a signal c12 (to be explained later). Infact, transistors M1 and M4 form an inverter in thefault-free case. When c12 1, the AFD circuit is innormal operation mode;, when c12 0, it is in testmode (and the AFD circuit indicates whether thereis an analog fault or not). Apart from the inclusionof M4 (as compared with Fig. 2), transistors MI,M3, and M4 are designed to have appropriateaspect (IV/L) ratios such that the signal E will be0 (,,0 V) when one of the Vdd-GND paths (i.e.,M1-M3 and M1-M4) is conducting. The influence

of transistor stuck-on and stuck-open faults occur-ring in the AFD circuit of a TSC checker is listed inTable I. Even if M1 is stuck on, the functionalcircuit will still work normally, and the AFD circuitcan still detect a subsequent fault. However, theredoes exists a side-effectmwith the signal c12 high,M4 is on and the path M1-M4 would produce largecurrent. There are only two faults which can not bedetected by the TSC checker, and whose presencedo prevent the AFD circuit from detecting faults inthe functional circuit: one is the stuck-on fault inM2, and the other is the stuck-open fault in M3.

TABLE Influence of faults on the AFD circuit itself

Stuck-on Stuck-open

M undetected; no influence E always 0 (-, 0 V)on checker function

M2 undetected detected by checkerM3 E always 0 (,, 0 V) undetectedM4 E always 0 (,, 0 V) E always (,, 5 V)

Vdd

networ

network

Vdd

network

AFD circuit/

Vdd

network

FIGURE 3 Steady-state current-detection AFD circuit.


Though the checker can not expose these faults, thepresence of any of these faults does not cause theoriginal circuit to malfunction. The checker mayonly lose the ability of detecting the steady-statecurrent of the circuits which connect to the AFDcircuit. Consider the situation that M2 is stuck on(see Fig. 3), and then a subsequent stuck-on fault orbridging fault in the functional circuit occurs. Thisfault consequently induces a static current whichcan not be detected by the AFD circuit because thisAFD circuit has lost its ability of detecting thesteady-state current. Therefore, this checker willlose the SCD ability but still satisfy the 2-FT PSCDcondition.We can add n parallel M3 transistors and n serial

M2 transistors to increase the fault toleranceability, which makes the checker (n + 1)-FT PSCD.However, the circuit area overhead will increaseand the circuit performance will degrade. Theabove two transistors should be laid out carefullyto improve the reliability of the whole system.Except for these faults, all other faults can bedetected on-line by the TSC checker. If thetransistor M2 is stuck-open, this fault is equivalentto the GND line being floating, which will bedetected by the checker. The error signal E 0 ifM3 or M4 is stuck on, because of the ratioedtransistor pairs (M1, M3) and (M1, M4). This is trueeven if subsequently M1 is stuck on or stuck open.There is no conducting path from Vdd to E whentransistor M1 is stuck open, so E gets no ch’ance tobe charged, and will discharge toward 0 V. In anyof these cases, the fault is equivalent to E beingstuck at 0, which obviously can be detected by thechecker. Finally, when transistor M4 is stuck open,the fault is equivalent to E being stuck at 1 (unlessthere is a second fault--a stuck-on fault in thefunctional circuit--turning M3 on), which also canbe detected by the checker. This result is guaran-teed under appropriate control of the periodicsignal c12, which is designed to fulfill the concurrent(on-line) fault detection capability of ourapproach. Signal c12 is functionally the ORedoutput of 1 and 2 (nonoverlapping two-phaseclock). The half cycle when c12= is for normal

operation mode of the system; while the other halfcycle is for test mode. This is illustrated in Fig. 4. InFig. 5, we show the DFT approach for concurrentanalog fault detection, which mixes the test phasesand the normal-operation phases using c12, in a

pipelined system with a two-phase clock.The functional circuit in Fig. 5 is structured in

the form of an iterative pipelined array (e.g., asystolic array) of simple cells. In the figure, thereare two AFD modules which are complementary toeach other. The upp6r AFD module is for detectingstuck-on faults in even-numbered cells, while thelower AFD module is for detecting stuck-on faultsin odd-numbered cells. The two error indicationsignals E and E2 produce 1-0ut-of-2 code outputsin the fault-free case (the reason that a checkerrequires at least two outputs is that a single-outputchecker cannot detect one of the output line stuck-at faults). A stuck-on fault in M3 of the lower AFDmodule turns (El, E2) from (1, 0) into (0, 0) duringthe test phase, which has the same effect when thereis some stuck-on fault in the odd-numbered cellscausing the gate ofM3 to be charged high. The (0, 0)

(b)

FIGURE4 (a) Nonovcrlappingtwo-phaseclock. (b) Signal C12.


bus2

2i

Vdd

Vdd | -E

2t] / Vdd

1

GND

FIGURE 5 A DFT approach for concurrent CMOS analog fault detection.

output therefore indicates that there is a fault in theodd-numbered cells or the lower AFD module.Similarly, the (1, 1) output indicates that there is afault in the even-numbered cells or the upper AFDmodule. Note that we consider only single faults.The correct timing of 12 is shown in Fig. 4(b).Because ofcascading transistor ME (see Fig. 3) withthe original circuit, the computation time may beincreased and noise margin may be narrowed. Toalleviate these problems, it is necessary to give anappropriate aspect ratio to transistor M2.

4. CMOS AND BiCMOS PSCDCHECKER DESIGN

Modularity and regularity are vital circuit designcriteria known to every VLSI designer. Many TSCcheckers designed with modular structures havebeen proposed in the past[24-27]. In this section, weapply our analog fault concurrent detection tech-nique to the unordered-code TSC checkers pro-posed by Smith[24]. Fig. 6 shows the structure of

Smith’s m-out-of-2m TSC checker, which has beenproved to be totally self-checking (with respect tosingle stuck-at faults, of course). Since the m-out-of-2m TSC checkers are constructed by elementarysorter cells (Fig. 6), the m-out-of-2m TSC checkersare modular and regular. This TSC checker candetect all single stuck-at faults at the gate level.However, when the fault model is extended toinclude switch-level faults, this checker will nolonger satisfy the self-testing condition[6]. Kunduand Reddy therefore proposed a design procedurefor two-level or multilevel (but with an evennumber of levels) circuits, which meet the TSCcondition even if the transistor stuck-open faultsare considered[24]. However, the stuck-on faults arenot discussed in their paper.The m-out-of-2m PSCD checker is pipelined by

adding transmission gates in between every twostages (or more, if desired) as shown in Fig. 7. Toalso detect the stuck-on faults concurrently, theAFD circuit can be used jointly with this pipelinedchecker. A two-variable two-rail checker (TRC) isthen cascaded to form the final m-out-of-2m PSCD


il

llow lhgh

m

IL

AND, OR TREEs,Zl 2;2

(a) (b)FIGURE 6 Smith’s unordered-code TSC checker: (a) Schematic diagram of the elementary cell, which is a 2-bit sorter. (b) m-out-of-2m code TSC checker by an array of m (m- l) elementary cells.

m

AND OR TREEs

TRC

(a) (b)FIGURE 7 An m-out-of-2m PSCD checker which can detect transistor stuck-on faults.


checker, as indicated in the figure. If there is astuck-on fault in this checker, and an input patternthat sensitizes a power-ground path, then the AFDcircuit takes on the value (0, 0) or (1, 1) instead of(0, 1) or (1,0), which violates the normal inputrequirement of the TRC, causing its output (zl, z2)to display this error. Therefore, the stuck-on faultis detected.Shown in Fig. 8(a) is one possible small system

design. Since the AFD circuit can not be separatedfrom the functional circuit, slight performancepenalty is unavoidable. This effect however can bereduced by a careful design oftransistor ME (see thenext section). Another design is shown in Fig. 8(b),which is good for larger CMOS circuits. In thefigure, there are (n- 1) AFD circuits: (n-2) of themare for the functional circuit (which is partitionedinto (n-2) blocks), and the last one is for the

original checker circuit. This design improves onthe performance of large circuits by reducing straycapacitance on each bus. More AFD circuitmodules can be used in a similar way to detectanalog faults in a larger system. For example, wecan use another AFD circuit to detect stuck-onfaults in the TRC, circuit (see Fig. 8(c)). Stuck-onfaults on the TRC circuit is undetected, but since itis simple in circuit complexity, we can design itcarefully to avoid analog faults. Without thisassumption, the checker conditions would be hard,if not impossible, to satisfy.To justify the proposed concurrent analog fault

detection approach, an example circuit is designed,laid out, and simulated. Its schematic diagram andmask layout are shown in Figs. 9 and 10,respectively. The functional circuit is a pipelinedinverter chain, which can be consider as a dynamic

Input Functional OutputCircuit, , /

AFD Checker

TRC2

Input FunctionalCircuit

AFD AFD2

’Ou )ut

Checker

TRC

(b)FIGURE 8 CMOS PSCD system designs: (a) For a small circuit. (b) For a large circuit. (c) With the AFD circuit embedded in TRC..


GND

FIGURE 9 An inverter chain with the proposed AFD circuit.

FIGURE 10 The mask layout of Fig. 9.

shift register--a frequently used circuit module inCMOS. The layout is based on a 3 #m CMOStechnology, and the circuit is extracted from thelayout and simulated. The aspect ratio (W/L) ofM1, M3, and M4 are 3/10, 4/2, and 4/2, respectively.Switch-level (Irsim) and circuit-level (Spice) simu-lation results are shown in Fig. 11, which are just aspredicted. In Fig. l(a), signals x and y are theinput and output of the CUT, respectively. Weapply x and monitor its output y, which doesnot change even if there are two consecutive faultsin the circuit, i.e., we can not tell whether the circuit

is faulty or not just by observing primary output y.However, we are able to know that the circuit isfaulty (there are analog faults) by observing theerror indication signals E and E2, which alternateback and forth between (0, 1) and (1,0) in the faultfree case (before 200 ns). If there is a stuck-on faultin transistor M (of Fig. 9), then the signals (E, E2)will take on the values (0, 0) to indicate this analogfault (from 250 ns to 300 ns and 350 ns to 400 ns). Ifthere is a stuck-on fault in transistor M4 (of Fig. 9),then the signals (E, E2) will take on the values (1, 1)to indicate this analog fault (from 450 ns to 500 ns


and 550ns to 600ns). From 600ns to 800ns, thiscircuit is fault free again. Fig. 11 (b) shows the Spicesimulation result corresponding to Fig. l(a), inwhich the upper half shows the result for 0 ns to400 ns, while the lower half shows that for 400 ns to800 ns. It should be noted that stuck-at faults in theinverter chain cannot be detected at (El,E2),however, they will be exposed at (Z1, Z2) as shownin Fig. 8.A 4-out-of-8 code checker chip employing the

proposed scheme has been designed, simulated,

(b)

FIGURE 11 Simulation results: (a) Switch level. (b) Circuitlevel.

fabricated, and tested. The 2062-transistor chip isfabricated by an inexpensive 3 #m CMOS technol-ogy, which runs at about 1.7 MHz, and occupies anarea of about 25 mm2. We received 20 parts fromCIC (Chip Implementation Center, a serviceorganization in Taiwan similar to MOSIS in theUS), among which 85% worked as predicted by thesimulation results. The failed parts are due tofabrication defects (there is no test service per-formed by CIC or the foundry). Fig. 12 shows thelayout plot of the PSCD ctiecker chip, in whichthere are eight 4-out-of-8 code PSCD checkers.The process we used for the experiment is slow, butour purpose was to justify the functionality of ourchecker scheme and to see how much performancepenalty we will suffer from the extra nMOStransistor appended to the pull-down path. Ourmeasurement result is consistent with the Spicesimulation as shown in Fig. 13, in which we tracethe rising and falling transitions of the originalcircuit (in solid line) and the circuit with the AFDscheme (in dashed line). There is no difference inrising transition as expected, but in falling transi-tion there is an extra 10% delay time when theAFD circuitry is included. This penalty obviouslyis unavoidable. It however can be reduced by usingthe BiCMOS technology. Fig. 14 shows this newcircuit.Although the performance degradation also can

be reduced by a careful layout of transistor M2 (inFig. 3), it has many side-effects. Owing to the speeddegradation, the functional and checker circuitsmay need a number of AFD circuits to detectsteady-state current produced by a stuck-on tran-sistor. Maly and Patyra pointed out that a bipolarjunction transistor (BJT) device, rather than a MOSdevice, should be used as a voltage drop element ina current sensor[16], since BJTs have high switch-ing speed and low voltage drop (in the saturationmode). In our design, the transistor M2 can bereplaced by an npn BJT (see Fig. 14). The circuitperforms the same logic function, and the systemspeed is improved. We also can replace the MOStransistor M3 (in Fig. 3) with a BJT (see Fig. 14),which reduces the testing time. Fault models for


FIGURE 12 Chip layout of the fabricated 4-out-of-8 code PSCD checker.

BJTs are assumed to be transistor stuck-on andstuck-open faults, which are similar to those forMOS transistors. Therefore, the AFD circuits inFig. 14 preserves the PSCD property.To evaluate our new scheme, both the circuit

with AFD and the circuit without AFD (theoriginal circuit) are simulated. Spice simulationresults are shown in Fig. 15, in which the solid lineis for the circuit without AFD, and the dashed lineis for the circuits with AFD. The upper half of thefigure shows that the difference between the circuitwith AFD and the original circuit is very small(as compared with Fig. 13). Though the circuit

performance is greatly improved, the power con-sumption also increases. Static power is consumedduring the time period when the control signal el2 ishigh (see the lower half of the figure, which showsthe current levels). Therefore, if the resistance of Ris low (e.g., 4.3 KY), the circuit will consume largepower. The power consumption can be reduced toapproximately the power consumption of theoriginal circuit, shown in Fig. 16, if the resistanceR is increased (e.g., 86 Kf). The resistance needsnot be linear, so we can use a MOSFET for thispurpose. There is a trade-off between powerconsumption and area overhead.


FIGURE 13 Delay comparison between the original circuit and that with the AFD scheme.

T Vdd Vdd

net rk

networ

E

Vdd

AFD circuit

GND

FIGURE 14 Steady-state current detection circuit using BiCMOS technology.


FIGURE 15 Simulation result: R 4.3 KfL

SPit( IrlL CRRTD FOR CIRCUIT WITHOUT Aro COMPRRO WITH AFDlg-RPRgq lOtqGI 1

.o :-:-’---’".’:. . j|_..t.. ".:"

I.o.: .... .._Ol.O?OgU

Ii....

_al cvs,ol

VSND.OH

,. ,, g,, ,,,,,, ,,,,,O.ON TXM(OLIN) 66e.oN

FIGURE 16 Simulation result: R 86 Kft.

5. CONCLUDING REMARKS

We discuss concurrent detection of’ CMOS stuck-on and bridging faults which induce steady currentflow. We first review a novel scheme of detectingtransistor stuck-on faults which was proposed byFavalli, et al. [19]. Then the circuit is modified to

fulfill the requirement of concurrent error detec-tion, and is applied to an m-out-of-2m TSCchecker. We show that the combined m-out-of-2mchecker is two-fault tolerant partially strongly codedisjoint (2-FT PSCD). A simple inverter chain ispresented to justify our concurrent detectionapproach. Switch and circuit level simulations are


performed, and chips are fabricated and tested,which shows the correctness of the method, andalso shows that performance penalty can not beavoided.An important factor that affect the performance

is that the parasitic capacitance from the virtualground (bus in Fig. 3) and true ground is large dueto the diffusion-substrate capacitances of all thepull-down nMOS transistors. If the circuit speed isuntolerable due to this effect, the functional circuithas to be further divided into smaller subcircuits,i.e., with separate shorter busses and multiple AFDcircuits. This becomes a tradeoff between clockperiod and chip area.

In a similar work[18], performance degradation isreduced by connecting in parallel with the currentsensor a large diode. We propose an alternativesolutionmBiCMOS circuits are used to reduceperformance degradation. Although this methodcan be used only with the BiCMOS process (whichhave become common in the industry), the checkercircuit is simpler. The current sensor in[18] is SCD,while ours is PSCD. Both methods require specificclocking schemes.

Acknowledgement

This work was supported in part by the NationalScience Council, R.O.C., under Contracts NSC80-0404-E007-33 and NSC81-0404-E007-118.

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Authors’ Biographies

Yeong-Ruey Shieh received the M.S. degree inelectrical engineering from National Tsing-HuaUniversity, Taiwan, in 1992, where he currently isa Ph.D. student. His current interests include VLSItesting, fault tolerance, and VLSI design for signalprocessing applications.

Cheng-Wen Wu received the BSEE degree in1981 from National Taiwan University, Taipei,Taiwan, and the M.S. and Ph.D. degrees, bothin electrical and computer engineering, in 1985and 1987 respectively, from the University ofCalifornia, Santa Barbara. From 1985 to 1987 hewas a post graduate researcher at the Center forComputational Sciences and Engineering atUCSB. Since 1988 he has been with the Depart-ment of Electrical Engineering, National TsingHua University, Hsinchu, Taiwan, where he iscurrently a professor. Dr. Wu’s interests includeVLSI testing and design for testability, and designof high performance application-specific VLSIcircuits and systems. He is a senior member ofIEEE.

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Design CMOS PSCD Circuits and Checkers Stuck-At and Stuck...

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