Design Considerations for Connecting Multiple DSAs in a … · GNDe 9 GNDg 11 GNDh 12 GNDi 13 GNDj...

Design Considerations for Connecting Multiple DSAs in a Cascaded-Series ConfigurationApplication Note 79

©2018, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121

SummaryThis application note provides the design considerations needed to connect multiple digital step attenuators (DSAs) in a cascaded-series configuration. In many applications, customers want to achieve a high attenuation value, and this higher value can be achieved by cascading multiple DSAs in series. In general, the cascaded DSAs are placed close together in a small space with shared control inputs and VDD connections. A total attenu-ation value above 50 dB can be difficult to achieve without careful attention to the layout and design consider-ations. These layout and design considerations are detailed in this application note

IntroductionThe two main considerations when cascading DSAs are the conducted leakage and radiated leakage across the circuit. Both types of leakage require that the circuit layout and the circuit interconnections be carefully defined. These leakage issues are detailed below.

Page 1 of 11 DOC-91980-1 – (12/2018)www.psemi.com

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Application Note 79Design Considerations for Connecting Multiple DSAs

Isolation Between the Digital Control or VDD Connections and the DSA RF PortsConducted LeakageConducted leakage is the leakage of the RF signal across the circuit connections. In this case, we are consid-ering the leakage from the VDD or digital connections to the RF ports. These connections are often shared between cascaded DSAs and can be routes of leakage between the cascaded DSAs, which can in turn disturb each DSA’s attenuation accuracy. Figure 1 shows the isolation between digital lines and RFx ports for the pSemi PE43711 DSA. The result is almost 40 dB of isolation across the whole band of operation. This high level of isolation is typical of pSemi products. The same isolation is expected for the other digital pins such as control lines and serial interfaces as shown in Figure 2.

From Figure 1, we can assume the VDD to RF isolation is approximately 40 dB in general. We cannot assume that this isolation is purely due to the conducted isolation of the part. We need to exclude any leakage caused by inadequate radiated isolation.

Figure 1 • PE43711 VDD to RF Ports Isolation

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Isol

atio

n (d

B)

Frequency (MHz)

Min Attn_ISO_RF1_VDD Min Attn_ISO_RF2_VDD

Max Attn_ISO_RF1_VDD Max Attn_ISO_RF2_VDD




Radiated LeakageFigure 2 shows the isolation from the VDD to the RF port when RF shields are placed over the devices. The figure also includes isolation measurements for all of the other digital control lines (SI,CLK,P/S and LE) used in serial bus control. The parallel DSA control inputs (D1–D7) are all grounded. From this result, it is apparent that the shield has only a limited effect on the isolation. We can now conclude that the measured leakage from the control and VDD lines is mostly conducted rather than radiated.

Figure 2 • Isolation Between RFx and DC Lines—with Shield

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Frequency (MHz)

CLKtoRF1 CLKtoRF2 LEtoRF1 LEtoRF2 SItoRF1

SItoRF2 PStoRF1 PStoRF2 VDDtoRF1 VDDtoRF2

DOC-91980-1 – (12/2018) Page 3 of 11www.psemi.com



In-line Filter DesignBy applying a suitable filter to the VDD and control lines, we can show that the leakage is dominated by the conducted leakage via the control and VDD line. Figure 3 shows the response and implementation of a suitable low-pass filter used in-line for all the control and VDD connections.

Figure 4 shows the resultant isolation from the control and VDD lines to the RFx ports with the in-line filters placed in circuit and with a shield in place. It shows an isolation improvement of 20 to 30 dB with a minimum isolation of 65 dB. This result means that the minimum conducted isolation between any two RF ports via the control or VDD pins should now be now >120 dB.

Figure 3 • Low Pass Filter and S-parameter

Figure 4 • Isolation between RFx and DC Lines with In-line Filter and Shield

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Frequency (MHz)

CLKtoRF1 CLKtoRF2 LEtoRF1 LEtoRF2 SItoRF1

SItoRF2 PStoRF1 PStoRF2 VDDtoRF1 VDDtoRF2




Final DesignWith this information, we can now design a layout for the cascaded DSA board. This layout is shown in Figure 5 with the schematic, including the in-line filters, shown in Figure 6.

Figure 5 • Four-Cascaded PE43712 DSA Board




Figure 6 • Four-Cascaded PE43712 DSA Schematic—Serial Addressable Control

PS1 PS3 PS4PS2VDD1

VDD2 VDD3 VDD4

VDD

VDD1 VDD2 VDD4VDD3

CLK1 CLK2 CLK3 CLK4

SI1 SI2 SI3 SI4

LE1 LE2 LE3 LE4PS4

RFINRFOUT

C3591nH

C3468pF

U3PE43712

GNDa1

VDD2

P/S3

A04

GNDb5

GNDc6

RF17

GNDd8

GN

De

9

GN

Dg

11

GN

Dh

12

GN

Di

13

GN

Dj

14

GN

Dk

15

GN

Dl

16

CLK24

LE23

A122

A221

GNDo20

GNDn19

RF218

GNDm17

C0.

2532

C0.

531

C1

30

C2

29

C4

28

C8

27

C16

26

SI

25

GN

Df

10

PA

D33

U2PE43712

GNDa1

VDD2

P/S3

A04

GNDb5

GNDc6

RF17

GNDd8

GN

De

9

GN

Dg

11

GN

Dh

12

GN

Di

13

GN

Dj

14

GN

Dk

15

GN

Dl

16

CLK24

LE23

A122

A221

GNDo20

GNDn19

RF218

GNDm17

C0.

2532

C0.

531

C1

30

C2

29

C4

28

C8

27

C16

26

SI

25

GN

Df

10

PA

D33

C3291nH

C3168pF

C3622pF

U5PE43712

GNDa1

VDD2

P/S3

A04

GNDb5

GNDc6

RF17

GNDd8

GN

De

9

GN

Dg

11

GN

Dh

12

GN

Di

13

GN

Dj

14

GN

Dk

15

GN

Dl

16

CLK24

LE23

A122

A221

GNDo20

GNDn19

RF218

GNDm17

C0.

2532

C0.

531

C1

30

C2

29

C4

28

C8

27

C16

26

SI

25

GN

Df

10

PA

D33

U4PE43712

GNDa1

VDD2

P/S3

A04

GNDb5

GNDc6

RF17

GNDd8

GN

De

9

GN

Dg

11

GN

Dh

12

GN

Di

13

GN

Dj

14

GN

Dk

15

GN

Dl

16

CLK24

LE23

A122

A221

GNDo20

GNDn19

RF218

GNDm17

C0.

2532

C0.

531

C1

30

C2

29

C4

28

C8

27

C16

26

SI

25

GN

Df

10

PA

D33

C2722pF

C2691nH

C2568pF

C3322pF

C2991nH

C2868pF

C3022pF

Filters for VDD

Same filters can be applied to control lines.




Using this board, we can demonstrate the effect of the in-line filters and the RF shields on a typical cascaded DSA attenuation setting of 80 dB.

These results clearly show the effect of the filters on the DSA attenuation accuracy across all frequencies. Figure 8 also shows the effect of the RF shields at the higher frequencies.

Figure 7 • Attenuation vs. Frequency (@ 80 dB Attenuation) With and Without In-line Filters

Figure 8 • Attenuation vs. Frequency (@ 80 dB Attenuation) With and Without RF Shields

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ion

(dB

)

Frequency (MHz)

80dB Attn Filtered_Shield 80dB Attn NoFiltered_Shield

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(dB

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Frequency (MHz)

80dB Attn Filtered_Shield 80dB Attn Filtered_NoShield




An important factor must be addressed when implementing in-line filters on the control lines.The designer must ensure that the filters do not degrade the clock and data signals. The clock and data rate must be carefully considered when implementing the filters. Figure 9 shows the effect of the in-line filter on the 1 MHz clock signal, which shows the clock still transitions correctly.

Figure 9 • Serial Interface Clock 1 MHz Waveforms With and Without In-line LPF

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0.5

1

1.5

2

2.5

3

2.35 3.35 4.35 5.35 6.35 7.35 8.35 9.35 10.35 11.35

Volta

ge (V

)

Time (µS)

Filtered_Shield NoFiltered_Shield Digital Input High_Min




ResultsFigure 10, Figure 11, and Figure 12 show three plots of attenuation over the full attenuation ranges of all four DSAs with 5 dB steps from 0 dB to 125 dB and the maximum attenuation state of 127 dB. These figures show the effect of the RF shields and the in-line filters, and the final result with both in place. The red line is the measurement of the VNA noise floor.Figure 10 • Attenuation vs. Frequency (5 dB step); No Filter with Shield

Figure 11 • Attenuation vs. Frequency (5 dB step) with In-line Filter Without Shield

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Frequency (MHz)

0dB 5dB 10dB 15dB 20dB 25dB



90dB 95dB 100dB 105dB 110dB 115dB

120dB 125dB 127dB VNA_NoiseFloor

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Frequency (MHz)




90dB 95dB 100dB 105dB 110dB 115dB





These results clearly show that both the in-line filter and RF shields are important for a successful design using cascaded DSAs when trying to achieve the highest attenuation across the whole frequency of operation. Only above 5 GHz does leakage around the DSA cause the attenuation to fall below that expected.

Figure 13 shows the board RF input to RF output isolation with the filters and RF shields in place but without the DSAs assembled to the board. This result shows that there is still some leakage across the board. To address this leakage, attention should now be focused on the adoption of vigorous EM simulations for the coplanar or stripline design, ground plane isolation, and the number and size of ground plane vias.

Figure 12 • Attenuation vs. Frequency (5 dB Step) with Both In-line Filter and Shield

Figure 13 • Attenuation vs. Frequency (5 dB Step)—Filtered_Shield

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(dB

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Frequency (MHz)




90dB 95dB 100dB 105dB 110dB 115dB


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Frequency (MHz)

0dB 5dB 10dB 15dB 20dB




100dB 105dB 110dB 115dB 120dB

125dB 127dB VNA_NoiseFloor NoDSA_barePCBonly

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(dB

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Frequency (MHz)





100dB 105dB 110dB 115dB 120dB

125dB 127dB VNA_NoiseFloor NoDSA_barePCBonly



Application Note 79Design Considerations for Con-

necting Multiple DSAs

ConclusionWe have shown it is possible to produce a high value attenuator by cascading several DSAs in series. However DC and control line isolation and radiative isolation should be carefully considered to achieve the highest atten-uation. Isolation can be improved with low pass filters on the shared the digital lines provided that the digital signal integrity is also considered. Radiative isolation can be improved with RF shields and inner layer design of the RF signals path. If customers need very high attenuation levels > 95 dB, the isolation of the board itself should be considered carefully using EM simulation to ensure better isolation of the bare board.

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Sales ContactFor additional information, contact Sales at [email protected].

DisclaimersThe information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirelyat the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’sproducts are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support orsustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur.pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications.

Patent StatementpSemi products are protected under one or more of the following U.S. patents: patents.psemi.com

Copyright and Trademark©2018, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registeredtrademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries.

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SummaryIntroductionIsolation Between the Digital Control or VDD Connections and the DSA RF PortsConducted LeakageRadiated Leakage

In-line Filter DesignFinal DesignResultsConclusion

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Design Considerations for Connecting Multiple DSAs in a … · GNDe 9 GNDg 11 GNDh 12 GNDi 13 GNDj...

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