NANOELECTRONICS

Design, fabrication and characterisation of strainedSi/SiGe MOS transistors

S.H. Olsen, K.S.K. Kwa, L.S. Driscoll, S. Chattopadhyay and A.G. O’Neill

Abstract: Strained Si/SiGe heterostructure MOS transistors offer great promise for nanoscaleCMOS technology. This paper reviews these high performance devices and the challengesassociated with their integration into conventional CMOS processes. Simulation results at a deviceand circuit level show that n-channel MOSFET performance can influence circuit speed to agreater extent than p-channel devices. Consequently the experimental work discussed is focused onrecent progress in the optimisation of strained Si/SiGe n-channel MOSFETs. Simulation predictsthat dual channel CMOS architectures offer the greatest performance advantages for both n- andp-channel MOSFETs. However, experimental evidence suggests that a single channel CMOSarchitecture may be a more pragmatic choice, given the material and processing complexitiesinvolved. The optimum SiGe alloy composition for virtual substrate based devices is discussed.Electron mobility is shown to peak in strained Si channels fabricated on relaxed Si0.75Ge0.25, yetwafer yield is compromised for virtual substrate compositions incorporating Ge contents above15%. Optimum strained Si/SiGe device design is therefore shown to be highly dependent on thedevice parameter to be optimised, and specific processing conditions.

1 Introduction

The rate of technological advances in the semiconductorindustry has followedMoore’s Law for almost four decades[1]. Figure 1 depicts the historical trends, which wereanticipated by GordonMoore in 1965. Geometric scaling ofMOSFET transistor dimensions has been the primarymethod used to increase transistor speed and simulta-neously reduce the cost per function. State-of-the-artMOSFETs are now being fabricated with effective gatelengths of only a few tens of nanometres, pushingconventional Si-based technologies into the nanoelectronicsregime. Figure 1 shows that for recent technologygenerations it has been necessary to reduce gate lengthsmore aggressively, leading to new challenges in modifyingother device dimensions which must also be scaledaccordingly [2]. Junction depths and gate oxide thicknessmust both be reduced, while substrate doping is increased inorder to minimise MOSFET short channel effects. Thethinner gate oxides produce a higher degree of Si/SiO2

interface roughness [3]. This, together with higher verticalfields experienced by inversion layer channel carriers, due tohigher substrate doping, leads to increased carrier scatteringand ultimately lower channel mobility. Alternatives to SiO2

as the gate insulator are under development, which achievelow effective oxide thickness by virtue of high permittivity.Unlike SiO2, which is grown, these ‘high-k’ dielectrics areusually deposited. This results in poor interface properties atthe Si surface, leading to additional reductions in channelmobility. New channel materials with advanced electronic

properties are therefore required in order for CMOS toprogress deeper into the Si nanoelectronics regime andmaintain the rate of performance increases demanded bythe International Technology Roadmap for Semiconduc-tors, ITRS [4].

The strained Si/SiGe material system uses the 4.2%difference in the atomic spacing of Si and Ge atoms tocreate nanoscale strain-engineered devices. Electron mobi-lity is enhanced in strained Si compared with bulk Si due totensile strain splitting the six-fold degenerate conductionband valleys and causing the resulting two-fold band withlower energy and reduced in-plane effective mass to bepreferentially filled. Hole transport is improved in bothtensile strained Si and compressively strained SiGe

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The authors are with the School of Electrical, Electronic and ComputerEngineering, University of Newcastle, Newcastle, NE1 7RU, UK

r IEE, 2004

IEE Proceedings online no. 20040995

doi:10.1049/ip-cds:20040995

Paper first received 4th December 2003 and in revised form 27th May 2004.Originally published online: 26th October 2004

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004 431

compared with bulk Si. The energy band offsets betweenstrained and unstrained Si, Ge and SiGe alloys allow theconfinement of carriers in high mobility epitaxial layers.Using the high mobility layers as the channel for MOSFETdevices therefore leads to increased device performancewithout the need for expensive conventional scalingstrategies. Furthermore, combining the strained Si/SiGesystem with scaledMOSFET technologies (to at least 70nmgate lengths [5]) has been shown to offer additionalperformance gains. While bipolar and BiCMOS marketshave benefited tremendously from the introduction ofstrained SiGe, a much greater proportion of the semicon-ductor industry arises from CMOS products: in 2000, 79%of the market was attributed to CMOS products, comparedwith 11% for bipolar and BiCMOS applications [6]. Thus,by exploiting the higher mobility of both electrons and holesin the strained Si/SiGe layers for MOS technology, evengreater performance advantages and financial gains arepossible.

2 Design

The critical thickness of a strained layer imposes severalrestrictions on the optimum device design and processing ofstrained Si/SiGe MOS transistors. Matthews and Blakesleefound that if a strained layer is grown above a criticalthickness hc, the material becomes unstable and strainrelaxation can occur [7]. The critical thickness is dependenton strain in the layer and for strained Si grown on relaxedSi1-xGex is given by [8]

hc ¼ 2:2969x�1:2326 ð1ÞStrain may also relax if the material is exposed to very highthermal budgets. For strained Si surface channel MOS-FETs, the critical thickness has several implications.Following (1), a strained Si layer can be grown in a stablestate up to approximately 10nm on relaxed Si0.70Ge0.30.However, a minimum channel thickness of approximately5nm is required for efficient carrier conduction [9], andboth wafer cleaning and gate oxidation consume surface Si.Ge diffusion from the underlying SiGe layer will also occurduring high temperature processing and act to reduce the Sichannel thickness. Ge diffusion into the Si channel canadditionally limit mobility enhancements through degrada-tion of the heterostructures, alloy scattering [10–12] andthrough deterioration of the gate oxide should Ge reach thestrained Si surface [13], since Ge will not becomeincorporated into thermal oxides [14]. Bean et al. haveshown that a ‘metastable’ region exists, whereby strainedmaterial can be grown above the critical thickness [15].However, high thermal budgets cause metastable layers torelax. This is especially important in SiGeMOS technology,where a higher thermal budget process is required comparedwith bipolar and BiCMOS technologies. In addition tolosing the benefits of the enhanced mobility in strained Si,relaxation of the material occurs through the formation ofmisfit dislocations [7], which can act as leakage paths [16]and scattering centres [17], or surface roughening, furtherdegrading the material quality.

Early simulation work investigated the potential advan-tages offered by strained Si/SiGe devices assuming that theincreased mobilities measured experimentally in strained Si/SiGe MODFET devices [18] could be realised in MOSFETdevices [19, 20]. By using strained Si/SiGe layers as thechannel material of MOS devices, a new universal relation-ship was shown to exist which shows improved device speedcompared with bulk Si MOSFETs without compromisingdevice electrostatic integrity. A variety of technology nodes

and Si/SiGe layer architectures, including surface andburied channel designs, are presented in Figure 2 [21, 22].The device speed is represented by gm/WC, where gm istransconductance, the gate width is W and C is the gatecapacitance per unit area, while electrostatic integrity isrepresented by drain induced barrier lowering, DIBL.

The higher carrier mobility possible with strained Si/SiGeresults in increased drain current and consequently higherdevice speed. Alternatively the higher drain current can betraded-off against either reduced operating voltage tominimise power dissipation in the circuits or device width,resulting in both lower circuit delays through shorterinterconnect tracks and smaller chip area, which mayincrease the number of chips per wafer.

Simple MOSFET channel layer designs, using pseudo-morphic growth of compressively strained SiGe on bulk Si[23], enhances p-channel drain current and allows a morebalanced CMOS; conventionally the widths of p-MOSFETtransistors are larger than those of n-MOSFETs tocompensate for the significantly lower hole mobilitycompared with electron mobility in bulk Si. Sucharchitectures therefore enable an increase in the density oftransistors per chip, but do not offer any benefits to n-MOSFET devices. Both n- and p-channel devices can beimproved using a virtual substrate of relaxed SiGe to createboth tensile and compressive layers. Several trade-offs existbetween material quality and potential performance gains,particularly for strained Si p-MOSFETs, which require highvalues of strain for significant mobility enhancements. As aresult many experimental groups have focused on enhan-cing the performance of either n- or p-MOS devices.

In order to investigate the relative importance ofimproving n- and p-channel device performance throughthe incorporation of strained Si/SiGe layers, simulations ata circuit as well as device level were carried out [22].Increasing the speed of n-channel MOSFETs yields greateradvantages to circuit speed than those attainable byincreasing the performance of the p-channel devices alone.For example, in a four-bit carry lookahead adder, thepseudomorphic CMOS architecture demonstrates perfor-mance similar to conventional bulk Si CMOS, whereas thestrained Si CMOS architecture exhibits a four-foldimprovement in performance. Consequently, optimisingthe strained Si/SiGe layer architecture for n-MOS devices isparamount and the experimental section of this reviewconcentrates on n-channel MOSFETs. Obtaining high

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432 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004

performance from both n- and p-channel devices isnevertheless clearly advantageous for increasing the scopeof applications in which strained Si/SiGe technology canoffer performance gains, providing n-MOSFET deviceperformance is not compromised. Over the past few yearsa wide range of channel mobilities have been reported for avariety of epitaxial layer structures. However, the measuredmobility is itself a strong function of processing thermalbudget and epitaxial material quality [24, 25], therebycomplicating comparisons of strained layer structures fordevices fabricated using different processing conditions.Simulations have therefore been carried out which investi-gated the epitaxial layer structures required for optimisedelectrical performance from both n- and p-channelMOSFETs as a function of achievable channel mobility[22]. In Fig. 3 transconductance is compared for MOSFETshaving surface channels and channels buried up to 6nmbelow the gate oxide interface. It is found that for theseideal n-MOSFETs, surface channel devices offer themaximum performance over the entire range of achievablemobilities. A different trend is observed for the strained Si/SiGe p-MOSFETs. Hole channels buried 2nm below thegate oxide interface outperform surface channel devices,regardless of mobility. Furthermore, only if the holemobility exceeds approximately 700cm2V�1 s�1 would asurface channel MOSFET offer greater performance gainsthan a channel buried 4nm below the gate oxide interface.Figure 3 shows that the optimum CMOS performance isobtained by using a buried hole channel and a surfaceelectron channel. The band alignments of relaxed SiGe,compressively strained Si and tensile strained Si allow thisoptimum CMOS architecture to be achieved on a singlevirtual substrate. The layer structure and band alignment in

inversion conditions for devices fabricated using such a‘dual channel’ configuration are illustrated in Fig. 4.

The sequence of compressive and tensile strained layers inthe dual channel architecture provides strain compensationwithin the epitaxial structure and increases the robustness ofthe material to high thermal budget processing. This isimportant because many early attempts to fabricate strainedSi/SiGe MOSFETs using low thermal budget processing inconjunction with relatively high Ge content Si1-xGex virtualsubstrates (xB0.3) resulted in compromised performance ofboth strained Si/SiGe and bulk Si devices [25–29]. Althoughimproved performance of strained Si/SiGe MOSFETscompared with Si control devices was demonstrated,restrictions to processing arising from the critical thicknesswith such alloy compositions resulted in poor gate oxidequality [26] and parasitic series resistance [27–29]. Analternative approach is to identify the required strained Si/SiGe material composition and layer thicknesses for anoptimised thermal budget process. This methodology hasrecently shown great signs of success. For 150nm gatelength devices fabricated using a high thermal budgetprocess [30] the saturated drain current (I satd ) is more thanfive times higher than in similar geometry devices fabricatedusing a low thermal budget [28]. High temperatureprocessing, however, increases Ge out-diffusion from thehigh Ge content buried hole channel into the surfaceelectron channel. The simulations carried out in [22] do notinclude the detrimental effects of processing Si/SiGematerial using a high thermal budget. Therefore definingan optimum experimental CMOS architecture from simu-lated results is not straightforward and requires compar-isons of simulated results with experimental data. Studies ofdevices fabricated on both single and dual channelstructures are presented below.

3 Devices

3.1 Optimisation of the virtual substratealloy compositionThe studies of circuit performance presented in Section 2highlight the importance of maximising n-MOSFETperformance. In addition, since virtual substrate materialquality degrades with increasing Ge composition [31, 32]and electron mobility enhancements saturate at lowervalues of tensile strain compared with hole mobility [33],there are several clear incentives for optimising the SiGevirtual substrate alloy composition for n-channel MOS-FETs. Strained Si surface channel MOSFETs were there-fore fabricated with a range of Si1-xGex virtual substratealloy compositions, with 0oxo0.3 [34]. Figure 5 shows theelectron mobility enhancement compared with bulk Sidevices as a function of virtual substrate Ge compositionmeasured at effective vertical fields (Eeff) between0.4MVcm�1 and 0.7MVcm�1. At all Eeff investigated, themobility enhancement peaks for devices fabricated on the

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IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004 433

Si0.75Ge0.25 virtual substrate and subsequently decreaseswhen a higher Ge content is introduced into the virtualsubstrate. The reduction in mobility enhancement at higherGe compositions was reflected in the maximum transcon-ductance (gmax

m ) of short channel length devices. Theseresults indicate that by exceeding 25% Ge in the virtualsubstrate, the material becomes degraded and the highvalues of electron mobility achieved using a Si0.75Ge0.25virtual substrate cannot be maintained. Other reports havesuggested electron mobility enhancements saturate at theirmaximum values above Ge compositions of approximately20–25% in the virtual substrate [35, 36]. However, thosedata were measured on devices fabricated using non-optimised, lower thermal budgets. The degradation ob-served in the high Ge content devices in [34] may have beendue to strain relaxation caused by the high thermal budgetprocessing, from increased Ge diffusion into the channelcausing alloy scattering, reduced carrier confinement andpoor gate oxide quality, all of which act to lower themobility. Studies of gate oxide quality on strained Si/SiGeMOS capacitors confirmed a significant increase in the mid-gap gate oxide interface state density (Dit) measured usingthe conductance technique [37] on virtual substrates wherethe Ge content exceeded 25% (Fig. 6) [38]. Schimmeletching, TEM analysis and AFM measurements alsoverified that the defect density and surface roughnessincrease significantly as the Ge content in the virtual

substrate is increased, which will contribute to degradedgate oxide quality. Measurements of gate oxide interfacetrap density on strained SiGe p-MOS devices capped withSi [39] were in excellent agreement with the data presentedin [38]. Whereas gate oxide quality was significantlydegraded on the Si0.70Ge0.30 virtual substrate comparedwith all other SiGe virtual substrates (Fig. 6), the mobilityof the strained Si/Si0.70Ge0.30 devices was comparable withdevices fabricated on the Si0.80Ge0.20 virtual substrate(Fig. 5). Therefore gate oxide quality is not the dominatingfactor behind the performance of these strained Si/SiGeMOSFETs fabricated on high Ge content material, despitethe high processing thermal budget. The largest mobilityenhancements are observed at lower vertical effective fieldsfor all virtual substrate compositions (Fig. 5) becausesurface roughness-limited mobility dominates over pho-non-limited mobility at higher effective vertical fields [40].

The off-state drain leakage characteristics were alsoinvestigated and found to be more sensitive to virtualsubstrate material quality and strain relaxation comparedwith on-state parameters. It has been demonstrated that forvirtual substrate Ge compositions exceeding 15%, the cross-wafer device yield is significantly reduced compared withlower Ge content devices [38]. Studies therefore suggest thatthe optimal virtual substrate alloy composition will belargely determined by the electrical parameter to beoptimised and consequently the specific product applica-tion.

3.2 Dual channel device performanceRim et al. have investigated p-channel performance in dualchannel architectures using a compressively strainedSi0.70Ge0.30 layer below a tensile strained Si layer [41], buthave only provided a limited assessment of electron mobilityin such structures. Researchers at MIT have considereddual channel structures with a view to optimising buried p-MOS devices using relaxed Si1-xGex virtual substrates with0.3oxo1 [42–44]. Strained Si surface channel n-MOS-FETS were also fabricated on a dual channel Si0.70Ge0.30virtual substrate [44] but the devices had long channellengths and were fabricated using a low thermal budgetprocess, unlike conventional CMOS. The first analysis ofexperimental device data demonstrating enhanced perfor-mance from small geometry n-channel MOSFETs using thestrain-compensated structure is reported in [30]. The deviceswere fabricated using a high thermal budget process on aSi0.85Ge0.15 virtual substrate grown by low-pressure CVDmaterial [45] and demonstrated some of the largestperformance gains to date for n-MOS transistors fabricatedon any strained Si/SiGe architecture. Fabrication followed aconventional 0.25mm CMOS process and devices havingdrawn gate lengths of 0.3mm yielded I satd of 0.55mAmm�1 atVg�Vt¼Vd¼ 1.5V, an enhancement of over 140%compared with bulk Si controls (Fig. 7). The gate voltageis Vg, the drain voltage is Vd and the device thresholdvoltage is Vt. Moreover, as predicted in the early work ofO’Neill and Antoniadis [19], the increased on-state perfor-mance of the strained Si/SiGe devices was not at theexpense of short channel effects; DIBL was maintainedbelow 10mV/V for both sets of devices and Ion/Ioff exceeded10 orders of magnitude (Fig. 8). The 0.3mm gate lengthdevice metrics compared favourably with previouslyreported strained Si/SiGe devices having similar geometries[29, 46]. The higher performance of the devices in [30] wasparticularly notable since the MOSFETs were fabricated ona lower alloy composition virtual substrate than those in[29] and [46] which employed 30% Ge virtual substrates. A

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434 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004

Si0.85Ge0.15 virtual substrate was used in order to maximisewafer yield.

3.3 Comparison of single and dual channeldevicesThe primary aim of incorporating the buried strained SiGelayer is to improve p-channel devices [22]. Therefore inorder for the increased complexity of dual channel designsto be worthwhile, n-channel performance must not becompromised compared with devices having single strainedSi surface channels. Improved performance may beanticipated in dual channel structures due to the increasedconfinement of electrons in the high mobility strained Sisurface channel compared with single channel strained SiMOSFETs. However, increased Ge diffusion into thetensile strained Si channel from the high Ge contentstrained SiGe layer during processing and additionalcomplexity in the material growth may offset anyadvantages offered by the double quantum well structure.

Recent work has been carried out in order to comparethe experimental performance of single and dual channel n-MOSFET devices having the same channel strain andfabricated at the same time using a high thermal budgetprocess [47]. The device architectures are shown in Fig. 9.The single channel MOSFET comprised a strained Si layergrown directly on a Si0.85Ge0.15 virtual substrate whereas thedual channel architecture incorporated a compressivelystrained Si0.70Ge0.30 layer in between the Si0.85Ge0.15 virtualsubstrate and the strained Si surface channel. The bandalignments for the layer structures biased into inversionconditions are also shown. Following high thermal budgetprocessing, strain was maintained in the surface channels.This is demonstrated by the reduced capacitance observedin the depletion region of the capacitance–voltage (C–V)characteristics presented in Fig. 10 [48] and was confirmed

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IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004 435

by Raman spectroscopy. The greater reduction in capaci-tance for the dual channel architecture is commensuratewith the larger valence band offset between strained Si andstrained Si0.70Ge0.30 compared with strained Si and relaxedSi0.85Ge0.15 (Fig. 9). Nevertheless, comparisons of mobilityshowed that the single channel devices outperformed thedual channel devices. The electron mobility enhancementcompared with Si control devices is shown in Fig. 11. Athigh fields surface roughness dominates mobility [40].Although both virtual substrates comprised 15% Ge andtherefore exhibit the same cross-hatching roughness, thecompressively strained SiGe layer introduces additionalsurface corrugations on a lateral scale more likely to affectcarrier transport than cross-hatching undulations [49].AFM measurements confirmed a higher degree of surfaceroughness on the dual channel devices compared with thesingle channel devices, which is likely to contribute to thereduced mobility enhancement in the dual channel device athigher fields. At low vertical fields electron mobility isdominated by Coulomb scattering events [40], such as thosegenerated by gate oxide interface traps and substrateimpurity doping. Both virtual substrates were grown withthe same background doping. Conversely, Fig. 12 showsthat the gate oxide interface trap density was an order ofmagnitude higher for the dual channel device comparedwith the single channel device. The improved gate oxidequality contributes to the greater mobility enhancement ofthe single channel devices at low fields. The increase in

surface roughness [50] and Ge diffusion into the Si channel[13] (from the compressively strained Si0.70Ge0.30 layer) bothcontribute to the degraded gate oxide quality of the dualchannel device. Therefore, despite offering performancegains for p-channel devices, the dual channel architectureintroduces several performance and reliability issues forstrained Si n-MOSFETs when fabricated using a highthermal budget process. Contrasting results have beenreported by IBM [41]. However, the processing thermalbudget was lower in [41] than in [47], causing a reducedimpact of Ge diffusion and notably indicating that thestrain-compensated dual channel structure can offer per-formance enhancements in applications which use a reducedthermal budget. As critical dimensions reduce, lowerthermal budgets become increasingly important for con-trolling dopant diffusion and minimising short channeleffects. Consequently, dual channel structures must berevisited for each technology node.

4 Summary

Recent progress in strained Si/SiGe MOSFET devices andtechnology have been discussed. Circuit simulations haveshown that the maximum benefit for many applicationsarises from optimising n-channel device performance, andconsequently the use of strained Si channels on relaxed SiGevirtual substrates has been studied. Device simulationsinvestigating the optimum epitaxial layer structure for highperformance strained Si/SiGe CMOS have been carried out.Experimental results from devices fabricated at advancedtechnology nodes using low thermal budgets suggest thatdual channel devices offer the greatest performanceadvantages over conventional bulk Si, in good agreementwith simulations. Many CMOS applications do not useminimum feature sizes, however, and here the processingthermal budget remains considerable. For such cases,utilising a strained Si surface layer for both the electronand hole channel may be favoured, in order to avoidcompromising n-MOSFET performance gains arising fromincreased Ge diffusion and surface roughness. Electronmobility is found to peak in strained Si channels fabricatedon Si0.75Ge0.25 virtual substrates while device yield isreduced when the virtual substrate Ge content exceeds15%. In conclusion, the future prospects for strained Si/SiGe CMOS technology in the era of nanoelectronics lookspromising. It seems likely that many manufacturers willintroduce strained Si into their 90nm or 65nm CMOSgeneration, while others may take advantage of it in largertechnology generations, in order to improve performancewithout the costs associated with a major re-tool.

5 Acknowledgments

This work is funded by the UK Engineering and PhysicalSciences Research Council. The authors wish to acknowl-edge contributions from partners on the UKHMOS projectand Peter Dobrosz and Steve Bull from the School ofChemical Engineering and Advanced Materials at theUniversity of Newcastle, UK.

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trol

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Fig. 11 Electron mobility enhancement of strained Si/SiGe singleand dual channel MOSFETs compared with control Si data.Strained Si/SiGe devices were fabricated on Si0.85Ge0.15 virtualsubstrates [47]

1×1010

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