Design methods to facilitate rapid growth of SoCs
Arvind Computer Science & Artificial Intelligence LabMassachusetts Institute of Technology
The biggest SoC driversExplosive growth in markets forcell phones game boxessensors and actuatorsFunctionality and applications are constrained primarily by: - cost - power/energy constrains
Current Cellphone ArchitectureComplex, High Performancebut must not dissipate more than 3 wattsTodays chip becomes a block in tomorrows chip
IP reuse is essential
Hardware/software migrationIP = Intellectual Property
An under appreciated factIf a functionality (e.g. H.264) is moved from a programmable device to a specialized hardware block, the power/energy savings are 100 to 1000 foldbut our mind setSoftware is forgivingHardware design is difficult, inflexible, brittle, error prone, ...Power savings more specialized hardware
SoC Trajectory:multicores, heterogeneous, regular, ...Can we rapidly produce high-quality chips and surrounding systems and software?
Things to rememberDesign costs (hardware & software) dominate Within these costs verification and validation costs dominateIP reuse is essential to prevent design-team sizes from explodingdesign cost = number of engineers x time to design
Common quotesDesign is not a problem; design is easyVerification is a problemTiming closure is a problemPhysical design is a problem
Through the early 1980s:The U.S. auto industry Sought quality solely through post-build inspection Planned for defects and rework
and U.S. quality was
less than world classAdding quality inspectors (verification engineers) and giving them better tools, was not the solutionThe Japanese auto industry showed the wayZero defect manufacturing
New mind set:Design affects everything!A good design methodologyCan keep up with changing specsPermits architectural explorationFacilitates verification and debuggingEases changes for timing closureEases changes for physical designPromotes reuse
Design for Correctness It is essential to
New ways of expressing behavior to reduce design complexity Decentralize complexity: Rule-based specifications (Guarded Atomic Actions)Lets you think one rule at a time
Formalize composition: Modules with guarded interfacesAutomatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodologyBluespec Smaller, simpler, clearer, more correct code for both simulation AND synthesisStrong flavor of Unity
Reusing IP BlocksExample: Commercially available FIFO IP blockThese constraints are spread over many pages of the documentation...No machine verification of such informal constraints is feasible
Bluespec promotes compositionthrough guarded interfaces
nnenqdeqfirstFIFO
theModuleAtheModuleBtheFifoSelf-documenting interfaces; Automatic generation of logic to eliminate conflicts in use.
Bluespec: State and Rules organized into modulesAll state (e.g., Registers, FIFOs, RAMs, ...) is explicit.Behavior is expressed in terms of atomic actions on the state: Rule: guard action Rules can manipulate state in other modules only via their interfaces.
The PlanBS2- Simple Example: GCDBS3- Combinational Circuits: IFFTBS4- Architectural Exploration: 802.11aBS5- The IP Lookup problem; subtle concurrency issuesBS6- Bluespec Semantics and Scheduling PrimitivesBluespec is available in two versions:BSV Bluespec in System VerilogESEPro Bluespec in SystemCThese lectures will use BSV syntax
