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Design Metrics

EE141- Spring 2003Lecture 2

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Last Lecture

� Moore’s law� Challenges in digital IC design in the

next decade.

Today� Design metrics

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Administrivia

� Everyone should have a UNIX account on Cory! Thiswill allow you to run HSPICE!» If not, check

http://www-inst.eecs.berkeley.edu/usr/pub/jpg/How-to-Get-Named-Acct.jpg

� PC accounts for 353 Cory will be created early nextweek (when the classlist is completed)

� Discussions start in Week 2� Labs start in Week 3!� If you have not signed-in on the class roster, please

do so after the lecture.

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The EE141 Week at a Glance

M

Tu

W

Th

F

8 9 10 11 12 1 2 3 4 5 6

Lab(TBD)353 Cory

Lab(TBD)353 Cory

Lab (TBD) 353 Cory

DISC*(Dejan)293 Cory

DISC*(Huifang)

203McLaughlin

Lec(Jan)

203 McLaughlin

<- ProblemSets Due

OH(Jan) 511Cory

Lec(Jan)

203 McLaughlin

* Discussion sections will cover identical material

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Introduction (wrap-up)

� Why is designing digitalICs different today thanit was before?

� Will it change in future?

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Frequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(Mh

z)

Lead Microprocessors frequency doubles every 2 years

Doubles every2 years

S. Borkar

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Power

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(Wat

ts)

Lead Microprocessors power continues to increase

S. Borkar

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Power will be a problem

5KW18KW

1.5KW500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(Wat

ts)

Power delivery and dissipation will be prohibitive

S. Borkar

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Power density will increase

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W/c

m2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low temp

S. Borkar

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Power delivery challenges

P6Pentium® proc

486386286

8086

80858080

800840040.01

0.10

1.00

10.00

100.00

1,000.00

1970 1980 1990 2000 2010Year

Icc

(am

p)

P6Pentium® proc

486386

286

8086

80858080

80084004

1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07

1970 1980 1990 2000 2010Year

L(d

i/dt)

/Vd

d

High supply currents at low voltage:Challenges: IR drop and L(di/dt) noise

S. Borkar

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Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

rp

erC

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff-M

o.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

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Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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Challenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝∝∝∝ DSM ∝∝∝∝ 1/DSM

?

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Why Scaling?

� Technology shrinks by 0.7/generation� With every generation can integrate 2x more

functions per chip; chip cost does not increasesignificantly

� Cost of a function decreases by 2x� How to design chips with more and more functions?� Design engineering population does not double every

two years…� Need to understand different levels of abstraction

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Design Metrics

� How to evaluateperformance of a digitalcircuit (gate, block, …)?» Cost» Reliability» Scalability» Speed (delay, operating

frequency)» Power dissipation» Energy to perform a

function

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Cost of Integrated Circuits

� NRE (non-recurrent engineering) costs» design time and effort, mask generation

» one-time cost factor

� Recurrent costs» silicon processing, packaging, test

» proportional to volume

» proportional to chip area

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NRE Cost is Increasing

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Die Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

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Cost per Transistor

0.00000010.0000001

0.0000010.000001

0.000010.00001

0.00010.0001

0.0010.001

0.010.01

0.10.111

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

cost:cost:¢¢--perper--transistortransistor

Fabrication capital cost per transistor (Moore’s law)

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Yield

%100per waferchipsofnumberTotal

per waferchipsgoodofNo. ×=Y

yieldDieper waferDies

costWafercostDie

×=

( )areadie2

diameterwafer

areadie

diameter/2waferper waferDies

2

××π−×π=

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Defects

α−

α×+= areadieareaunitperdefects

1yielddie

α is approximately 3

4area)(diecostdie f=

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Some Examples (1994)

$4179%402961.5$15000.803Pentium

$27213%482561.6$17000.703Super Sparc

$14919%532341.2$15000.703DEC Alpha

$7327%661961.0$13000.803HP PA 7100

$5328%1151211.3$17000.804Power PC601

$1254%181811.0$12000.803486 DX2

$471%360431.0$9000.902386DX

Diecost

YieldDies/wafer

Areamm2

Def./cm2

Wafercost

Linewidth

Metallayers

Chip

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Reliability―Noise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and groundnoise

v(t) VDD

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DC OperationVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

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Mapping between analog and digitalsignals

V IL V IH Vin

Slope = -1

Slope = -1

V OL

V OH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

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Definition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

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Noise Budget

� Allocates gross noise margin toexpected sources of noise

� Sources: supply noise, cross talk,interference, offset

� Differentiate between fixed andproportional noise sources

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Key Reliability Properties

� Absolute noise margin values are deceptive» a floating node is more easily disturbed than a

node driven by a low impedance (in terms ofvoltage)

� Noise immunity is the more important metric –the capability to suppress noise sources

� Key metrics: Noise transfer functions, Outputimpedance of the driver and input impedance of thereceiver;

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Regenerative Property

v0

v1

v3

finv(v)

f(v)

v3

out

v2 inRegenerative Non-Regenerativev2

v1

f(v)

finv(v)

v3

out

v0 in

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Regenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V (

Vol

t)

4

v0

v1v2

t (nsec)0

�1

1

3

5

6 8 10Simulated response

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Fan-in and Fan-out

N

Fan-out N Fan-in M

M

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The Ideal Gate

Ri = ∞Ro = 0Fanout = ∞NMH = NML = VDD/2g = ∞

V in

V out

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An Old-time Inverter

NMH

Vin (V)

V

o ut

(V)

NML

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

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Delay Definitions

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

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Ring Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 × tp × N

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A First-Order RC Network

vout

vin C

R

tp = ln (2) τ = 0.69 RC

Important model – matches delay of inverter

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Power Dissipation

Instantaneous power:p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:Ppeak = Vsupplyipeak

Average power:

( )∫ ∫+ +

==Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

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Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) =

quality metric of gate = E × tp

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A First-Order RC Network

E0 1→ P t( )dt0

T

∫ Vdd isupply t( )dt0

T

∫ Vdd CLdVout0

Vdd

∫ CL Vdd• 2= = = =

Ecap Pcap t( )dt0

T

∫ Vouticap t( )dt0

T

∫ CLVoutdVout0

Vdd

∫12---C

LVdd• 2

= = = =

vout

vin CL

R

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Next Lecture

� Manufacturing Technology� A First Glance at an Inverter