Design of a bit-slice microcomputerD.F. Neale, Ph.D., C.Eng., M.I.E.E., A.T. Clark, B.Sc, and

Prof. D.R. Wilson, M.Sc. Tech., Ph.D., C.Eng., M.I.E.E., F.I.E.R.E., Mem. I.E.E.E.

Indexing terms: Digital computers and computation, Microcomputers, Microprogramming

Abstract: The fact that the synthesis of a microcomputer, to achieve the specific requirements for real-timeoperation, can be achieved through bit-slice technology is utilised as a design factor. The paper presents thedesign of a 3 MHz clock frequency microprogrammable microcomputer based on the Intel 3000 series ofmicroprocessors. The requirements of real-time signal processing are included in the computer specification,as are facilities to incorporate incircuit emulation for software development. The paper discusses themicroprogramming technique and illustrates the flexibility of the microcode through the jump-functionfacility. The paper evaluates the performance to achieve a worst-case cycle time of 383 ns withoutpipelining and carry look ahead as opposed to a worse case of 149 ns with pipelining and carry look ahead.A 3 MHz clock frequency was easily achieved without pipelining.

1 Introduction

The design of a small microcomputer suitable for signalprocessing and associated control algorithms is obviouslyrestricted by the capability of the chosen components. Thedesign freedom is essentially concentrated into the use of thebus structure and the instruction set of the microprocessors.Both of these factors enjoy increased flexibility when bit-slicetechnology is employed with the associated option of micro-programming [1—4]. Tao [5] employed a second-order filterto establish a bench-mark test for a variety of microprocessorsusing software multiplication. The results varied from anestimated 600/us for the 8-bit NMOS Intel 8048 to 23 jus fora 16-bit bipolar bit-slice microcomputer based on AMD 2900series. Neuvo [6], with a peripheral multiplier, has similarlyreported a second-order processing speed of 5/us on an AMD2900 based system, with a computation time T approximatedby

T = 8.5Nr + 5r

where

T = clock period, in this case 230 ns

N — the order of the filter

Alternative implementations, both with and without peripheralmultipliers, have reported essentially similar processing speeds[7—10] to those quoted above.

The authors selected Intel 3000 series components [11,12]circa \916lll as the basis of a microcomputer suitable forsignal processing associated with control systems on the basisof the arguments subsequently published in the literature[13—15]. The reasons can be summarised as follows:

(a) The ability to select the word size appropriate to theperceived computation requirements of the objective.

(b) The advantage of computation time offered by bipolartechnology at the time of hardware selection.

(c) The flexibility to develop a microinstruction codethrough microprogramming.The two major components of the Intel 3000 series are themicroprogram control unit (MCU) and the central processingelement (CPE). The CPE is a 2-bit processing module.Virtually any number of CPEs may be connected to imple-ment a data processing section of any word length. As theCPEs are wired together, all registers, arithmetic and logiccircuits, and data paths expand accordingly. However, theseven-function inputs to each CPE are connected in parallel

Paper 1294E, first received 7th January and in revised form 26thNovember 1980The authors are with The Polytechnic of Central London, School ofEngineering and Science, 115 Cavendish Street, London WlM 8JS,England

to form a single 7-bit CPE function bus from the micro-program memory for the entire array. The function buscontrols the internal operation of the CPE array by selectingthe operands and the operation to be performed during amachine cycle. The ALU under the control of the functionbus decoder performs over 40 Boolean and arithmeticfunctions including 2 s complement arithmetic and logicalAND, OR, NOT and exclusive-NOR. Three buses (M, I andK-bus) provide the CPE array input data paths. Within the CPEarray, eleven scratch pad registers, an accumulator register anda MAR provide data storage. Two internal multiplexers selectoperands for the ALU from data in the registers and on theinput buses. Results of ALU operations can be stored in theregisters and/or the accumulator. The ALU provides a datapath to the MAR, and the data in the MAR and the accumu-lator can be gated on to the output buses A and D. The CPEprovides independent carry input, carry output, shift inputand shift output providing for shift left and right operations.Also incrementing, decrementing, bit-testing and zero-detection facilities are contained within the CPE.

The MCU issues addresses to the microprogram memoryand fetches micro-instructions. This control function uses thecontents of the microprogram memory (micro-instructions) todrive the CPE, external circuits and selects the next micro-instruction. The MCU provides the following independentlycontrollable function facilities:

(i) Jump functions: A mechanism for controlling thesequence in which the micro-instructions are accessed from themicroprogram memory.

(ii) Flag input functions: A mechanism for saving the stateof the flag input which is usually connected to the carry/shiftoutput of the CPE array.

(iii) Flag output functions: A mechanism for controlling thestate of the flag output which is normally connected to thecarry/shift input to the CPE array.

Other attractive features of the Intel 3000 series are:(a) The multiple independent data and address buses that

eliminate time multiplexing and the need for external latches.(b) The three-state output buffers with high fanout that

make bus drivers unnecessary except in the largest system.(c) The separate output enable logic that permits bidirec-

tional buses to be formed simply by connecting inputs andoutputs together.The major application objective of the microcomputer systemhas been that the system should be cable of implementing self-adaptive configurations, based on defined filter design criteria[16—22]. The specification of the unit to achieve thisfunction was interpreted as follows:

8K microprogram memory controlled via the MCU4K program memory for macro instructions and CPE data

overflow

IEE PROC, Vol. 128, Pt. E, No. 3, MAY 1981 0143-7062/81/030095 + 08 $01.50/0 95

Eight 2-bit slice CPEs arranged to provide a 16-bit word3 MHz clockControl panel interface through bidirectional bus driversCompatibility with the microcomputer development system

(MDS).In the first instance the hardware configuration is reviewedthat implements this specification.

MI12-MI15 the K-bus (K0-K3) which provides the maskingfacilities for the CPE array.

MI16-MI22 the micro-function bus (F0-F6) to the CPE array.Other output lines are not displayed on the control panel.

The two read/write lines RWMU and RWML, from themicroprogram memory represent the upper (most significant)four chips and lower (least significant) four chips, respectively.

DM-bus fromfront panelswitches

A-bus to frontpanel lampsand switches

function bus7 „

AK-bus

rprogr^Laddre

MA-bus tofront panellamps and

switches

micro-program -^Caddress - I —

k jumpfunction

bus o 2

CPE array

8 A-bus

16M-bus

16 D-bus

microprogramoutput lines(see fig. 3)

hardware multipliercontrol bus

161-bus

ready signal MI 30

i Itiming

status

resetADC

\zhardwaremultiplier

V

1

programmemory

16- W -i

X \D-bus to frontpanel lamps and

switches

MI 31

74373flip-flops

Fig. 1 Microcomputer system

2 Hardware system design

2.1 MCU and microprogram memory

Fig. 1 illustrates the layout of the processor in block formwith its associated bus structure, and Fig. 2 shows the micro-program memory output. Eight 256 x 4 (3621) PROMelements are used to form the microprogram memory. Theaddress inputs are paralleled through the chips and connectedto the microprogram memory addresses of the MCU. In thisconfiguration an 8-bit microprogram address is used from theMCU (MA0-MA7) where the row address is specified by theupper 4 bits (MA4-MA7) and the column address by the lower4 bit (MA0-MA3). The matrix can therefore contain up to16 row addresses and 16 column addresses giving a total of256 micro-instruction addresses. The DM-bus to the3621 PROMs comes from the data input switches SA0-SA15on the control panel of the computer. The microprogrammemory display (MI0-MI23) on the control panel comes fromthe first 24 output lines of the 3621 chips after passingthrough 24 inverters and 24-330 f2 resistors. This displayrepresents the following:MI0-MI6 the address control functions (AC0-AC6) which

provide the jump functions to the MCU.MI7W indicates macro write in the control logic.

These lines are used in the logic control circuits to operate thecontrol panel. The microprogram address lines (MA0-MA7)which are passed through two 4-bit parallel, inverting bidirec-tional bus drivers are displayed on the front panel. Switchinputs on the control panel provide for the microprogram tobe addressed from the control panel. When this takes place,theMCU microprogram address lines (MA0-MA7) must bedisabled (line EN) and the bidirectional bus from the busdriver must be set in the correct direction (line DCEM); alsothe bus driver must be selected (line CSM).

The remaining lines from the MCU represent the following:SX0-SX3 and PX4-PX7 provide the secondary and primaryinstruction buses from the program memory.Fl, F0 provide the flag logic input and output to and from theCPE array, respectively.The lines (PR0-PR3, ERA, ISE, LD) are not internally con-nected.CLK is the clock to the MCU (and CPE array) and is describedin the control logic section.

2.2 CPE array

Eight CPE (3002) chips connected together form the desired16-bit word length. The buses represent the following:

96 IEE PROC, Vol. 128, Pt. E, No. 3, MAY 1981

ED and EA are the data and address enable lines which areparalleled through the CPE array.F0-F6 provide the microfunction bus from the microprogrammemory; these are also paralleled through the array.The D-bus (D0-D15) provides the data bus to the programmemory and the A-bus (A0-A7) provides the address of theD-bus data to the program memory.TheM-bus(M0-M15)is the data bus from the program memoryto the CPE array.The I-bus is the input bus from an external device, this bus isdiscussed more fully later.The K-bus (K0-K3) is the mask bus and is provided by themicroprogram memory either set to all zero or all ones. Placingthe K-bus in the all one or all zero state in most cases willselect or deselect the accumulator in the operation.

microprogram output lines

I M131-M10 1

F-bushardwaremultiplier

bus

K-bus

ITT3|2|i|0

FC-bus

3 2 10

AC-bus

Z 6 5 4 3 2 1 0\ \^1 H G E D C B A

Fig. 2 Microprogram memory output lines

2.3 Program memory

The program memory consists of four 256 x 4 (3621) PROMs,which provides the macro-instructions to the MCU as alreadydescribed. In addition a small amount of RAM memory will beprovided to cater for any data overflow from the CPE array.

The address bus (A0-A7) and the data bus (D0-D15) fromthe CPE array are passed through bus drivers (the 3226 chips)so that the data and addresses can be displayed on the controlpanel. The program memory can also be accessed from thecontrol panel via switches. The A-bus must pass throughinverters before passing into the program memory as theprogram memory operates its address lines under the oppositelogic from the CPE array. The read/write (RWP) lines selectthe mode of operation for front panel access to the program

memory. The data output bus (M-bus) from the programmemory goes to the CPE array. The 8 most significant bitsof this bus (M8-M15) are also sent to the MCU. These linesconstitute the secondary and primary instruction buses for theMCU.

2.4 Microprocessor clock and con trol logic

The control logic provides the necessary circuits, Fig. 3, forclocking the microprocessor and for running the micropro-cessor from the control panel. A VCO provides the monostablewith a square-wave input of period 320 ns. The monostable'stiming circuit (external resistor and capacitor) triggers themonostable every 320 ns on the falling edge of the VCO inputsquare wave producing a pulse width of 90 ns. The monstable'soutput provides the microcomputer system's clock and isapplied to the MCU and CPE array clock inputs as illustratedin Fig. 3. In addition, a variable capacitor (4-40 pF) has beenapplied to the VCO across the 120 pF timing capacitor to allowthe clock period to be tuned to an exact frequency. The'match' cable applied to one of the inputs of NAND gate 11 isthe control line from the ICE-30 module (see Section 2.6).When the ICE-30 is active the MCU and CPE array clocks arestopped and held in the high state.

With S6 and Si as shown, the microprocessor will berunning under the internal control of the MCU. To single stepthe microprocessor from the front panel Si is closed forcingthe VCO output high. The monostable can be triggered fromthe control panel producing a single pulse which will step themicroprocessor by one cycle. This single step procedure can berepeated continually.

If RAM were installed in the system's memory (as may bethe case for portions of the program memory) it could bedesirable to write to the memories. Therefore, the logiccontrol in Fig. 3 is designed so it can write as well as read fromthe memories via the control panel.

2.5 Microprocessor and interface board

The system consists of two boards, the microprocessor andinterface boards. The microprocessor board contains the MCU,8 CPEs arrayed together, the 8-microprogram and 4-programmemory sockets plus the two inverter chips for the program

LED,GND

variable capacitor(4-40pf)

to MCU and CPEclock inputs

S2 '• program/GND I m'croprogram

address

GND

Fig. 3 Microprocessor clock and control logic

IEEPROC, Vol. 128, Pt. E, No. 3, MA Y1981 97

Table 1 : Significant delay paths

(a) With pipelining and carry look-ahead

tPLRtxftxc*ss*wp

(b)

*co

Delay pathClk t to pipeline register outputsFunction inputs to look-ahead inputsLook-ahead circuit delayData set up time L, C, (3002 inputs)Clock pulse width

T cycle =

Without pipelining and carry look-ahead

Delay pathClk t to MA, F0 outputs (3001)

tROM Pr°9- rnemory access time*cf7xtcc

t S l

Function in to CO outputRipple carry through 7 slicesFlag input set up timeClock pulse width

T cycle =

Delay, ns1752202733

149 ns

455065

1751533

383 ns

memory address lines. The interface board contains all thenecessary components for the interfacing facilities for signalprocessing applications, i.e. ADC, DAC, hardware multiplier.Three 50-way cables pass information between the twoboards, and two other 50-way cables pass information betweenthe two boards, and two other 50-way cable assembliesprovide access to and from the control panel. An additional50-way edge connector is provided on the interface board forexternal input/output facilities connected to the CPE arrayoutput (D-bus) and input (I-bus) buses, respectively.

2£ Software development

For software development, the hardware has been designed tohave compatible buses to an ICE-30 module. The ICE-30consists of a single printed-circuit board and a cable assemblywhich contains an MCU (3001) compatible 40-pin connector.By inserting the board into the bus inside a basic MDS theMCU chip in the user's system may be emulated. On the ICE30 board there is an MCU (3001) chip, which simplifies theemulation of the user system's MCU, and a multiplexer, break-point, and single-step logic circuits. High speed, bipolar RAMis also provided to save addresses and logic signals for tracepurposes. The function of the ICE-30 module is controlled bythe host MDS CPU. The commands issued to the ICE-30 boardare processes by the ICE-30 software driver operating underthe host MDS CPU. The processed command is then trans-ferred to the ICE-30 module for action by way of a memoryread/write to one of two control blocks.

In addition to the ICE-30, three ROM simulator boards areincorporated in the MDS. Two of these boards are designed tosimulate the microprogram memory PROM elements and thethird to simulate the program memory PROM elements. This isachieved by removing all the memory PROMs and inserting theplugs from the ROM simulator boards into the PROMs'sockets. The ROM simulator boards contain compatible RAMto the PROMs; thus the memories can be simulated in RAMwithin the MDS.

2.7 Evaluation of performance

Fig. 4 indicates the relevant delay paths for a basic system(solid lines) and a system with pipelining and carry look-ahead(dotted lines). The worst case delay times are listed in Table 1for both cases.

From Table l(c) it is seen that the fastest cycle time corre-sponds to a clock frequency of 7 MHz. This compares with aclock frequency of 2.6 MHz for the basic system.

The cycle times calculated in Table 1 are for worst-case

parameters. For the system described in this paper a clockfrequency of 3 MHz was easily achieved.

3 Application examples

3.1 The jump function facility

The MCU defines the microprogram memory addressingscheme which contains 11 conditional and unconditionaljump functions. The system has a 7-bit jump field which drivesthe jump-function bus to the MCU. This jump-function bus(AC0-AC6) is shown in Figs. 1 and 2. Each of the MCUs11 jump functions is represented by a unique coding of thejump field. From two to five bits of the field select the jumpfunction while the remaining bits supply part of the desti-nation address. During each micro-instruction cycle the MCUexecutes the jump function specified by the micro-instructioncurrently being accessed from the microprogram memory. Inexecuting this jump function, the MCU formulates the addressthat will be used to access the microprogram memory for thenext micro-instruction in the microprogram sequence. In thisway, the microprogram controls its own sequencing. Theconditional jump functions provide a test facility by allowingselected information maintained by the MCU (i.e. in the C andZ flags, PR-latch etc.) to influence program sequencing. If themicroprogram memory is considered as a matrix consisting of16 rows and 16 columns (providing a total of 256 micro-instruction locations), then the location of the micro-instruction is obtained by its row and column address withinthe matrix. The 8-bit microprogram memory address bus(MA0—MA7) which the MCU transmits to the microprogrammemory specifies the row address in the higher order four bitsand the column address in the low-order four bits.

Fig. 4 Arithmetic delay paths

For example, from any row and column location, it ispossible to jump unconditionally to any other location in thatrow (using one jump instruction) or any other location in thatcolumn (using another jump instruction). For a given locationin the microprogram memory matrix and for a MCU jumpfunction there is a fixed subset of microprogram addresses thatmay be selected as the next address. Fig. 5 shows the 11jump functions with the AC-bus coding together with themicroprogram next address (MA-bus) that these jump func-tions provide. The MCU flag control functions are also shownin Fig. 5.

To illustrate this addressing technique, consider the firstthree jump functions defined in Fig. 5, i.e. JCC, JZR and JCR.If it is assumed that the present microprogram address is:

row address column addressMA-bus lines 7 6 5 4 3 2 1 0Data on MA-bus 0 0 0 0 0 0 0 0

98 IEEPROC, Vol. 128, Pt. E, No. 3, MA Y 1981

then a simple example of these three jump functions is:

Jump AC-bus FIA-bus

3CR 011 fi110

rou column

0000 0000

-13CC 001 101101

3ZR 010 11101

3CC 001 101001

3CR 011 fOOOT

3ZR 010 [0000I

0000 (11011i

|oiool 1101-I- __0100 booil

oooo booo| HThe microprogram memory locations for this program may

be represented as illustrated below (in hexadecimal notation):

addresses

Icolumn0

3 FT

4

- -

a-_

*—.

1ii

j

ii+ - -ii

ij —

,\ 20_i

II

,

1

f

11

1

11

1

1

1

"\

ii

1|

+•

2I1

11

i1 _11

111

J, _11

I

1r

311

J.1i

iii

i

i

ii

. J_.ii

— ! -

4 511

1I

- - , - -

11i

L_

1

1_ _ T . -

11

1

1

11

|1

1

— 1 -

t

|

1

11

11

11

t1

1

1

6I1

_4

i111

T1

J.1

1r

ii1i

- - 4 -

7 8i

1

1

1

1

1'T11I

1

[

I

1Ii

1

~ri

iiIi

i~~r

iii

_ T _

9 Ai1

Lii

— i

i•

ii

riiii

1Ii

j .

Bi i

I1

T1

i

11i

_i

I1

—

I

!

{_i

Ci

1

Ii

1

111

1 ^\_11i _

11

_ _ _ J _i

u L

14 . 16

-

* ' f-t-—'_ J _

ii

I

~ r~

1

- J1

-

Jl v—

2D-

rI

i

p1fi

1 - •

1—i — —

I

i

1i

T ~ ~

Address control function summary

Mnemonic

JCCJZRJCRJCE

JFLJCFJZF

JPRJLLJRLJPX

Symbol

Description

Jump in current columnJump to zero rowJump in current rowJump in column/enable

Jump/test F-latchJump/test C-flagJump/test Z-flag

Jump/test PR-latchesJump/test left PR bitsJump/test right PR bitsJump/test PX-bus

Meaning

Function

AC6

0001

111

1111

5

0111

000

1111

4

d 4

011

011

0011

3

d 3

d 3

d ,0

d3

01

0111

2

Q _

Q

d2

d2Q

Q _

d 2

10

1

d,d,d,

d,d,d,

d ,d ,d ,d ,

0

d n

d n

d n

d 0

dn

dnd 0

d n

d 0

d 0

Next

MA8

d 4

0m8

m8

mg

m8

m8

m8

m8

m8

m8

*

row

7

d 3

0m 7

m7

d 3

m7

m7

m7

m 7

m 7

m 7

6

d 7

0m6

d 2

d 7

dT

d 2

d7

d 71m 6

5

d,0m5

d,

d id,d,

did ,d ,d ,

4

d n0m4

d0

d0

dnd0

dnd n

d n

do

Next column

MA3

m3

d ,

m3

m3

m3

m 3

p3

01x7

2

m2

d2

d2m2

000

P211X 6

1

m,d,d,m,

111

PiP I

P Ix s

0

mn

dn

m0

fcz

PoPiPn

d n Data on address control line nm n Data on microprogram address register bit npn Data in PR-latch bit nxn Data on PX-bus line n (active LOW)f, c, z Contents of F-latch, C-flag, or Z-flag, respectively

* MA8 not connected

Fig. 5 MCU jump instructions and input/output flag control Junctions

IEE PROC, Vol. 128, Pt. E, No. 3, MA Y1981 99

Flag control function summary

Type

Flaginput

Type

Flagoutput

Mnemonic

sczSTZSTCHCZ

Mnemonic

FFOFFCFFZFF1

Description

Set C-flag and Z-flag to fSet Z-flag to fSet C-flag to fHold C-flag and Z-flag

Description

Force FO to 0Force FO to C-flagForce FO to Z-flagForce FO to 1

FC,

0011

FC3

0011

0

0101

2

0101

Fig. 5 (continued)

3.2 Multiplication routines

The time required to perform the multiplication of two 16-bitnumbers in 2s complement form will depend upon the formatof the numbers. If binary notation of the values is consideredthe program will require an extra operation every time a ' 1 ' ispresent in the multiplier, hence the computing time will vary.Fig. 6 lists the microcode and Fig. 7 the flow chart of a 16 x16 fixed point software multiplication routine implementedon the microcomputer. The maximum time required for thisprogram will not exceed 66JUS. The full CPE instruction set isillustrated in Fig. 8.

To perform a 12x12 multiplication via the hardwaremultiplier (MPY), eight instructions are required (as shownbelow) and takes approximately 2.5 jus.

CLR Ro clear register Ro

LMI Ro load MAR with Ro, increment Ro

LCM AC load AC with M-bus data, clock X-input to MPYLMI Ro load MAR with Ro, increment Ro

LCM AC load AC with M-bus data, clock Y-input to MPYLDI AC load AC with I-bus data, clock MSP of MPYSDR Rj load Rt with ACLDI AC load AC with I-bus data, clock LSP of MPY

Eight microprogram operations are also required to perform asoftware addition routine on the microcomputer. The total

time required to execute this program is the same as the 12 x12 multiplication routine using the hardware multiplierprogram outlined above.

4 Conclusions

The advantage of the microprogram technique has beenreviewed and software development considered in the contextof the hardware capability of the computer's configuration.The design of the microprocessor provides a realisable com-puter system with the following specifications:

8 K of microprogrammable memory controlled via the MCU4K of program memory for macro-instructions and CPEdata overflow8 two-bit slice central-processing elements arrayed togetherprovide the required 16-bit word length3 MHz clock frequencyBidirectional bus drivers to provide access to and from themicroprocessor's front panelHardware organisation compatibility for operation via theMDS and associated software development packages, i.e.ICE-30 and ROM simulator boards

The microcomputer system that has been designed does notutilise a carry look-ahead generator or a pipeline register,hence the worst case-delay time for this system is 383 ns.

Comment Program memory

58X X

To 16-bit numbers to be CDmultiplied together GH

Number of bits to be multiplied F FStarting address 00

IF LSBof AC = 1. C-flag = 1IF LSB of AC = 0, C-f lag = 0

C-flag = 1

C-flag = 0

| F T * 0 , F = 1 IF T = 0, F = 0F = 1F = 0

59XX

ABEF

EF00

X X

0001

0203

CPE array coding

controbus

I mnemonicfunctions

CLR Ro

CLR R,

CLR R4

LMI R4

LCM ACSDR R2

LMI R4

LCM ACSDR R3

LMI R4

LCM TILR R2

SRA ACSDR R2

ILR R3

ADR Ro

ILR Ro

SRA ACSDR Ro

ILR R,SRA ACSDR R,DCA TT Z A TIMOPILR R,ILR Ro

K-bus

FF

FFF0FF0FFFF0

F0FF0FF000FFF

F-bus3 2

FFOFFO

FFOFF1FFOFF1FF1FFOFF1FFOFFOFFOFFOFF1

FFOFFOFFOFFOFF1FFOFFCFF1FFOFFOFFOFFOFFO

1 0

HCZHCZ

HCZHCZHCZHCZHCZHCZHCZHCZHCZHCZSCZHCZ

HCZHCZHCZSCZHCZHCZHCZHCZHCZHCZHCZHCZHCZ

MCU jumpinstructions

JCRJCR

JCRJCRJCRJCRJCRJCRJCRJCRJCRJCRJCRJCF

JCRJCRJCRJCRJCRJCRJCRJCRJCRJFLJZRJCRJZR

Microprogram memory

57XX

2020

202020202020202020202020

20202020202020202020202020

55XX

4041

44147B22147B23147A02OF22

033000OF2001OF211E5E650100

53XX

F3F3

F3FFF3OFFFF3OFF3F3F3FOOF

F303F3FOOFF3F7OF0303F3F3F3

51XX

3132

333435363738393A3B3C3D51

3C3A30313233343536422B3120

XX

0001

0203040506070809OAOBOCOD

1B1C1A10111213141516232221

Fig. 6 Microcode for 16 X 16 multiplication

100 IEEPROC, Vol. 128, Pt. E, No. 3, MA Y1981

which allows a maximum clock frequency of 2.61 MHz. Thecycle times calculated are for worst case parameters. It wasfound that for the programs described a clock frequency of3 MHz was easily achieved.

clear Rn.R1.R4

1load MAR with R̂increment R,

1load AC withMt>us data

tload R2with AC

Iload MAR withR, increment R,I* 4

1load AC withM-bus data

Iload R3 with AC

*load MAR with R j

\load T withM-bus data

1load AC with R2

1shift AC rightone bit positionset C&Z flags

tload R2 with AC r-

L5B 1

\ = /

load AC with RQ I

Ishift AC rightone bit positionset C&Z flags

load AC with R3

Iadd AC and RQ

answer in RQ

load Rowith AC

load AC with R^

shift AC rightone bit positionforce FO to C flag

load R1 with AC

subtract 1from T

no / \

yyes

load AC with R^

*load AC with RQ

Fig. 7 16 X 16 multiplication flow chart

All-zero and all-one k-bus micro-functions

The architecture of the microcomputer has been extendedto include facilities for analog input/output appropriate totypical transducers in an instrumentation system. In addition,a hardware multiplier has been incorporated which eliminatesthe need for time consuming complex software subroutines toperform multiplication. This is illustrated by the multipli-cation routine using the hardware multiplier which requiresthe same time as a software addition routine of 2.5 jus. Thefixed point software multiplication routine takes 66/us.

The CPE instruction set allows complex signal processingalgorithms to be readily implemented which, coupled withbipolar technology and the hardware multiplier, allows signifi-cant reductions in data computation times over other micro-processor systems.

5 Reference*1 HOOLEY, D.: 'Bit slice technique minimises microcontroller cost/

complexity', Comput. Design, October 1979, pp. 105-1132 CONWAY, J.C.: 'Hardware approaches to microprogramming with

bipolar microprocessors', ibid., August 1978, pp. 83—913 AGRAWLA, A.K., and RAUSCHER, T.G.: 'Foundations of micro-

programming, architecture, software and applications' (AcademicPress, 1976)

4 RAUSCHE|t, T.G., and ADAMS/, P.M.: 'Microprogramming: atutorial and survey of recent developments. IEEE Trans., 1980,C29, pp. 2-20

5 TAO, T., YEHOSH, D., and MARTINEZ, R.: Applications of micro-processors in control problems. Proceedings of International Con-ference of Digital Signal Proa, August 1978, pp. 8—145

6 NEUVO, Y., ROPPONEN.JC., and SIMULA, O.: 'A fast micropro-grammed digital filter design"'. IEEE Proc. Int. Conf. Acoust. SpeechSig. Prbc, 1977, pp. 523-526

7 ZEMAN, J., and NAGLE, H.T.: 'A high speed microprogrammabledigital signal processor employing distributed arithmetic', IEEETrans., 1980, C29, pp. 134-144

8 MINTZER, L.: 'A microprogrammable signal processor', IEEE Proc.Int. Conf. Acoust. Speech Sig. Proc, 1977, pp. 494-497

9 LOWE, E.: 'A 16 bit microcomputer for missile guidance and con-trol applications'. Proceedings of International Conference onDigital Signal Proc, August 1978, pp. 8-16

10 CUMMINGS, G.A., and MILLER, G.S.: 'Application of a bipolarmicroprocessor chip set to control systems', JACC, 1977, pp. 40-45

K-bus = 00 Micro-function

Rn + Cl - Rn, ACM + C I - A TATL-RO ATH-ATL LI-ATt

Rn-MAR Rn + CI-Rn

M-MAR M + CI-ATAT + Cl - AT

(See CSA above)

Rn + Cl - Rn

(See ACM above)AT + Cl - AT

CI-CO 0 - R n

CI-CO 0 - A T(See CLA above)

(See CLR above)(See CLA above(See CLA above)

Cl —CO R n ^ R nC I - C O M - AT(See IMOP above)

Cl —CO R^ - *R n

CI-CO Iv f -ATCI-CO A T - A T

Mnemonic

ILRACM

[ SRA

LMILMMCIA

CSRCSA

INR

INA

CLRCLA

—

NOPLMF

CMRLCMCMA

K-bus = 11 Microfunction

AC + Rn + Cl - Rn, ACM + AC + C l - A T(See Appendix B)

11 - M A R11 - M A RAT - 1 + Cl - AT

1 - 1 + C l - A T

AC + Rn + Cl — Rn

(See AMA above)I + AT + Cl - AT

Cl V ( R n A A C ) - C OCIV (MA A C ) - C OCIV (AT A I ) - C O

Cl V R n - C OCl V M - COCIV AT-CO

CIV AC-COCl V AC - COCl V I - CO

CIV(Rn AC)-COCIV(M AC)-COCIV (AT I ) -CO

R n - 1 + C I - R n

M - 1 + Cl - AT

> N m . i

Rn A A C - R n

M A AC - ATAT A 1 - AT

Mn- AT°A T - A T

R n V A C - R nM V A C - A T1 V AT - AT

R n e A C - R n

M e AC - ATI i A T - AT

Mnemonic

ALRAMA

DSMLDMDCA

SDRSDALDI

ADR

AIA

ANRANMANI

TZRLTMTZA

ORRORMORI

XNRXNMXNI

NOTE:1. 2's complement arithmetic adds 111

Fig. 8 CPE instruction set

11 t o p e r f o r m s u b t r a c t i o n o f 0 0 0 . . . 0 1 .

IEE PROC, Vol. 128, Pt. E, No. 3, MA Y1981 101

11 Series 3000 mioprogramming manual. Intel Corporation, Santa 17 BRAFMAtf, J.P., SZEZUPAK, J., and MITRA, S.K. An approach toQara.CA 95051 the implementation of digital filters using microprocessors. IEEE

12 Series 3000 reference manual. Intel Corporation, Santa Clara, CA Trans., 1978, ASSP 26, pp. 442-44695051 18 WHITE, R., and NAGLE, H.T.: Digital filter realisations using a

13 HOWARD, J.A., MITRA, S.K., and HUGHES, W.R.: 'A flexible special purpose stored program computer'. IEEE Trans., 1972,architecture for single multiplier accumulator implementation of AU20, pp. 289-294IIR and FIR digital filters', JACC, 1979, pp. 173-177 19 PELED, A.: 'On the hardware implementationof digital signal

14 MACKAY, J.D., and SILVERMAN, H.F.: 'A 16-bit microprocessor processors', IEEE Trans., 1976, ASSP 24, pp. 78-86based digital filter architecture'. IEEE Proc. Int. Conf. Acoust. 20 OPPENHEIM, A.V., (Ed.):'Applications of digital signal processing'Speech Sig. Proc, 1978, pp. 812-815 (Prentice Hall, 1978)

15 PFISTER, B.F., and HORVA"TH, S.: 'Microprocessor based real 21 HIRANO, K., NISHIMURA, S., and MITRA, S.K.:'Design of digitaltime speech processor', ibid, 1979, pp. 872-875 notch filters', IEEE Trans., 1974, Com 22, pp. 964-970

16 JACKSON, L.B., KAISER, J.F., and MCDONALD, H.S.: 'An 22 TREICHLER, J.R., LARIMORE, M.G., and JOHNSON, C.R.:approach to the implementation of digital filters'. IEEE Trans., 'Simple adaptive IIR filtering', IEEE Proc. Int. Conf. Acoust.Electroacoustics, pp. 413-421 Speech Sig. Proc, 1978, pp. 118-121

1 0 2 IEEPROC, Vol. 128, Pt. E, No. 3, MAY 1981