Vol. 9(32), Apr. 2019, PP. 4177 -4187 4177 Article History: Received Date: Dec. 18, 2018 Accepted Date: Mar. 21, 2019 Available Online: Apr. 01, 2019 Design of Modified High Speed 16 & 64-bit Carry Select Adders Yousef Valizadeh-Yaghmurali * , Mostafa Amirpour, Ebrahim Abbaspour-Sani Microelectronics Research Laboratory of Urmia University, Urmia, 57159, Iran Phone Number:+98-44-33452807 *Corresponding Author's E-mail: [email protected]Abstract n this paper a new method for speed improvement of the conventional Carry Select Adder (CSA) has been presented. By means of the proposed methodology a new path for carry propagation is utilized in the architecture of the 16-bit CSA/CLA which improves the speed considerably. This advantage is obtained while the active area consumption for the designed circuit remains the same as conventional CSA structure. Meanwhile, by extending the idea for 64-bit CSA better outcomes have been obtained in comparison with previous works. Post-layout simulation results for TSMC 0.35μm standard CMOS technology depict the correct behaviour of the proposed architecture for both 16-bit and 64-bit adders while the total measured delays for these structures were 1ns and 1.3ns, respectively from 3.3v power supply. Keywords: Carry Select Adder, Carry Lookahead Adder, High Speed. 1. Introduction As a result of various technology developments, the speed of computation has dramatically increased over last decades. There are two factors which play the main role for this achievement. The first one is the rapid growth of submicron technologies and the second one is the expansion of different algorithms. For circuit designers the latter is more important because they can significantly improve the speed performance of the system by means of design techniques whilst the former factor depends on the fabricating specifications. Regardless of the technology, logic path delay depends on many different factors in which the important ones are the number of gates through which the signal has to pass before a decision is made, the logic capability of each gate, cumulative distance among all such serial gates and the electrical signal propagation time of the medium per unit distance [1]. Having the smallest delay among the arithmetic calculating architectures, adders have always played the basic role on the performance of the arithmetic circuits [2]. They are basic building blocks for complicated systems such as digital multipliers and high speed microprocessors. Therefore, they usually lay within the critical paths of these systems and any reduction on the delay of their critical paths will directly improve the speed performance of the system. High speed digital adders are not only for addition of binary numbers but also used for subtraction, multiplication and division. Therefore, the speed of a digital processor depends heavily on the speed of the adder networks [3]. Classic high-speed adders are classified in one of the following groups: Carry Lookahead Adders (CLAs), Carry Skip Adders, Carry Select Adders (CSAs), and conditional-sum adders. Over last years, many more algorithms and circuits have been reported in literature in order to improve the performance of the adders [4] along with their benefits and drawbacks. Among these architectures, Spanning Tree Using Carry Lookahead Adder (STCLA) uses a tree of 4-bit Manchester Carry-Lookahead Chains (MCC) to generate carry for different bit position [2]. In addition, CLA/CSA hybrid adder (RCLCSA) reported in [5] is a continuation of the I
Transcript
Vol. 9(32), Apr. 2019, PP. 4177 -4187
4177
Article History: Received Date: Dec. 18, 2018 Accepted Date: Mar. 21, 2019 Available Online: Apr. 01, 2019
Design of Modified High Speed 16 & 64-bit Carry Select Adders Yousef Valizadeh-Yaghmurali*, Mostafa Amirpour, Ebrahim Abbaspour-Sani
Microelectronics Research Laboratory of Urmia University, Urmia, 57159, Iran Phone Number:+98-44-33452807
Abstract n this paper a new method for speed improvement of the conventional Carry Select Adder (CSA) has been presented. By means of the proposed methodology a new path for carry propagation is utilized in the architecture of the 16-bit CSA/CLA which improves the speed considerably. This
advantage is obtained while the active area consumption for the designed circuit remains the same as conventional CSA structure. Meanwhile, by extending the idea for 64-bit CSA better outcomes have been obtained in comparison with previous works. Post-layout simulation results for TSMC 0.35µm standard CMOS technology depict the correct behaviour of the proposed architecture for both 16-bit and 64-bit adders while the total measured delays for these structures were 1ns and 1.3ns, respectively from 3.3v power supply.
Keywords: Carry Select Adder, Carry Lookahead Adder, High Speed.
1. Introduction
As a result of various technology developments, the speed of computation has dramatically increased over last decades. There are two factors which play the main role for this achievement. The first one is the rapid growth of submicron technologies and the second one is the expansion of different algorithms. For circuit designers the latter is more important because they can significantly improve the speed performance of the system by means of design techniques whilst the former factor depends on the fabricating specifications. Regardless of the technology, logic path delay depends on many different factors in which the important ones are the number of gates through which the signal has to pass before a decision is made, the logic capability of each gate, cumulative distance among all such serial gates and the electrical signal propagation time of the medium per unit distance [1]. Having the smallest delay among the arithmetic calculating architectures, adders have always played the basic role on the performance of the arithmetic circuits [2]. They are basic building blocks for complicated systems such as digital multipliers and high speed microprocessors. Therefore, they usually lay within the critical paths of these systems and any reduction on the delay of their critical paths will directly improve the speed performance of the system. High speed digital adders are not only for addition of binary numbers but also used for subtraction, multiplication and division. Therefore, the speed of a digital processor depends heavily on the speed of the adder networks [3]. Classic high-speed adders are classified in one of the following groups: Carry Lookahead Adders (CLAs), Carry Skip Adders, Carry Select Adders (CSAs), and conditional-sum adders. Over last years, many more algorithms and circuits have been reported in literature in order to improve the performance of the adders [4] along with their benefits and drawbacks. Among these architectures, Spanning Tree Using Carry Lookahead Adder (STCLA) uses a tree of 4-bit Manchester Carry-Lookahead Chains (MCC) to generate carry for different bit position [2]. In addition, CLA/CSA hybrid adder (RCLCSA) reported in [5] is a continuation of the
STCLA work which uses the same conception as STCLA except the lengths of its carry chains are not fixed. High Speed Adder (HSAC) composed of CLA uses Ling’s adder which solves the transition of carry propagation delay [6].
A comparative analysis shows that in the reported works over the last 10 years the main emphasis in the adder design criteria was the reduction of critical path delay while the number of employed transistors and in better words, the on-chip active area had to remain in a reasonable size [7-13]. In [7], [10] and [11] the speed performance was only considered while in [8] and [12] the number of transistors is the main point.
In addition, the focus on the design of high speed 64-bit and 128-bit adders for parallel multipliers of DSP systems consolidates the attention of researchers on the design specifications of such architectures. It is because that regardless of partial production generation and reduction scheme consisting of Booth encoder/decoders [13-14], 4-2 compressors [15-16], Wallace tree [17] and etc, the final summing stage is composed of the adders.
Following the same principles, in this paper a new architecture is introduced for the design of Carry-Lookahead/Carry-Select adders. The architecture is used to implement a novel 16-bit adder in which the speed performance of the system has been improved considerably while the number of transistors is in a moderate level.
To obtain this, in the conventional architecture of 16-bit addition which is composed of 4-bit adding blocks, the first stage 4-bit adder block is replaced with a 3-bit full adder (FA) block and the last block is transformed to a 5-bit FA block to constitute the 16-bit adder structure. Then with the help of a parallel path, the carry selection will be carried out which reduces the delay of whole structure. Using the same design procedure, the idea is extended for 64-bit adder which shows good speed enhancement in comparison with previous works.
In section 2, the main idea of the CSA circuit is briefly discussed. Section 3 is about the new architecture with complete analysis. Section 4 contains the extended idea for 64-bit structure and the simulation results are discussed in Section 5. Finally, the conclusions are summarized in Section 6.
2. Carry Select Adder
General architecture of the CSA which is shown in Figure 1, consists of two ripple carry adders and a multiplexer. Adding two 4-bit numbers with a carry-select adder is done with two adders in order to perform the calculation twice, once with the assumption of the carry being zero and the second time by assuming it logically one. After the two results are calculated, the correct sum, as well as the correct carry, is then selected with the multiplexer when the correct carry is known.
In Figure 1, the resulting carry and sum bits are selected by the 𝐶𝐶𝑖𝑖𝑖𝑖. Because one of the ripple carry adders assume 𝐶𝐶𝑖𝑖𝑖𝑖 = 0, and the other assumes 𝐶𝐶𝑖𝑖𝑖𝑖 = 1, therefore, the output bits can be changed by varying two input bits for 𝐶𝐶𝑖𝑖𝑖𝑖. As it is obvious, the Carry Select principle requires two identical parallel adders that are partitioned into four-bit groups. Each group consists of the same design as shown on Figure 1. Each group generates a group carry. In the CSA, two sums are generated simultaneously. One sum assumes that the logic value of carry is equal to one as the other assumes that the logic value for carry is equal to zero. Therefore, the predicted group carry is used to select one of the two sums.
It can be seen that the logic level of the group carry increases rapidly since more high order groups are added to the total adding path. This complexity can be decreased, with a subsequent increase in the delay, by partitioning a long adder into sections, with four groups per section, similar to the CLA adder.
The main drawback of this architecture is that for higher bits addition, the increased capacitances of middle stages will slow down the performance of the whole structure which results to a larger delay from inputs to the outputs.
3. Designed Architecture
To construct the high speed 16-bit adder structure, some modifications are applied to the conventional structure of Figure 1. The basic idea which is the modified architecture is illustrated in Figure 2(a). It is composed of four blocks in series. The first block is a 3-bit FA while the second and third blocks are 4-bit FAs. The rest 5 bits are summed by a 5-bit FA block. Therefore, there will be three critical paths from inputs to the outputs. The worst case of delays for these paths is summarized in Table 1. To increase the speed of whole architecture, these paths must be optimized. The designed architecture for this purpose is shown in Figure 2(b).
Table 1: Delays for three critical paths.
number Path Delay
1 1-st input bit to S16 3riples + 3Mux
2 4-th input bit to S16 4riples + 2Mux+ 1Mux(ready channel)
3 12-th input bit to S16 5riples + 1Mux(ready channel)
To enhance the speed performance, a 3-bit CLA block is used in parallel with 3-bit FA, so that two
different paths for carry selection of the subsequent blocks will be available. Since the carry selection delay for 4-th block is the longest one, the second route provides a facility to reduce this delay. In Figure 2(a), 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜3 and 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜7 which are the outputs of 3-bit FA and first 4-bit FA block, respectively will charge the input logic value for the gates of the transistors in five Multiplexers (MUXs) of second and third blocks whilst in Figure 2(b), 𝐶𝐶3 and 𝐶𝐶7 must charge the gate capacitance of one MUX transistors.
Therefore, the gate capacitance of second route in Figure 2(b) will be one fifth of its counterpart in Figure 2(a) which takes a smaller fraction of time to be charged. In addition, the input of MUX(*) will be generated sooner in second path which enhances the speed performance. A comparison between
these two structures depict that the gate level delay is not changed but the delay of each block is reduced in Figure 2(b) considerably.
(a)
(b)
Figure 2: Designed adder (a) basic idea (b) complete architecture.
The delay of first state in Table 1 is reduced because of CLA architecture. The latencies of second and third states must be decreased, too. Also, a point which must be considered is that delay of the fourth block should be less than 1𝑛𝑛𝑛𝑛. Also, the delay of second block must not exceed the value of “3ripples + 1MUX” for the worst case which coincides with the generation of 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜3.
Therefore, the speed of second and fourth FA blocks in Figure 2(b) must be improved. To achieve this, these blocks are modified and their carry rippling is eliminated with the use of following techniques:
1) The second block is implemented with the combination of two carry rippling structures. 2) The fourth block is designed by means of a 2-bit and a 3-bit carry rippling blocks which is shown
in Figure 3.
The speed enhancement configuration of Figure 3, has two blocks for 2-bit carry generation. The outputs of these blocks are generated faster and will be applied to the 3-bit FAs. This method reduces the delay more.
The carry generation circuits are shown in Figure 4. If one of the paralleled paths can discharge the gate of the inverter, then 𝐶𝐶2 will charge to a high level voltage. To achieve this, let’s consider that 𝑎𝑎2 and 𝑏𝑏2 contain opposite logic states. In Figure 4(a), if at least one of 𝑎𝑎1 and 𝑏𝑏1 inputs become logically 1, then the output carry will rise to a high level voltage. In Figure 4(b), if at least one of the mentioned inputs becomes logically zero, then the output will be discharged to the low level voltage.
Figure 3: Improved 5-bit FA block (**Carry Generator).
Figure 4: Designed adder (a) basic idea (b) complete architecture.
The designed MUX circuits are illustrated in Figure 5. The circuit of Figure 5(a) is the conventional structure of a transmission gate (TG) based MUX. An inverter can be used at the input of MUX to sharpen the slope for rise time and fall time of the signal. The inverter does not have any effect to the output of the MUX. Therefore, the configuration of Figure 5(b) is employed as the MUX.
Figure 5: TG based MUX (a) conventional MUX (b) Designed MUX.
In addition, to increase the speed more, the 1-bit FA of Figure 6 is employed which is derived from [18].
Figure 6: General architecture of a 1-bit full adder proposed in [18].
4. 64-Bit Full Adder
To show the effect of the parallel path in speed increment, the proposed idea for 16-bit is expanded to 64-bit adder structure. The designed architecture is illustrated in Figure 7 which is composed of the proposed 16-bit adder structures of Figure 2(b). The outputs of each block constitute a 17-bit array in which 16 bits are the outputs of one adder block along with an output carry which has to be selected.
Just like the provided discussion in Section 3, the fourth block has the main effect on the speed performance of the whole system. Therefore, with the existence of a special path in 64-bit adder structure for the selection of this block, the same idea for the speed enhancement of the 16-bit adder will be obtained.
By some attention in Figure 7 it is clear that 𝐶𝐶16 and 𝐶𝐶32 outputs must charge the gate capacitance of one MUX in their path. In comparison with the conventional CSA in which the gate capacitance of transistors of 17 MUXs in parallel should be charged, the delay is much less for the proposed architecture. Therefore, with the increment of the input bits for the adder structure the efficiency of the special path becomes more apparent.
Simulations are performed based on TSMC 0.35µm standard process and 3.3V supply voltage by HSPICE for the architecture of Figure 2(b). The results which are illustrated in Figure 8, indicate that the delay of 5-bit FA block (S12-S16) via second path is approximately equalized with the delay of third block (S8-S11).
Figure 8: Simulation results of proposed 16-bit architecture.
Therefore, according to the simulation results, the delay of the proposed 16-bit architecture is almost equal to the delay of the conventional 11-bit CSA.
In order to provide more real simulation results, the layout of the designed 16-bit and 64-bit structure, has been drawn and the parasitic capacitances are extracted for post-layout simulation. The layout of the designed 64-bit structure is shown in Figure 9.
(c) Figure 10: Simulation results of the designed 16-bit architecture for three worst cases of the outputs (a)
first case (b) second case (c) third case.
Referring to the configuration of Figure 2(b), the worst case for the outputs may occur for one of the following states:
a) A change in the logic state of 𝐶𝐶0 or 𝑎𝑎1 which may change 𝐶𝐶16 and 𝑆𝑆16 outputs
b) A change in the logic state of 𝑎𝑎4 which may change 𝐶𝐶16 and 𝑆𝑆16 outputs c) A change in the logic state of 𝑎𝑎12 which may change 𝐶𝐶16 and 𝑆𝑆16 outputs
The simulation results for all of these three states are shown separately in Figure 10. All of the delays are less than 1𝑛𝑛𝑛𝑛. It must be considered that the rise time and fall time of the input signal are assumed 100𝑝𝑝𝑛𝑛.
Two inverters in series are put at all outputs (before loads) to sharpen the slope for rise time and fall time of the output waveforms. The load of each output bit is assumed 5 unit inverters.
In order to measure the carry rippling delay for the worst case of 16-bit structure, the input pulses are applied separately to 𝑎𝑎1, 𝑎𝑎4 and 𝑎𝑎12 inputs. The worst case of delay which belongs to 𝑎𝑎4, is 905𝑝𝑝𝑛𝑛. As in the design of the 64-bit architecture the proposed 16-bit adder is employed, therefore, the critical path of this structure will belong to 𝑎𝑎4 input. In Figure 11, the measured delay for the worst case of 64-bit system which is 1286𝑝𝑝𝑛𝑛 and belongs to the signal changes in 𝑎𝑎4 input is shown. The latencies for 𝑎𝑎1 and 𝑎𝑎12 are 1255𝑝𝑝𝑛𝑛 and 1245𝑝𝑝𝑛𝑛, respectively.
Figure 11: Simulation results for the worst case delay from inputs to outputs in 64-bit adder structure.
The transistor count for the design of 64-bit adding system is 6288 and total power consumption for the 16-bit and 64-bit adding systems are 4.07𝑚𝑚𝑚𝑚 and 16.9𝑚𝑚𝑚𝑚, respectively.
In Table 2, the specifications of similar 64-bit designs are compared with the proposed 64-bit architecture. With the consideration of technology difference, the number of employed transistors for [7], [10] and [11] are at least 33% more than proposed structure whilst the speed performance is better than [8], [12] and [19].
CONCLUSION
A new high speed 16-bit adder is presented in this paper which can be widely used in high speed digital multiplier design. A design methodology is introduced in which by means of an improved system, a new path for carry propagation is employed in the architecture of the 16-bit CSA/CLA that improves the speed performance considerably. This advantage is obtained while the active area consumption of the designed circuit is almost like the conventional CSA structure. By expanding the idea to 64-bit adder structure the efficiency of the special path becomes clearer since the capacitance of the middle stages will be reduced considerably. Post-layout simulation results for TSMC 0.35µm standard CMOS technology depict the correct behavior of the proposed architecture. The delay of the whole circuit is less than 1ns for 16-bit architecture while the power consumption of the whole architecture is 4.07mW from 3.3v power supply. For the 64-bit system the delay of the critical path is 1286ps architecture while the power consumption is 16.9mW.
Table 2: Comparison between designed architecture and previous works.
64 Bit adder Process
(μm)
VDD
(v)
TR.
#
Delay (ps) Log.
[7] 0.18 1.8 8138 409 (meas)
411 (sim)
Dyn.
[8] 0.25 2.5 2590 3040 (sim) Sta.
[9] 0.18 1.8 ---------- 853 (sim) Sta.
[10] 0.18
(SOI)
1.5 18291 720 (meas)
679 (sim)
Sta.
[11] 0.18 1.8 9642 650 (sim) Sta.
[12] 0.5 3.3 3044 2600(meas) Sta.
[19] 0.18 1.8 ---------- 1030 (sim) Sta.
Our Work 0.35 3.3 6288 1286 (sim) Dyn.
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Authors
Yousef Valizadeh-Yaghmurali was born in Urmia, Iran, in 1986. He received the B.S. and M.S. degree in Electrical Engineering from Urmia University, Iran in 2010 and 2013 respectively. His research interests are analog and digital integrated circuit design and MEMS sensors. He is currently a researcher in the Microelectronics Research Laboratory at the Urmia University, Urmia, Iran.
Mostafa Amirpour received his B.Sc. and MSc. degree in Electronics Engineering from Urmia University, Iran, at 2012 and 2015 respectively. His current research interests are design of MEMS sensors and their interface circuits including Signal Processing Units, Data Converters, and PLLs. He is currently a researcher in the Microelectronics Research Laboratory at the Urmia University, Urmia, Iran. Ebrahim Abbaspour-Sani received a B.Sc. degree from Ahwaz University, Iran at 1976, a MSc. degree from University of Wales Institute of Technology (UWIST), Cardiff, UK, at 1981 and PhD from University of New South Wales, Sydney Australia at 1996. He joined the department of Electrical Engineering, Urmia University, Iran at 1983 as a lecturer. He is currently acting as an associated professor at the MEMS department of Urmia University. His current interests are MEMS sensors and actuators including Accelerometers, RF switches, phase shifters and Micro-Mirrors.
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