Design of Radix-2 Butterfly Processor

8/9/2019 Design of Radix-2 Butterfly Processor

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ABSTRACT

The high growth of the semiconductor industry over the past two decades has put Very

Large Scale Integration in demand all over the world. Digital Signal Processing has played a

great role in expanding VLSI device area. The recent rapid advancements in multimedia

computing and high speed wired and wireless communications made DSP to grab increased

attention.

or an !"point transformation the direct computation of the Discrete ourier Transform

#D T$ re%uires ! & operations. 'ooley and Tur(ey explained the concept of ast ourier

Transform # T$ which reduces the order of computation to !log & !. )asically T decomposes

the set of data to be transformed into a series of smaller data sets to be transformed. The si*e of

T decomposition is called +radix+. Then, it decomposes those smaller sets into even smaller

sets.

In this wor(, the -adix"& )utterfly Processor will be designed which includes the adder,

subtractor and the twiddle factor multiplier. The complex multiplier algorithm will be used in

order to achieve the efficient complex multiplication. The -adix"& )utterfly Processor will be

modeled using V DL language which is a ardware Description Language # DL$ used to

describe a digital system. The modeled design can be simulated using /odelsim tool and the

intended functionality can be verified with the help of its simulation results and also it can be

synthesi*ed using the 0ilinx tool.


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CHAPTER 1CHAPTER 1INTRODUCTION AND LITERATURE SURVEY

igh performance VLSI"based T architectures are (ey to signal processing and

telecommunication systems since they meet the hard real"time constraints at low silicon area and

low power compared to 'P1"based solutions.

The fast ourier transform # T$ plays an important role in the design and

implementation of discrete"time signal processing algorithms and systems. In recent years,

motivated by the emerging applications in the modern digital communication systems and

television terrestrial broadcasting systems, there has been tremendous growth in the design of

high"performance dedicated T processors. Pipelined T processor is a class of real"time T

architectures characteri*ed by continuous processing of the input data which, for the reason of

the transmission economy, usually arrives in the word se%uential format. owever, the T

operation is very communication intensive which calls for spatially global interconnection.

Therefore, much effort on the design of T processors focuses on how to efficiently map the

T algorithm to the hardware to accommodate the serial input for computation.

The T is a faster version of the Discrete ourier Transform #D T$. The T utili*es

some clever algorithms to do the same thing as the DT , but in much less time. 2(, but what is

the D T3 The D T is extremely important in the area of fre%uency #spectrum$ analysis because

it ta(es a discrete signal in the time domain and transforms that signal into its discrete fre%uencydomain representation. 4ithout a discrete"time to discrete"fre%uency transform we would not be

able to compute the ourier transform with a microprocessor or DSP based system.

The Discrete ourier Transform #D T$ plays an important role in the analyses, design and

implementation of the discrete"time signal" processing algorithms and systems It is used to

convert the samples in time domain to fre%uency domain. The ast ourier Transform # T$ is

simply a fast #computationally efficient$ way to calculate the Discrete ourier Transform #D T$.

The wide usage of D T5s in Digital Signal Processing applications is the motivation to

Implement T5s. D T is identical to samples of the ourier transform at e%ually spaced

fre%uencies.

'onse%uently, computation of the !"point D T corresponds to the computation of !

samples of the ourier transform at ! e%ually spaced fre%uencies 6( 7 &8(9!. 'onsidering input


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x:n; to be complex, ! complex multiplications and #!"


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unctionally, the T decomposes the set of data to be transformed into a series of smaller

data sets to be transformed. The si*e of T decomposition is called +radix+. Then, it

decomposes those smaller sets into even smaller sets. Bt each stage of processing, the results of

the previous stage are combined with twiddle factor multiplication. inally, D T is calculated for

each small data set. T s can be decomposed using D T s of even and odd points, which is

called a Decimation"In"Time #DIT$ T, or they can be decomposed using a first"half9second"

half approach, which is called a +Decimation"In" re%uency+ #DI $ T .

The T is simply an algorithm to speed up the D T calculation by reducing the number

of multiplications and additions re%uired. It was populari*ed by F. 4.'ooley and F. 4. Tu(ey in

the


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naive way, using the definition, ta(es 2 #! &$ arithmetical operations, while an T can compute

the same result in only 2#! log !$ operations. The difference in speed can be substantial,

especially for long data sets where ! may be in the thousands or millionsQin practice, the

computation time can be reduced by several orders of magnitude in such cases, and the

improvement is roughly proportional to !9log#!$. This huge improvement made many D T"

based algorithms practicalE Ts are of great importance to a wide variety of applications, from

digital signal processing and solving partial differential e%uations to algorithms for %uic(

multiplication of large integers .

The most well (nown T algorithms depend upon the factori*ation of !, but #contrary

to popular misconception$ there are Ts with 2#! log !$ complexity for all !, even for prime

!. /any T algorithms only depend on the fact that is an ! th primitive root of unity , and thuscan be applied to analogous transforms over any finite field , such as number"theoretic

transforms .

Since the inverse D T is the same as the D T, but with the opposite sign in the exponent

and a .g. radix"& transforms can be ?"point,


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decimation"in"time transforms need their input samples to be swapped into bit"reversed order

prior to the transform which gives normal"order results, and decimation"in"fre%uency transforms

use normal ordered input samples and generate their output samples in bit"reversed order.

owever, this overhead is insignificant when compared to the transform itself.

6 ! 7 e R@& 9!. =============..#


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In addition, the factor W N k+N/2 = -W N k . ence the e%uation may be expressed as

======..#


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The decimation of the data se%uence can be repeated again and again until the resulting

se%uences are reduced to one"point se%uences. or N 7 &v, this decimation can be performed v 7

log & N times. Thus the total number of complex multiplications is reduced to # N 9&$log& N . The

number of complex additions is N log & N .or illustrative purposes, igure C.& depicts the computation of N 7 N point D T. 4e observe that

the computation is performed in three stages, beginning with the computations of four two"point

D Ts, then two four"point D Ts, and finally, one eight"point D T. The combination for the

smaller D Ts to form the larger D T is illustrated in igure T'.C.C for N 7 N.

Fi)ure 1.' Three stages in the computation of an N 7 N"point D T.


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Fi)ure 1.# >ight"point decimation"in"time T algorithms.

Fi)ure 1.* basic butterfly computations in the decimation"in"time T algorithm.

Bn important observation is concerned with the order of the input data se%uence after it is

decimated #v"


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======#


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Fi)ure 1. N 7 N"piont decimation"in"fre%uency T algorithm.

4e observe from igure.


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which for large ! ma(es a huge difference. The optimi*ed version of the algorithm is called the

fast ourier transform, or the T.

Let s do some bac( of the envelope calculations. Suppose that we want to do a real"time

ourier transform of one channel of 'D"%uality sound. That s ??( samples per second. Suppose

also that we have a


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If we start with ! that is a power of &, we can apply this subdivision recursively until we

get down to &"point transforms.

4e can also go bac(wards, starting with the &"point transformA

V:(; 7 4 &U( v: ; 4 &


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I encourage the reader to derive the analogous diagrammatical representation for !7N.

4hat will become obvious is that all the butterflies have similar formA

ig.


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This diagram is the essence of the T algorithm. The main tric( is that you don t

calculate each component of the ourier transform separately. That would involve unnecessary

repetition of a substantial number of calculations. Instead, you do your calculations in stages. Bt

each stage you start with ! #in general complex$ numbers and +butterfly+ them to obtain a new

set of ! complex numbers. Those numbers, in turn, become the input for the next stage. The

calculation of a ?"point T involves two stages. The input of the first stage is the ? original

samples. The output of the second stage is the ? components of the ourier transform. !otice that

each stage involves !9& complex multiplications #or ! real multiplications$, !9& sign inversions

#multiplication by "


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CHAPTER 'CHAPTER 'De i)n of Butterf( Pro2e or Re u( t an$ Di 2u ion

'.1 HDL Co$in) for the FFT A()orith!

In T all the operation to be performed is fixed. Bt top level it has instantiation of the

basic radix"& butterflies. >ach butterfly includes the multiplication with the twiddle factor and

some complex addition and subtractions. So, the butterfly coding also has the instantiations of

the signed complex adder9Subtractors and multipliers. In these two main modules the complexity

lies in proper port match while instantiation. The port connections should match the e%uation to

be derived so as the connections are optimi*ed and an inherent optimi*ed design is being

implemented.

The adder9subtractor and the multipliers need to handle signed complex numbers, so thecoding for them is done with parameteri*ed signed operation of the bloc(. Blso, in all of the

operations the bit si*e of the output increases and in cascaded connection of such logic, proper

length is to be maintained. The modules are also parameteri*ed for the same and while

instantiation of the module the length of the input bit si*e is defined. In case of multipliers, one

of the numbers is twiddle factor whose value lies between < and "


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/BTLB) tool from /athwor(s Inc., has inbuilt function defined for fast fourier transform

# T$. To get the proper test cases, the input were chec(ed in the /BTLB) and corresponding

output values being noted. The values of output match to the specified output values with

%uanti*ation error. The error fluctuates w.r.t. the %uanti*ation ta(ing place in the calculation.

'.* VHDL 2o$in)"

The V DL code is developed for &"point radix"& Decimation"In" re%uency T

algorithm. There are different modules are performed in order to implement the algorithm such

as complex multiplication, single stage butterfly and top module that has the instantiation of sub"

modules.

In the code, totally & inputs that has both real and imaginary each of G"bits are fed to first

stage butterfly. )efore that twiddle factor is to be multiplied which is neglected since all the

twiddle factors are


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'2S 7 c

SI! 7 s

- @I 7 #x @y$ #cos& @sin& $U 7 x J y

Y 7 c #x " y$

4e can compute - 7 #c " s$ y *

- 7 # c J s $y c#x " y$

7 cy J sy cx J cy

7 cx J sy===================.#&.C$

I 7 #c s$ x " *

I 7 # c s $x c#x " y$

7 cx sx " cx cy 7 cy sx===================.#&.?$

The e%uation &.C and &.? are the results of the complex multiplication for doing complex

multiplication we already (now the values of cos and the sin so we need to find out the

intermediate values of the complex multiplier. 4e are feeding the values of '2S JSI! and the

'2S SI!. These values we can multiply with the difXim and difXr. so we can avoid the two

subtractions in the DL.

Bccording to the e%uation we come to (now that we need to have the complex adder

complex subtractions and complex multiplier.

or the test case of the butterfly processor we given the inputs

Bre @Bim 7 < @im 7 4/difXre @difXim$9& U ##cos& @sin& $Ure >im 7 4/difXre @difXim$9& U ##cos& @sin& $U


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>re >im 7 4/M @O $9& U ##M @O059re >im 7 O @HN. ===================#2utputXC$

ig.&.& -esult for the above test case in )utterfly architecture

The architecture is modeled in the DL and the simulation results are shown in the figure &.& the

inputs of the butterfly processor will be having two points and each of G bits. Bfter the butterfly

processor we need to divide the result by & < . In the twiddle factor multiplication the results

need to divide by the & M. The output of the butterfly architecture we need to multiply the value of

the number of inputs that5s why we can avoid the overflow in the arithmetic operation. igure &.Cshowing the each stage outputs.

The implementation re%uirement which includes the primary input and primary output of

the design and the proper notation and conventions were discussed.

Keneral implementation flow of the design were represented and explained in order to

understand the proper flow. Implementation details have been discussed which includes

implementation style of each process. The results showing after the twiddle factor multiplication

in figure &.C. The twiddle factor multiplication architecture developed using the twiddle factor

e%uation #&.&$. The ( values ta(ing from the architecture and the ! is the number of points here

we are having ! 7


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ig.&.C -esult for the above test case in )utterfly architecture

Su!!er The identified -BDI0 & algorithm is modelled and is simulated using the /odelsim tool.

The simulation results are discussed by considering different cases.

-eference cloc(

< @


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CHAPTER #CHAPTER #I!3(e!entation of Butterf( 3ro2e or

#.1 Intro$u2tion to FP6A

The digital circuits can be broadly classified as Standard, BSSP #Bpplication Specific

Standard Product$ or 'ustomi*ed. ield Programmable Kate Brrays # PKBs$ is one of the ways

to implement custom logics. Bs the name suggests, this I' can programmed in the field i.e. by

the system manufacturer. These are li(e programmable BSSPs. The product cost of PKBs is

significantly higher than BSI's but the !on"recurring >ngineering costs #!->$ are reduced to

*ero.

#.' Literature Sur7e on FP6A

PKBs provide a lot of flexibility to the user to program it in the way it is re%uired. Bll theI2 pins, the internal bloc(s and even the interconnects are programmable. This flexibility

extends to design changes even after the layout is complete.

Fi)ure #.1 8 FP6A De i)n F(o9

The main part of the PKB design cycle is to design the logic and the tune it during

verification while implementation to an PKB board. During the implementation, various


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/ap

Place and -oute

Tran (ate " /erge multiple design files into a single netlist.

:a3 " Kroup logical symbols from the netlist into physical components.

P(a2e an$ Route " The place components into the chip, connect the components, and extract

timing data into reports

The developed -TL model will be translated to the mathematical e%uation format which

will be in the understandable format of the tool. These translated e%uations will be then mapped

to the library that is, mapped to the hardware. 2nce the mapping is done, the gates were placed

and routed. )efore these processes, the constraints can be given in order to optimi*e the design.

inally the )IT /BP file will be generated that has the design information in the binary format

which will be dumped in the PKB board.

Bbove shows the basic steps involved in implementation. The initial design entry of may

be V DL DL, schematic or )oolean expression. The optimi*ation of the boolean expression by

considering area or speed.

Fi)ure #.# Lo)i2 B(o2;

In technology mapping, the transformation of optimi*ed )oolean expression to PKB

logic bloc(s. ere area and delay optimi*ation will be ta(en place. During placement the

algorithms are used to place each bloc( in PKB array. Bssigning the PKB wire segments,which are programmable to establish connections among PKB bloc(s through routing. The

configuration of final chip is made in programming unit.


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#.+ S nthe i Re u(t

The developed & point -adix"& T design is simulated and verified their functionality.

2nce the functional verification is done, the -TL model is ta(en to the synthesis process using

the 0ilinx IS> tool. In synthesis process, the -TL model will be converted to the gate level

netlist mapped to a specific technology library. This & point -adix & T design can be

synthesi*ed on the family of SPB-T>! C>.

ere in this SPB-T>! C> family, many different devices were available in the 0ilinx

IS> tool. In order to synthesis this design the device named as [0'CSO e"? KC& \ has been

chosen and the pac(age as [


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Logic 1tili*ation

Logic Distribution

Total Kate count for the Design

The device utili*ation summery is shown above in which its gives the details of number of devices used from the available devices and also represented in ]. ence as the result of the

synthesis process, the device utili*ation in the used device and pac(age is shown above.

Memory Usage

otal memor* 'age i' #"#&0, kilo *te'

Device Utilization Summary:

elected e ice $'%00efg$20-!

N m er of lice' 1" o t of !"%" 2

N m er of lice Fli3 Flo3' "! o t of 1$#2 0

N m er of ! in3 t 45 ' #%& o t of 1$#2 #

N m er of 67' 1#

N m er of onded 678' 1# o t of 2$2 $1

N m er of 954 #,X#, 67' $ o t of 20 #%

N m er of :;4


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During the implementation of the logic, any sub"output results are obtained. These together

with the related reports are detailed in the sub"section ahead.

#.-.1 RTL B(a2; Bo% of the Lo)i2

2n successful synthesis of the DL code, the -TL blac( box #as shown in figure C.&$ is

obtained. It shows all the inputs on the left and outputs on the right.

Fi)ure #.* 8 RTL S2he!ati2 for ' 3oint Ra$i%&' FFT

#. I!3(e!entation of the Ra$i%&' Butterf( A()orith!

or further analysis of the T algorithm implementation, the code is synthesi*ed in 0ilinx

IS> and the reports are analy*ed. The level"< views of the -TL schematic for the T logic is

shown in the figure &.H. The synthesis report lists the options for synthesis and provides the DL

compilation reports. . It also lists the Design 1tili*ation details, both in numbers of bloc(s and

the ] of usage. This helps to analy*e the area utili*ation of the PKB board used for

implementation.

#.< De7e(o3in) S3e2ifi2ation

>very logic has some design specifications which are to be met during the design. Blso

some other parameters related to the functionality and operation of the design is available as a

part of the specification of the design. The T algorithm implemented has the specs as J

Point #!o. of inputs$ J &

Blgorithm used J -adix"&

'oding Scheme J Decimation"in" re%uency #DI $

/aximum fre%uency of operation J %".$!!9>? 2ffset in Period J C.MH ns

2ffset out Period J &.MGGns

#.1= Ne9 I$ea for Rea(i>ation of De i)n on FP6A

I n p u t s

2 u t p u t s


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PKB are finding more and more application because of the flexibility they provide in

prototyping any logic and the re"configurability. This creates a need to find new ideas for

reali*ation of Design on PKB.

Bs the limited by the PKB board hardware, it is found that the number of inputs andoutput are very limited. This could be increased by using roc(er or piano type of micro"switches.

B ?A< switch can be directly connected to the seven segment display to represent the ?"bit input

e%uivalent in hexadecimal. These hardware elements being smaller in si*e can be easily

accommodated on PKB boards, but yes complexities do add to have the interconnects re%uired

for the same to be connected to the control logic and to ma(e it an integral part of the

programmability

Su!!er The -TL model is synthesi*ed using the 0ilinx tool in Spartan C>

The synthesis results were discussed with the help of generated reports.

Bccording to the synthesis report the area utili*ation and the timing details is analy*ed.

CHAPTER *CHAPTER *CONCLUSION

ast ourier Transform # T$ techni%ues have revolutioni*ed the Digital Signal Processing

techni%ues in the past C years. In does not only provide a fast response but also many logic

thought to be un"reali*able come easily in the range to be reali*ed. The parallel processing of

T hence has been proposed to be used in multiprocessor algorithms. 4hen an T is

implemented in special"purpose hardware, errors and constraints due to finite word lengths are


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Design of Radix-2 Butterfly Processor

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