IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011 2883
Design of Robust Digital PID Controller forH-Bridge Soft-Switching Boost Converter
Veerachary Mummadi
Abstract—In this paper, a robust digital proportional–integral–derivative (PID) controller is proposed for the H-bridge soft-switching boost converter (HSBC). This digital PID controller isdesigned to ensure load voltage regulation as well as to give robustperformance with step loads and source rejection. The mathemat-ical models of the H-bridge boost converter are formulated, usingthe system identification tool, and then used in digital PID design.Here, this compensator is designed in the direct digital domain ac-cording to a pole placement approach that uses sensitivity functionshaping in order to ensure closed-loop converter system stabilityas well as robust performance against converter parameter uncer-tainties. To confirm this, design simulations have been carried outon a 60-W 24–42-V HSBC. The experimental results are providedto validate the robust controller design concept.
Index Terms—Digital proportional–integral–derivative (PID)controller, H-bridge soft-switching converter, robust performance,sensitivity functions.
I. INTRODUCTION
H IGH-FREQUENCY switching converter applications inlow-power compact electronic circuits have increased in
recent years. As power conversion systems become miniatur-ized, increasing the power density is one of the challenging is-sues for power supply designers. One of the main orientations inpower electronics in the last decade has been the developmentof switching-mode converters with a higher power density andlow electromagnetic interference. Low weight, small size, andhigh power density are also some of the key design parameters[1]–[3]. The need to increase the power density is related toconverter design and packaging. Conventional boost converter-based topologies are well established for applications requiringhigher load voltages. However, hard switching results in aconsiderable amount of power loss and imposes a constrainton the maximum achievable efficiency. In order to reducethe switching losses and realize higher efficiencies, severalsoft-switching (SFSW) techniques have been reported in theliterature [4]–[13]. Some of these topologies are accompaniedby higher voltage, higher current stress, and larger conduc-tion losses than those in hard-switched pulsewidth modulated(PWM) converters. Zero-voltage switching is realized with aswitched snubber in [6]. Zero-voltage/zero-current switching
Manuscript received April 25, 2010; revised July 27, 2010; acceptedAugust 28, 2010. Date of publication September 20, 2010; date of currentversion June 15, 2011.
The author is with the Department of Electrical Engineering, Indian Instituteof Technology Delhi, New Delhi 110016, India (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2010.2077615
PWM converters are reported in [11]. However, these solu-tions need additional drive circuitry. Although quasi-resonantconverters are capable of achieving higher efficiencies, theymust be operated at variable switching frequencies. Further-more, optimizing resonant tank elements for such convertersis a tedious task. Single-switch SFSW converters have alsoresulted in higher efficiencies, but they exhibit higher voltageand current stresses. An H-bridge-based soft-switching schemewas introduced for conventional buck, boost, and buck–boostconverters [13]. This concept used an auxiliary switch, a pairof diodes, and the main switch-forming bridge network. Theanalysis of a soft-switching boost converter topology with azero-voltage turn-on feature is reported in the literature. How-ever, there is insufficient literature covering the developmentof controllers for such kinds of converters. In order to bridgethis gap, this paper presents investigations on robust digitalproportional–integral–derivative (PID) controller design withthe following features: 1) ensures load voltage regulation;2) rejects source and load disturbances; and 3) rejects converterparameter variation.
Although custom-built IC-based analog controllers are wellestablished for switched-mode power supplies (SMPSs) [1]–[3], digital controllers offer many advantages over their analogcounterparts. Due to recent advances in microcontrollers/digitalsignal processors, there has been a growing interest in theapplication of digital controllers for high-frequency conversionsystems and low- to medium-power dc–dc converters due tothe low price-to-performance ratio for implementing complexcontrol strategies [14]–[23]. Several compensator design ap-proaches have been reported in the literature for operational-amplifier or IC-based analog controllers. However, in the caseof digital controller design [15], the following two main ap-proaches are widely used: 1) digital redesign method (DRM)and 2) direct digital design method (DDDM). In the firstcase, the compensator is designed in the conventional wayby using s-domain transfer functions, together with a linearsystem theory, and the resulting compensator is transformedinto the digital domain using appropriate z-transformations.The main limitations of the DRM are the following: 1) Thediscretized controller is not guaranteed to have closed-loopsystem (CLS) stability; 2) CLS properties need to be takeninto account while choosing a particular discretization method;3) for a given converter, the selection of the discretizationmethod depends on the sampling rate at which the digital con-troller needs to be operated; and 4) the sampling rate, togetherwith the selection of the discretization method, gives manydigital controller configurations, and some of these controllerswill not stabilize the actual closed-loop converter. Furthermore,
2884 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
Fig. 1. Circuit diagram of HSBC.
such designs need a lot of tuning of the gain parameters beforethey are operational. On the other hand, in the DDDM, thecompensator design is carried out in the z-domain itself, andhence, there is no need for s-to-z-domain transformation. Sincethe DDDM handles discrete-transfer functions, in their design,it is possible to include the sample-and-hold time-delay effects,if there are any, and thus, the final resulting digital controller ismore realistic and meets the design tradeoffs without needingany fine tuning.
Controllers, whether analog or digital, are more sensitiveto noise, parameter variation, and external disturbances. Inorder to make a digital controller that is capable of rejectingdisturbances and is more immune to perturbations, which maybe either internal or external, the controller must be designedwhile taking extreme operating conditions into account. In thiscontext/direction, robust control methods [24]–[30] are morecommon in the design of conventional controllers; however,their application in the digital controller domain is slowlybecoming more common. The purpose of these investigationsis to design a robust digital PID design for an H-bridge soft-switching boost converter (HSBC), and a detailed discussion isgiven in the following sections.
II. ANALYSIS AND DISCRETE-TIME
MODEL FORMULATION OF HSBC
An HSBC is shown in Fig. 1. Compared to the conventionalboost converter, it has an additional soft-switching networkwhich is indicated within the box and consists of two diodes(D1,D2), an auxiliary switch (Sa), a capacitor (Cr), and aninductor (Lr). This HSBC operates in six different operatingmodes [13] in one PWM cycle, and the conducting devicesin each mode of operation are as follows: 1) mode-1: D-ON;2) mode-2: Sm, Sa, and D are in the ON-state; 3) mode-3: Sm
and Sa are in the ON-state while Lr and Cr are resonating;4) mode-4: Sm, Sa, D1, and D2 are in the ON-state; 5) mode-5:D1 and D2 are in the ON-state while Lr and Cr are resonating;6) mode-6: D1, D2, and D are in the ON-state. The steady-statevoltage gain of this HSBC has an identical form, V0 = Vg/(1 −Deff), to that of the conventional boost converter, except that ituses an effective duty ratio Deff = (D − ΔD), where ΔD isthe duty ratio loss due to the soft switching.
Generalized state-space averaging (GSSA) is one of the well-established techniques employed for modeling soft-switchingPWM dc–dc converters [35]. However, this model formulation
TABLE IHSBC PARAMETERS
methodology assumes variables associated with the resonanttank (Lr, Cr) as input control variables, rather than as statevariables. In view of this, the resulting model accuracy is low.To improve the model accuracy, a larger number of harmonicsneed to be included in the GSSA model. This increases theorder of the model, and its mathematical analysis now becomesmuch more complex. To alleviate some of these problems,system identification techniques have been reported in theliterature for modeling switch-mode dc–dc converters [36]–[38]. The advantages of these techniques are as follows: 1) Theinternal structure of the converter need not be known in advanceas long as one can obtain a satisfactory statistical distributionof the data; 2) in some cases, this approach is very effectiveat generating a reduced-order model to represent a complexsubsystem of the distributed power electronic system; and3) this method is particularly useful in a SMPS where thereare many modes of operation and where there is difficulty infinding the duty ratio of each mode operation, etc.
Although several system identification tools can be em-ployed for soft-switching converter model formulation, here,a Box–Jenkins [35]–[39] methodology is used for the HSBCdiscrete-transfer function generation. Taking the designed con-verter parameters, firstly, the HSBC is formulated in a Simulinkplatform, and then, the response of the desired parameter isgenerated for a given range of perturbation of the predefinedparameter. Here, the perturbation range and sampling frequencyof the perturbing signal and the duty ratio play an importantrole in the accuracy of the final transfer functions generated.Hence (in the converter discrete-transfer function generation),the control duty ratio range must be chosen judiciously in orderto get accurate transfer functions. For a given source voltageand load resistance range, shown in Table I, the duty ratiovaries between 0.3 and 0.7, and this is used as the range for theperturbation duty ratio control signal. Taking these boundaries,equally spaced intermediate points with a step time equal to thesampling time period are generated using a random generator.This signal is then compared with the triangular ramp and usedto generate an equivalent duty ratio signal which is used to drivethe switching device of the converter. Since there is a perturba-tion in the converter, various current and voltage quantities willhave corresponding variations. In order to find the converterdiscrete-transfer function of interest, the corresponding samplesof current or voltage and the perturbation signals are passed onto the system identification toolbox of MATLAB [41]. In this
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2885
Fig. 2. Block diagram of the digital PID controlled HSBC.
toolbox, the user has the option to choose a linear parametricmodel formulation methodology and its fitting order for thegiven input–output data pattern. Once these are decided, then,the model is estimated, and its accuracy is verified by residualanalysis. If the residual of the model is within the allowableconfidence interval, then the corresponding estimated modelrepresents the true behavior of the converter. Although it ispossible to establish various discrete-transfer functions for theHSBC, only the transfer functions which are useful for robustcontroller design are estimated and then used in the controllerdesign.
For a given load power demand, source, and load voltages,the power stage parameters L and C are designed such that theinductor current ripple is less than 20% of the load current andthe load voltage ripple is less than 5% of the load voltage usingthe following design equations: L = D(1 − D)2RI0/(fsΔIL)and C = (1 − D)V0/(RfsΔV0). The resonant tank circuit isdesigned such that its time constant is five times lower than thepower stage time constant as per the design procedure discussedin [13], and the corresponding design equations are as follows:Lr = Zr/ωr and Cr = 1/(Zrωr).
III. RPIDC DESIGN FOR THE HSBC
A. Digital PID Controller Design Through Pole Placement
Fig. 2 shows the digitally controlled HSBC system, where theloop gain is defined by TL(z−1) = Gcr(z−1)Gvd(z−1). Here,we need to design a robust digital PID controller (RPIDC)Gcr(z−1) such that the load voltage is constant irrespective ofthe uncertainties in the converter parameters, the disturbancescaused by the input dc bus, or load fluctuations. The selec-tion of the compensator is more important, and its structuredepends on the order of the converter system. The converterunder consideration is the second order, and hence, simplecompensators, like one-zero–one-pole or one-pole–two-zerodesigns, will not be suitable as they will not provide a sufficientgain margin (GM) or phase margin (PM). The option left tothe designer is a high-order compensator: a minimum of twozeros and two poles. Several other types of higher-order digitalcompensators [29] can easily be designed for this converter, butfor the sake of simplicity, both from the point of view of thedesign and implementation, the second-order compensator witha two-pole and two-zero configuration is sufficient in order torealize the performance tradeoffs. Although this compensator
is simple to implement, the judicious selection of the pole-zero(PZ) location is required to meet the robustness performancespecifications [30]–[34]. A digital PID controller, of a three-branch-structured RST controller shown in Fig. 2, is designedin this paper in order to ensure load voltage regulation androbustness against converter parameter uncertainty as well asstep source and load rejection. Using the well-known pole-placement technique (PPT), the RPIDC can easily be designedfor the HSBC. However, such pole-placement design may notsatisfy all the control specifications, and hence, the probabilityof achieving regulation under all possible operating conditionsof the converter is low. In order to ensure load voltage regula-tion, together with acceptable robust performance, for a givenclass of converter parameter uncertainty, the PPT must be com-bined with sensitivity function shaping (SFS). Here, SFS givesadditional flexibility to obtain a certain performance and to en-sure some robustness with respect to unstructured uncertainty.To this effect, here, a design procedure is developed basedon a combination of the PPT and SFS methods such that theresulting controller meets predefined robustness specifications.
A block diagram of the closed-loop converter (CLC) isshown in Fig. 2. The problem here is to design the R-S-Tcontroller polynomials such that the CLC is stable and robustagainst converter parameter uncertainty. Since the goal of theseinvestigations is to design an RPID, which is equivalent toa standard R-S-T controller with T = R as shown in Fig. 2,where the R and S polynomials need to be designed, takingthe robust performance specifications into account, let the con-verter model and controller be defined by the transfer functionsGvd(z) and Gcr(z−1), respectively, represented in terms of thenumerator and denominator polynomials as
Gvd(z−1) =B(z−1)/A(z−1) (1a)
Gcr(z−1) =R(z−1)/S(z−1) (1b)
where B(z−1) = (b0 + b1z−1 + b2z
−2), A(z−1) = (a0 +a1z
−1 + a2z−2), R(z−1) = k(1 − α1z
−1)(1 − α2z−1) =
[r0 + r1z−1 + r2z
−2], and S(z−1) = (1 − γ1z−1)(1 −
γ2z−1) = [q0 + q1z
−1 + q2z−2], and they do not have any
common factors. The CLC transfer function between the loadvoltage and the reference is
Hcl(z−1) =B(z−1)R(z−1)
P (z−1)(2a)
P (z−1) =[A(z−1)S(z−1) + B(z−1)R(z−1)
]
=Pd(z−1)Pa(z−1). (2b)
In the PPT, the controller (R,S) is designed such that the CLSpoles are located at the desired locations. Let Xdchp(z−1) bethe desired characteristic polynomial (CHP) defined as
Xdchp(z−1)=(1−β1z−1)(1−β2z
−1)(1−β3z−1)(1−β4z
−1)
=[1+k1z−1+k2z
−2+k3z−3+k4z
−4] (3)
where k1 = −(β1 + β2 + β3 + β4), k4 = (β1β2β3β4), k2 =−[β1β2+β3β4+(β1+β2)+(β3+β4)], and k3 = [β1β2(β3 +
2886 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
β4)+β3β4(β1+β2)]. Substituting the A(z−1), B(z−1), R(z−1),and S(z−1) polynomials in (2b) and comparing with the desiredCHP Xdchp(z−1) give a system of four equations with fourunknowns. This system of equations, [M ][x] = [β], can easilybe solved using matrix inversion, and its equivalent form is
[x] = [M ]−1[β] (4)
where
[M ] =
⎡⎢⎣
a0 0 b0 0a1 a2 b1 b0
a2 a1 b2 b1
a2 0 0 b2
⎤⎥⎦ [x] =
⎡⎢⎣
q1
q2
r1
r2
⎤⎥⎦
[β] =
⎡⎢⎣
(k1 − a1q0 + b1r0)(k2 − a2q0 + b2r0)
k3
k4
⎤⎥⎦ .
From the aforementioned analysis, it is possible to computecontroller parameters Gcr(z−1) by placing closed-loop polesat the desired locations within the unit circle. However, sucha PPT may give a satisfactory fixed-point controller but maynot yield robust performance against converter parameter un-certainty or may exhibit poor dynamic performance in terms ofthe step source and load rejection.
In order to achieve load voltage regulation, together withan acceptable range of robustness, the CLC poles P (z−1) aredivided into dominant and auxiliary poles. Here, Pd(z−1) isthe polynomial corresponding to the CLC dominant poles,which are chosen to satisfy the desired load voltage regulationnominal performance. The second polynomial Pa(z−1) consistsof the auxiliary poles of the CLC, and their locations mustbe chosen judiciously such that the converter system exhibitsacceptably robust performance and is capable of rejecting stepload and source variations. In this context, the sensitivity func-tions provide a useful means for arriving at a robust controller.Their shaping, to achieve acceptably robust performance, needsthe rearrangement of poles, depending on the actual converternature, type, and range of expected parameter uncertainties.The detailed description of various sensitivity functions, theirdependence on converter behavior, and robust performancerequirements is discussed in the following paragraphs.
B. Formulation of Sensitivity Functions
The sensitivity functions play a key role in the CLC system’sstability as well as in its robustness performance againstparameter variation. Normally, these functions are shapedin order to ensure nominal performance for the rejection ofthe step load and source disturbances and the stability ofthe CLC system in the presence of a model mismatch. TheCLS performance is completely characterized by six differentsensitivity functions. Although these sensitivity functions caneasily be established from the general system analysis point ofview [24], for the regulation of power supplies, the followingsensitivity-indicating transfer functions (STFs) completelycharacterize the CLC system stability and robustness: 1) load
Fig. 3. SFG of the digital PID controlled HSBC.
voltage sensitivity against step disturbance defined as outputsensitivity Syp; 2) disturbance to control input defined as inputsensitivity Sup; and 3) measurement noise to output defined asnoise sensitivity Syb.
A properly designed dc–dc converter has to meet perfor-mance specifications, and these can be readily expressed interms of various sensitivity functions. The robustness againstconverter parameter variation, either in converter parameters orin an operating point, is easily captured through the sensitivityfunctions, and hence, a design based on the shaping of thesefunctions results in a realistic controller, which ensures loadvoltage regulation, rejects step load and source disturbances,and is also robust over the specified range of converter parame-ter variations. The formulation and detailed description of thesesensitivity functions, in the discrete-time domain, for powersupplies are given in the following equations.
Syp(z−1) =A(z−1)S(z−1)
P (z−1)(5a)
Sup(z−1) =−A(z−1)R(z−1)
P (z−1)(5b)
Syb(z−1) =−B(z−1)R(z−1)
P (z−1). (5c)
A transfer function analysis of the control loop is extremelyuseful in identifying clearly the performance objectives of thecontroller design problem. Now, let us formulate the mathemat-ical expressions for the previously defined sensitivity functionsin terms of the converter and controller quantities using theblock diagram shown in Figs. 2 and 3. For a given constantreference, the load voltage (v0) depends on the control input (d)and disturbing inputs which are the magnitudes of the sourcevoltage (vg) and the load demand (i0) on the converter. Withoutany closed-loop controller, the load voltage can be written,from Fig. 3, as
v0(z−1) = Gvg(z−1) • vg(z−1)
+ Z0(z−1) • i0(z−1) + Gvd(z−1) · d(z−1) (6)
where Gvg(z−1)= v0(z−1)/vg(z−1), Z0(z−1)= v0(z−1)/i0(z−1),and Gvd(z−1) = v0(z−1)/d(z−1). From the signal flow graph(SFG) shown in Fig. 3, using Mason’s gain formula, itis straightforward to establish closed-loop transfer func-tions v0(z−1)/d(z−1)|vg ,i0=0, v0(z−1)/i0(z−1)|vg,d=0, and
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2887
v0(z−1)/vg(z−1)|d,i0=0, and then, the load voltage, due to thecombined effect, is described by
where Syp(z−1)=1/[1+TL(z−1)], TL(z−1)=Gc(z−1)Gvd(z−1).The output sensitivity function must be shaped properly in orderto make the load voltage insensitive to the converter parameteruncertainty, step source, and load perturbations defined byGvg(z−1), Z0(z−1), and [vg(z−1) & i0(z−1)], respectively. Thetransfer function that defines the effect of measurement noiseon the load voltage is obtained by setting the perturbing inputs(vg, i0) in Fig. 3 to zero as follows:
v0(z−1) = Syb(z−1)[n(z−1)
](8)
where Syb(z−1) = TL(z−1)/[1 + TL(z−1)]. In dc–dc con-verter voltage regulation problems, the measured voltage issuperimposed on the switching noise components, and the noiseenergy is mostly concentrated at these high frequencies. In or-der to make the load voltage insensitive to these noise frequencycomponents, this sensitivity transfer function must have a flatgain response of 0 dB in the low-frequency region while it mustroll off in the high-frequency region for better noise attenuation.Combining (6) and (7) gives the load voltage dependence on thetwo important sensitivity transfer functions as
v0(z−1) = Syp(z−1)[SSLS(z−1)
]+ Syb(z−1)
[n(z−1)
](9)
where SSLS(z−1)=[Gvg(z−1) • vg(z−1)+Z0(z−1) • i0(z−1)].This equation plays a key role in the design of the controlleras it ensures the following: 1) CLC stability; 2) step sourceand load disturbance rejection; and 3) noise suppression. Inorder to make the load voltage insensitive to disturbancesand noise, SSLS(z−1) and n(z−1) and the coefficient transferfunctions Syp(z−1) and Syb(z−1) need to be shaped properlyby assigning suitable PZ locations to the desired CHP.
In a properly designed CLC system, to ensure load voltageregulation against the step load and source disturbances, theduty ratio control signal has to undergo variations. To absorbthis effect, the controller must be designed properly such thatit reacts quickly enough to disturbances and a control signalof suitable magnitude is generated, which must be within theallowable range. In order to understand this phenomenon, thefollowing mathematical analysis is performed. In the SFGshown in Fig. 3, there exists only one loop, and its looptransmittance is LT = −Gc(z−1)Gvd(z−1). The forward pathbetween disturbance signal (p) and control duty ratio (d) is(p − x2 − v0 − x3 − x1 − d), and its transmittance is pT =−Gc(z−1). There are no nontouching loops in the forward path“pT ,” and hence, ΔT = 1; Δ = (1 − LT ). Using Mason’s gainformula(pT ΔT /Δ), the CLC control signal dependence on thedisturbance is
d(z−1) =[Sup(z−1)
] [p(z−1)
](10)
where the control input sensitivity function Sup(z−1) =−Gc(z−1)/[1 + TL(z−1)]. Equations (9) and (10) completely
Fig. 4. NP indicating modulus, gain, and phase margins.
define the CLC dynamical behavior and its duty ratio signalvariation against disturbances. There are three important sen-sitivity transfer functions Syp(z−1), Syb(z−1), and Sup(z−1),and here, the controller Gcr(z−1) must be designed such thatall the STFs are within the template boundaries defined by therobust stability performance parameters. The significance ofthese STFs is explained in the following section.
C. Digital Controller Robustness Verification
The CLC system will be robust if its stability is guaranteedfor a given set of converter parameter uncertainties. Theoreti-cally, the robustness of the CLC is related to the minimal dis-tance on the Nyquist plot (NP) between the nominal operatingcondition and the critical point (−1 + j0), as shown in Fig. 4,as well as to the frequency characteristics of the modulus ofthe sensitivity functions. In view of the parameter uncertainties,the conventional frequency domain GM and PM specificationsare inadequate measures to quantify the robustness of the CLCsystem. For complete CLC system stability and robustnessquantification [30], the following four important parametersneed to be evaluated.
1) GM: The GM indicates the additional gain that wouldtake the closed loop to the critical stability condition. It isequal to the inverse of the TL(z−1) gain for the frequencycorresponding to a phase shift ϕ = −180◦. This must beat least 6 dB.
2) PM: The PM quantifies the pure phase delay that shouldbe added to achieve the critical condition, and its rangefor a stable system is 300 ≤ φ ≤ 700.
3) Modulus margin (ΔM): This quantity gives a measure ofthe robustness, and it is defined as the distance betweenthe stability point (−1 + j0) and TL(z−1). In mathemati-cal terms, it is ΔM = |1 + TL(z−1)|min. For a stable androbust CLC, it must be greater than -6 dB.
4) Delay margin (Δτ): The delay margin represents thedelay that can occur in the open-loop system before theCLC system becomes unstable. This gives an alternativeway of expressing the PM, and if the NP intersects theunit circle at several frequencies (ωi), then it is given byΔτ = mini(Δφi/ωi). A stable CLC system must haveΔτ > Ts.
2888 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
From a robust control point of view, the performance objec-tives of a feedback system can usually be specified in termsof the requirements on the sensitivity functions Syp(z−1),Syb(z−1), and Sup(z−1). Hence, the controller must be de-signed by shaping the frequency-response characteristics ofthese three sensitivity functions to achieve the following designrequirements: 1) load voltage regulation to set-point reference;2) rejection of noise, step source, and load disturbances; and3) stability and robust performance against converter parameteruncertainty. To achieve these design objectives [34], the follow-ing performance specification bounds must be ensured.(a) Reference or set point tracking
|e||r| =
∣∣Syp(z−1)∣∣ < εr, ∀ω ∈ [0, ωr]. (11)
(b) Disturbance rejection
|y||p| =
∣∣Syp(z−1)∣∣ < εp, ∀ω ∈ [0, ωp]. (12)
(c) Stability robustness∣∣Syr(z−1)
∣∣ < 1/∣∣δm(z−1)
∣∣ . (13)
(d) Measurement noise to control signal noise rejection∣∣Sup(z−1)
∣∣ < εn, ∀ω ∈ [ωn, ωp]. (14)
The physical significance of the bound εr, over the frequencyrange [0, ωr], on Syp is to maintain a constant load voltage evenunder source and load fluctuations. Larger values for εr and εp
indicate poor performance as well as poor robustness. In thefrequency domain, the maximum amplitude of the frequencyresponse of the transfer function is obtained by computing thenorm of H∞. Thus, the norm of H∞, represented as ‖ • ‖∞,gives an important measure of gain, often used in controller de-sign for measuring the peaks of the sensitivity functions. Hence,εr = ‖Syp(z−1)‖∞ represents the maximum magnitude of theoutput sensitivity function, for all possible parameter variations,in the frequency range [0, ωr]. Furthermore, the modulus ofthe inverse of the output sensitivity function gives, at each fre-quency, the distance on the TL(z−1) NP relative to the criticalpoint (−1 + j0). To maintain the CLC stability, the loop gaintransfer function TL(z−1) must be far away from the (−1 + j0)point. Furthermore, the tangential distance from (−1 + j0) toTL(z−1), |1 + TL(z−1)|, gives the modulus margin. Thus, forrobust stability, ΔM ≥ (1/εr). Therefore, the modulus marginfrequency template is the upper bound on the output sensitivityfunction Syp. The noise-output sensitivity function Syb allowsthe definition of a frequency template to ensure that the delaymargin constraint is fulfilled. For a delay margin of k samplingperiods [24], the robust stability condition is
∣∣Syb(z−1)∣∣ < 1/
∣∣δm(z−1)∣∣ (15)
where δm(z−1) = (z−k − 1). From (5a) and (5c), it is easy toestablish the identity Syp(z−1) − Syb(z−1) = 1, and therefore,the range on Syp is obtained as
The aforementioned relationship shows the interdependenceof the sensitivity functions Syp(z−1) and Syb(z−1). In view ofthis, formulating a bound on Syp(z−1) automatically sets thebound on Syb(z−1).
The input sensitivity function gives information on the dutyratio control signal, in the frequency domain, against distur-bances. Since uncertainties in the converter parameters areunavoidable, in such cases, the controller may generate ex-cessively high duty ratio control signal against disturbances.In order to ensure the robust stability of the CLC system, theSup must be shaped, and an upper bound (εn) must be set athigh frequencies. In a tradeoff design, the Sup must be shapedproperly such that its magnitude is low in the frequency regionwhere the converter gain is very low [24]. From the aforemen-tioned analysis, it can be noted that the sensitivity functionsdescribe the robust stability of the CLC system with respect tomodel/parameter uncertainty [31]. Bounds on the magnitude ofthe frequency-dependent model uncertainties convert to upperconstraints on the sensitivity functions. These upper boundconstraints, together with the modulus and delay margins, resultin the desired templates for the sensitivity functions, and theirtypical sample templates are shown in Fig. 5.
The step-by-step RPIDC design procedure is discussed in thefollowing list.
Step 1: For the nominal operating conditions, formulatethe control-to-output z-transfer function of the HSBC,Gvd(z−1). Define the bounds on the sensitivity functionsdepending on the nominal performance and robust stabilityrequirements.
Step 2: Choose the desired pole locations of the CLC system,which involves the identification of the dominant andauxiliary poles. The dominant pole locations are basedon the nominal performance requirements of the CLCwhile the auxiliary pole locations depend on the controllerrobustness requirement.
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2889
Step 3: Choose the PZ configuration of the controller, Gcr(z−1).Just like the CLC, the poles are divided into dominantand auxiliary poles, and here, the controller numerator(R(z−1)) and denominator polynomials (S(z−1)) are alsoexpressed in the factored form indicating the fixed andflexible parts. Choose the fixed part of these polynomialsin order to meet the predefined performance requirements.In voltage regulation problems, it is necessary to providean integral action by choosing the denominator polynomialfixed part Sf (z−1) = (1 − z−1) so that the controller ef-fectively eliminates the steady-state error. In the same way,placing a pair of complex zeros in R(z−1) or in S(z−1)decreases the magnitude of the modulus of the sensitivityfunctions around the frequencies of these zeros.
Step 4: Solve (4), and then, formulate the controller polynomi-als R(z−1) and S(z−1).
Step 5: Use the previously computed controller, and then,generate the sensitivity functions, defined by (5), for theexpected parameter variation. Check that all the sensitivityfunctions are within the prespecified boundaries. If any ofthese extend beyond the boundaries, then the followingmodifications are helpful in bringing the sensitivity transferfunctions within the defined templates. If the maximum ofSyp is located in the frequency range next to the attenuationband, then using a different damping factor, between 0.3and 0.8, to the dominant poles brings the magnitude of Syp
below the admissible value. If the maximum of the outputsensitivity function is located in the high-frequency range,then shift the auxiliary poles toward the high-frequencyregions so that the Syp maximum shifts toward the lower-frequency region. A similar exercise needs to be adoptedeven for reshaping the Sup sensitivity function.
Step 6: Repeat Steps 2–5 until the designed controllerGcr(z−1) satisfies the stability and robust performancespecifications.
Any controller which is stable and maintains load voltageregulation may not necessarily satisfy all the robust perfor-mance specifications. However, the controllers which have beendesigned based on the previously defined step-by-step designprocedure, involving the shaping of sensitivity functions whichare formulated according to the robust control theory, arecertain to meet all the specifications.
IV. RESULTS AND DISCUSSIONS
In order to confirm the robust control concepts, developedearlier and discussed in the preceding sections, simulation andexperimental studies have been carried out on a prototype soft-switching boost dc–dc converter. A 60-W 50-kHz 24–42-VHSBC is considered here to demonstrate the design concept.Using a steady-state analysis, as discussed in Section II, theconverter parameters have been designed, and the correspond-ing component values are listed in Table I. Discrete-timemodels have been formulated, based on the analysis givenin Section II, and then used in the RPIDC design. For theparameters listed in Table I, the control-to-output transfer func-tion is obtained from the system identification methodology and
Fig. 6. Comparison of control-to-output transfer function accuracy obtainedfrom three different methods.
GSSA, respectively, [35], [36], as explained in Section II, asfollows:
In order to compare the accuracy of this transfer function,the frequency response of the control-to-output small-signaltransfer function is also generated using the following: 1) theGSSA method and 2) the PSIM power electronic simulator.These frequency response plots are shown in Fig. 6. From this,it is clear that the transfer function obtained from system iden-tification is closely matching with the frequency response ob-tained from the PSIM simulator while the GSSA-based modelexhibits significant deviation in the high-frequency region. Inview of this deviation, any given digital controller will yielddifferent GM, PM, and crossover frequencies. Furthermore,this deviation affects significantly the loop-gain design, andsometimes, the direct use of such digital controllers may lead toan unstable closed-loop converter system on account of lowerstability margins.
2890 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
We proceed to design a robust controller directly in thez-domain, in the MATLAB [41] environment, using the step-by-step procedure given in Section III-C. For the given A(z−1),B(z−1), R(z−1), and S(z−1), the characteristic equationP (z−1) results in a fourth-order polynomial. Now, we have tochoose the desired CLC poles β1–β4 of Xdchp(z−1). As alreadypointed out in Section III-A, the desired CLC poles are dividedinto dominant and auxiliary poles, which are spread within theunit circle and are also responsible for achieving the desiredload voltage regulation performance. Here, first, we choose thedominant pole locations by specifying the damping ratio (0.6 <ξ < 1) and frequency (ωn) corresponding to the slowest poleof the converter. The poles and zeros of the HSBC for nomi-nal operating conditions are pole1,2 = (0.9430 ± j0.0505) andzero1 = −1.4525, and the frequency of the slowest pole1,2
is ωn = 3920 rad/s. The aim is to design a proper controller,where the controller transfer function numerator and denomi-nator polynomials are of equal degree, using a PPT to achieveload voltage regulation as well as robust performance. In thePPT, the system order gives the basis for the controller anddesired CHP order selection. For an nth order system [38], thecontroller and CHP order are (n − 1) and (2n − 1), respec-tively. Since the converter under consideration is of the secondorder (n = 2), the controller and CHP order are one and three,respectively. We first assign the desired CHP poles to p1,2 =0.97 (ξ = 1 and ωn = 1520 rad/s) and p3 = 0.94 (ξ = 1and ωn = 3090 rad/s), formulate Xdchp(z−1), and then solve(4) to obtain the controller polynomials R(z−1) and S(z−1),and the resulting controller is
Gc1(z−1) =−0.16152(1 − 1.007z−1)
(1 − 0.9931z−1). (18)
As the low-frequency gain associated with this controlleris low, the achievable stability margins are also smaller inmagnitude. In view of these, the robustness range of thiscontroller is restricted. Furthermore, there is a possibility ofhaving a steady-state error in the load voltage due to the lackof a pole at z = 1. To demonstrate this fact, as well as to see thesensitivity function dependence, the three STFs are generatedfor the variable load (R = 25 → 40 Ω) and source voltages(Vg = 20 → 28 V) as shown in Fig. 7. The output sensitiv-ity function is touching the modulus margin limit. Althoughthe noise sensitivity (Syb) is within the templates meetingthe allowable limits, the input sensitivity (Sup) variation athigh frequencies is very small. For this reason, the controllermay not generate a sufficient duty ratio in order to maintainconstant load voltage, and hence, its disturbance rejection ca-pability is low. This controller is suitable only for nominaloperating conditions, and it is not robust against parametervariations.
To eliminate the steady-state error problem, the CHP polesare now reassigned, p1,2 = 0.973 (ξ = 1 and ωn = 1370 rad/s)and p3 = 0.9405 (ξ = 1 and ωn = 3070 rad/s), such that theresulting controller has a pole at z = 1 and the correspondingcontroller transfer function is
Gc2(z−1) =0.14757(1 − 1.022z−1)
(1 − z−1). (19)
Fig. 7. Sensitivity functions with Gc1(z) controller.
Since this controller has a pole located at z = 1, the CLC sys-tem exhibits a zero steady-state error against the step changes.The robustness of this controller has been verified for the givenparameter uncertainty, and the corresponding STFs are drawnin Fig. 8. For the assumed parameter variation, the Syb and Sup
sensitivity functions meet the allowable limits, but the outputsensitivity function (Syp) exceeds the modulus margin limits.This deviation clearly indicates that this controller is unableto meet the modulus margin limits, and hence, the controllerrobustness is also restricted. Other combinations of the polesp1−p3 may not yield compensator configurations with a polelocated at z = 1, and the corresponding controllers are unableto meet steady-state error limits. In view of this limitation, otherpossible controllers, one zero-one pole configuration, are notdiscussed here.
The aforementioned discussion suggests that the one zero-one pole configuration is unable to fulfill simultaneously thedynamic and steady-state requirements of the HSBC. The
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2891
Fig. 8. STFs with Gc2(z) controller.
inclusion of an additional PZ pair gives more flexibility inreshaping the loop gain characteristic as well as the sensitivityfunctions, and thus, second-order controller configurations arenow considered. In order to meet the CLC system performancespecifications, the controller needs to satisfy certain additionalconstraints. A standard requirement for most controllers is that,in the steady state, the nominal control loop should yield zerocontrol error due to step disturbances. For this to be achieved,a necessary and sufficient condition is that the nominal loopshould be internally stable [40] and that the digital controllershould have at least one pole located at z = 1. Some ofthese requirements can be satisfied by the polynomial poleassignment approach by ensuring that extra poles or zerosare introduced. By introducing one pole for the system un-der consideration, the CHP order now becomes 2n = 4, andthe corresponding controller order is n = 2. Furthermore, onepole is fixed at z = 1 so that all the controllers of the twopole-two zero configurations are free from steady-state errorlimitations.
Fig. 9. STFs with Gc3(z) controller.
With a fourth-order characteristic polynomial, we begin withthe following pole assignment p1,2 = 0.973 (ξ = 1 and ωn =1370 rad/s), p3 = 0.7 (ξ = 1 and ωn = 0.8 krad/s), and p4 =0.8 (ξ = 1 and ωn = 11.2 krad/s) to Xdchp(z−1); then, itssolution, (4), results in the controller polynomials R(z−1) andS(z−1), and the corresponding controller is
Gc3(z−1) =2.542[1 − 1.966z−1 + 0.9675z−2]
[1 − 1.5734z−1 + 0.5734z−2]. (20)
With this controller, the STFs are generated for the expectedparameter uncertainty, and the corresponding plots are shownin Fig. 9. From these STFs, it is clear that the maximumoutput sensitivity is |Syp(z−1)| = 1, satisfying the constraint|Syp(z−1)|max < 2. However, the input sensitivity function Sup
has a larger magnitude at high frequencies, indicating that theduty ratio control signal of the HSBC may exceed its upper limit
2892 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
in the presence of disturbances of higher magnitudes. Hence,there is a need to look into other possible pole locations toreshape the Sup in the high-frequency region while enforcingthe boundaries on the other two sensitivity functions such thatthe resulting controller has robust control performance.
The main requirement of the CLC is that its transient re-sponse be sufficiently fast and sufficiently damped. This re-quirement necessitates a finite value of damping (0 < ξ < 1)which must be present in the CLC, and this can be achievedby introducing dominant complex conjugate poles in the CHP.Here, the real part of the complex conjugate pair controls thespeed of the response while the imaginary part determinesthe overshoot. In the case of a four-pole CHP, the dominantpole is the complex conjugate pair β1,2 = α1 ± jα2, (α2
1 +α2
2 < 1), while the auxiliary faster poles should be locatedat β3,4 = α1 − Δα, (Δα < α1), where α2 and Δα need tobe chosen depending on the required range of robustness andthe type of expected uncertainties in the converter system.In the discrete-time domain, the dominant poles must be withinthe circle of radius “r” (|r| < 1) whose center is at the origin.The radius of this circle depends on the ξ and ωn of thedominant poles (|r| ≤ e−ξωnTs). Assume that ωn = 3920 rad/s,which corresponds to the frequency of the slowest pole ofthe converter pole1,2, and that the damping (0.6 < ξ < 0.9)results in (0.93 < α1 < 0.95) and (0.034 < α2 < 0.0627). Forξ = 0.7, the pole locations are β1,2 = (0.9466 ± j0.056) andβ3,4 = (0.9466 − Δα).
Considering the dominance of the poles, one can chooseΔα > (4α1/5), but the inherent properties of the HSBC as wellas the robustness requirements will not allow such a selection.Furthermore, for a fixed-point nominal operating condition,one can easily generate different sets of CHP poles just bychoosing the appropriate value of Δα. However, to ensure CLCstability as well as to realize the desired robust performance,“Δα” must be chosen judiciously such that the CLC systemSTFs are within predefined templates. Respecting the STFsensures minimum stability margins for the CLC system evenunder the worst case of the expected operating point. It is betterto start with “Δα = 0,” and by progressively increasing it inthe forward direction, one can reach the desired location in asmaller number of iterations. Starting with Δα = 0 gives theCHP poles as β1,2 = (0.9466 ± j0.056) and β3,4 = 0.9466,and the corresponding controller is
Gc4(z−1) =0.23877[1 − 1.881z−1 + 0.8867z−2]
[1 − 1.9017z−1 + 0.9017z−2](21)
which gives GM = 53 dB, PM = 660, DM = 34 samples,and MM = 1.234 at the nominal operating condition. Al-though this controller is capable of regulating the load voltageboth at the nominal operating condition and under distur-bances, its starting performance has an overdamped nature.Furthermore, the output and noise sensitivity functions shownin Fig. 10 are within the allowable limits, but the Sup sensitivityfunction is low at high frequencies, indicating that the controllermay not generate a duty ratio signal of high enough magnitudefor load voltage regulation against high-frequency disturbances.MATLAB simulations have been performed for several dif-
Fig. 10. STFs with Gc4(z) controller.
ferent combinations of (α1,Δα), and in each case, the CLCperformance has been tested for stability and robustness. Thefollowing CHP poles β1,2 = (0.96 ± jα2) and β3,4 = 0.9 re-sult in a robust controller with the following characteristics:1) respecting the sensitivity functions for the expected param-eter variation; 2) resulting in an almost critically dampedstarting response under nominal operating conditions; and3) better disturbance, source, and load rejection. The corre-sponding robust controller configurations, for three differentvalues of α2(= 0.01, 0.05, 0.065), are
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2893
Fig. 11. STFs with Gcr2(z) controller.
By taking these controllers, various stability margins havebeen obtained, and it is found that they are within allowable lim-its. Furthermore, sensitivity functions indicative of robustnesshave also been generated for load (R = 40 → 25 Ω) and sourcevoltage (Vg = 20 → 28 V) variations as shown in Fig. 11 forGcr2(z−1). The aforementioned theoretical analysis providesinsight into robust controller design, and to validate this designin reality, one must verify its practicability with regard to con-verter dynamics and the required standard of control quality interms of the maximum allowable overshoot, accuracy, settlingtime, etc. To this effect, a prototype HSBC CLS has beenbuilt and tested under nominal controller conditions and forrobustness. The detailed discussions are given in the followingparagraphs.
To verify the digital controller design methodology and itsrobustness, as discussed earlier, simulations have been per-formed on the PSIM platform [42] and then verified witha laboratory prototype converter system. To demonstrate therobustness of the designed controller, variations in the supplyvoltage and load were created. It is assumed that a constant
Fig. 12. Simulated starting response of the load voltage with different sourcevoltages (R = 30 Ω; CV1 = 28 V; CV2 = 24 V; CV3 = 20 V).
Fig. 13. Simulated starting response of the load voltage with different sourcevoltages (R = 30 Ω; CV1 = 28 V; CV2 = 24 V; CV3 = 20 V).
source voltage (CV ) has possible relative fluctuations of ±15%about the nominal value (Vg : 20 → 28 V); similarly, the rela-tive load variation is about ±20% of the nominal value (R :25 → 40 Ω). The simulation results obtained with the robustcontroller Gcr2(z−1), shown in Figs. 12 and 13, indicate thefollowing: 1) a start-up response that is critically damped andexhibits a minimum rise time at the nominal operating condi-tion; 2) a better load voltage regulation against disturbancessuch as source voltage (Vg : 20 → 28 V) and load variation(R : 25 → 40 Ω), with a minimum settling time; and 3) overor undershoots during the step source and load variations areless than 12%.
To validate the theoretical analysis that has been devel-oped and the simulation results, a laboratory prototype CLCsystem has been built and tested for regulation and robust-ness. The digital control algorithm has been implemented us-ing a dsPIC30F6010 digital signal controller [43]. The de-vices used in the prototype converter circuits are as follows:switch IRF540, diode MUR860, driver circuit IR2110, andoptoisolator 6N137. The load voltage is sensed and is broughtwithin the range (0–5 V), which is passed on to the onboardanalog-to-digital converter of the dsPIC. The digital controllersGc1(z−1)−Gc4(z−1) and Gcr1(z−1)−Gcr3(z−1) were trans-formed into discrete-time forms and then listed in Table II forready use in experimentation.
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TABLE IIDIGITAL CONTROL LAWS FOR DIFFERENT CHP POLES
First, the controller Gc1(z−1) load voltage regulation capa-bility has been tested against the load change R : 25 → 40 Ω,and the measured dynamic response is plotted in Fig. 14(a). Itis clear that this controller exhibits a steady-state error in theload voltage due to the lack of a pole at z = 1. The controllerGc2(z−1) load voltage regulation capability has been testedagainst the load change R : 25 → 40 Ω for different sourcevoltages (CV1 = 28 V, CV2 = 24 V, and CV3 = 20 V) asshown in Fig. 14(b). Although this controller is regulatingthe load voltage and rejecting the load disturbances for CV1,a considerable steady-state error in the load voltage can beseen for other operating conditions, such as CV2 and CV3.Hence, this controller is not suitable for ensuring the predefinedrobustness range. A similar kind of dynamic response tests havebeen conducted on the HSBC with the Gc3(z−1) and Gc4(z−1)controllers, and the measured dynamic responses, plotted inFig. 14(c) and (d), reveal that they are not robust for the CV3
case. Although the digital controllers Gcr1(z−1)−Gcr3(z−1)are robust as the STF variation, against parameter uncertainty,is within the admissible limits as shown in Fig. 11, the cor-responding dynamic response results plotted in Figs. 15 and16 suggest that Gcr1(z−1) needs more time to respond whileGcr3(z−1) is faster in response with oscillatory behavior. On theother hand, Gcr2(z−1) exhibits tradeoff dynamic performanceand less response time, together with minimum oscillations, andsuch a controller would be better from the robustness point ofview. The measured starting response of the load voltage withthe Gcr2(z−1) controller is obtained for three different voltages,as shown in Fig. 17, and it is clear that the dynamic response isalmost critically damped for the nominal operating condition.
The robustness of the controller against parameter variationis also verified. Although several parameters can be variedeither simultaneously or one parameter can be varied at a timeand, in each case, the robustness of the controller as well as itsregulation capability can be recorded, for illustration, here, thecontroller robustness and regulation are measured against thefollowing: 1) gradual source voltage variation; 2) gradual loadvariation; and 3) inductance L variation. For the inductancevariation, an E-Ecore is used, and its L-variation is created by
Fig. 14. Measured dynamic response of the load voltage with differentcontrollers (different source voltages: CV1 = 28 V, CV2 = 24 V, and CV3 =20 V). (a) With Gc1(z−1). (b) With Gc2(z−1). (c) With Gc3(z−1).(d) With Gc4(z−1).
introducing an air gap. Initially, the circuit operates with anair gap in the inductor L, and it is varied by bringing the E-Ecores together. Experimental results (inductor current and loadvoltage) have been recorded for these variations and plottedin Fig. 18. It can be noted that the controller Gcr2(z−1) isyielding robust performance even for L-variation (L : 260 →320 μH). For a given load, the robustness of the controlleragainst supply voltage variation is also verified as shown inFig. 19. It can be seen that, for the parameter variation fallinginside the robustness range, the controller maintains a constant
MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2895
Fig. 15. Measured dynamic response of the load voltage with differentrobust controllers (different source voltages: CV1 = 28 V, CV2 = 24 V, andCV3 = 20 V).
Fig. 16. Measured dynamic response of the load voltage with different robustcontrollers (R = 30 Ω).
load voltage while it deviates from tracking the reference forvariations exceeding the robustness range.
Although all the digital controllers Gc1(z−1)−Gc4(z−1),Gcr1(z−1), and Gcr3(z−1) regulate the load voltage, the robustcontroller Gcr2(z−1) designed in this paper responds quicklyenough and reaches the reference load voltage in a shorter time.The measured performance of the robust controller Gcr2(z−1)for extreme cases is also shown in Figs. 15–17, where thedynamic response settling time and overshoot quantities arewithin the specified limits. Furthermore, the robust controllerexhibits a smaller response time during start-up and a shortersettling time against step source and load perturbations, indi-
Fig. 17. Measured starting response of the load voltage with different sourcevoltages (R = 30 Ω; CV1 = 28 V; CV2 = 24 V; CV3 = 20 V).
Fig. 18. Measured robustness indicating the plots of load voltage and inductorcurrent against inductance variation (L : 260 → 320 μH).
Fig. 19. Measured load voltage robustness with different load resistances(V V1 = 40 Ω, V V2 = 30 Ω, and V V3 = 20 Ω).
cating better disturbance rejection capability. The design of adigital controller to ensure the required range of robustnessrange, together with a smaller response time, may not be
2896 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 7, JULY 2011
feasible. In order to accommodate inaccuracies due to modelingerrors, the robustness range must be limited, or the responsetime must be moderate in order to allow wider parametervariation.
The experimental measurements are in close agreement withthose obtained in the theoretical studies and simulations. Slightdiscrepancies between the simulation and experimentally mea-sured results are attributed to the following factors: 1) Thesupply voltage step variations created in the laboratory envi-ronment may not be exactly those created in the simulations;2) the dc supply source may not be as stiff as assumed in thesimulations; 3) difficulty in including actual nonidealities of theexperimental system in the simulation environment; 4) a slightmismatch of the mathematical models may cause differencesbetween the simulation and experimental dynamic responses;5) analytically obtained dynamic responses also partly gov-erned by the type of simulation engine used, etc.
V. CONCLUSION
An RPIDC for an HSBC has been designed. Discrete-timemodels were formulated through system identification tools andthen used in the design of the digital controller. A PPT, togetherwith SFS, has been applied to establish design guidelines fordigital controller design. By choosing the desired CHP poles,controllers were designed, and then, to ensure a robust sta-bility input, output and noise determining sensitivity functionvariations, over a predetermined range of frequencies, havebeen obtained. For a predefined range of parameter uncertainty,if all the sensitivity functions are within allowable templates,then the corresponding controllers are classified as robust con-trollers. The sensitivity-function-based robustness that has beendeveloped has been verified by simulation and experimentalmeasurement. These investigations reveal that CHP complexconjugate pole damping has a substantial effect on the achiev-able range of robustness, speed of response, and overshoot. Lessdamping results in faster regulation at the expense of increasedovershoot and reduced robustness range, and vice versa. Hence,a tradeoff between the damping and placement of complexconjugate poles would be a better choice, and the dampingvalue depends on the range of the expected uncertainty in agiven CLC system and on the speed of the response requiredby the application.
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MUMMADI: DESIGN OF ROBUST DIGITAL PID CONTROLLER FOR H-BRIDGE SOFT-SWITCHING BOOST CONVERTER 2897
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Veerachary Mummadi was born in Survail, India,in 1968. He received the B.Tech. degree from theJawaharlal Nehru Technological University (JNTU)College of Engineering-Anantapur, Anantapur,India, in 1992, the M.Tech. degree from theRegional Engineering College, Warangal, India, in1994, and the Dr. Eng. degree from the Universityof the Ryukyus, Okinawa, Japan, in 2002.
From 1994 to 1999, he was an Assistant Pro-fessor with the Department of Electrical Engineer-ing, JNTU-Anantapur. From October 1999 to March
2002, he was a Research Scholar with the Department of Electrical and Elec-tronics Engineering, University of the Ryukyus. Since July 2002, he has beenwith the Department of Electrical Engineering, Indian Institute of TechnologyDelhi, New Delhi, India, where he is currently an Associate Professor. Hisresearch interests include power electronics and applications, the modeling andsimulation of large power electronic systems, the design of power supplies forspacecraft systems, control theory application to power electronic systems, andintelligent solutions for power supplies.
Dr. Mummadi is an Editorial Member of The Institution of Engineeringand Technology (IET) Proceedings on Power Electronics, IET, U.K., andthe Journal of Power Electronics. He served as one of the Guest Editors ofthe IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS for two specialsessions on “Photovoltaic Power Processing Systems” and “Efficient and Re-liable Photovoltaic Systems.” He is currently an Associate Editor of the IEEETRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS and the IEEETRANSACTIONS ON INDUSTRIAL ELECTRONICS. He was the recipient of theIEEE Industrial Electronics Society Travel Grant Award for the year 2001, theBest Paper Award at the International Conference on Electrical Engineering2000 held in Kitakyushu, Japan, and the Best Researcher Award for the year2002 from the President of the University of the Ryukyus. He is listed in theWho’s Who in Science and Engineering, 2003.
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