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1Oct 2, 2003
Design Optimization of Mixed Time/Event-Triggered Distributed
Embedded Systems
Traian Pop, Petru Eles, Zebo PengEmbedded Systems Laboratory
Computer and Information Science Dept.Linköpings universitet, Sweden
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
2Oct 2, 2003
Introduction
Node 1 Node 2 Node 3
Hard real-time
constraints
(e.g. X-by-wire)
...
...
Factory Systems
NoCs
Automotive Electronics
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
3Oct 2, 2003
Introduction (cont’d)
Node 1 Node 2 Node 3
CA
N
TTP
Time-
Triggered
(TT)
Scheduling
Event-
Triggered
(ET)
Scheduling
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
4Oct 2, 2003
Introduction (cont’d)
Node 1 Node 2 Node 3
Time-
Triggered
Functionality
Event-
Triggered
Functionality
Static (ST) communicatio
n
ST/DYN Bus access cycleDynamic (DYN) communication
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
5Oct 2, 2003
Our Contribution
Design of distributed hard real-time embedded
systems
Mixed ET and TT task sets
Universal Communication Model: representation of
mixed ST/DYN communication protocol over the bus
Our focus:
Scheduling and timing analysis for such systems
[CODES’02]
Specific design problems
Design optimization heuristic
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
6Oct 2, 2003
Outline
Introduction
System Model
Scheduling and Schedulability Analysis
Specific Design Problems and Design Optimization
Heuristic
Conclusions
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
7Oct 2, 2003
static phase static phase dynamic phase
dynamic phase
Hardware Architecture
ST/DYN bus
Node 1 Node 2 Node 3CPU
I/O
ROM
communicationcontroller
RAM
slot 1 slot 2 slot 3 slot 1 slot 2 slot 3
TbusTbus
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
8Oct 2, 2003
Application Model
Task graphs
Domains for tasks: either TT or ET
Domains for messages: either ST or DYN
Task attributes: Processor, Worst-Case Execution
Time(Ci), Period, Deadline, Priority
Message attributes: Sender, Worst-Case
Transmission Time, Period, Deadline, Priority
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
9Oct 2, 2003
Software Architecture
Real-time kernel which supports both ET and TT
activities
Static cyclic scheduling for TT activities
Fixed-priority scheduling for ET activities
Schedule Table
Prioritized Ready List
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
10Oct 2, 2003
Introduction
System Model
Scheduling and Schedulability Analysis
Specific Design Problems and Design Optimization
Heuristic
Conclusions
Outline
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
11Oct 2, 2003
Holistic Scheduling
Schedulabilityanalysis
Static scheduling
Ri Di ?
Valid static schedule
OUTPUTS
TT tasks ST messages
ET tasks DYN messages
INPUTS
[CODES’2002]
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
12Oct 2, 2003
Outline
Introduction
System Model
Scheduling and Schedulability Analysis
Specific Design Problems and Design Optimization
Heuristic
Conclusions
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
13Oct 2, 2003
Specific Design Problems
Partitioning of functionality into TT/ET domainsOptimization of the ST/DYN bus access cycle
ST/DYN Bus access cycle
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
14Oct 2, 2003
Mapping
Partitioning of the system functionality:
Tasks: TT or ET ?
Messages: ST or DYN ?
Partitioning and Mapping
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
15Oct 2, 2003
Partitioning of Functionality
Node1
Node2
Node1 Node2
Node1
Node2
D2 D3
Node1
Node2
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
16Oct 2, 2003
Optimization of Bus Access Cycle
Determining the optimal structure of the bus
access cycle
Number, length and order of the ST/DYN phases
Static phase 1
Static phase 2
Static phase 3
Dynamic phase 2
Dynamic phase 1
Bus access cycle
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
17Oct 2, 2003
Slot1 Slot1 Slot2Slot2DYN DYN DYN DYN
Node1
Node2
Bus
m
Bus cycle Bus cycle
Optimization of Bus Access Cycle
Slot1Slot1 Slot2Slot2 DYNDYNDYN DYN
Node1
Node2
Bus
m
Bus cycleBus cycle
Slot1 Slot1 Slot2Slot2DYN DYN DYN DYN
Node1
Node2
Bus
m
Bus cycle Bus cycle
Slot1 Slot1Slot2Slot2 DYN DYN
Node1
Node2
Bus
m
Bus cycle Bus cycle
Slot1Slot1 Slot2Slot2 DYNDYNDYN DYN
Node1
Node2
Bus
m
Bus cycleBus cycle
D2
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
18Oct 2, 2003
Problem Definition
Input: Specification of a TT/ET Distributed Embedded
System
Some tasks are not mapped
Some task graphs are not assigned to any of TT/ET
domains Output: System configuration
TT/ET partitioning
Structure of the ST/DYN Bus Cycle
Mapping of functionality on the nodes
Timing constraints of the application are satisfied
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
19Oct 2, 2003
Optimization Heuristic
Step 0:Straightforward configuration
Step 1:Modify Initial Configuration
unschedulableTT partition
Step 3: Bus Access Optimization
unschedulable ET partition
Step 2: Mapping and Partitioning
unschedulable ET partition
Greedy assignmentof tasks and messages tonodes and TT/ET domains
Exploration of variousstructures of the busaccess cycle
Schedulablesystem
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
20Oct 2, 2003
0102030405060708090
100
60 75 90 120
Tasks
Nu
mb
er o
f so
luti
on
s %
Step 3
Step 2
Step 1
Step 0
Schedulable Applications
6 nodes
40 applications / set
60% processor utilisation
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
21Oct 2, 2003
0
10
2030
40
50
60
7080
90
100
CompleteHeuristic
No Remapping NoRepartitioning
Nu
mb
er
of
sc
he
du
lab
le a
pp
lica
tio
ns
%
Step 3
Step 2
Step 1
Step 0
Schedulable Applications
60-100 tasks mapped on 4-6 nodes
12-20 task graphs
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
22Oct 2, 2003
Real-Life Example
Node 1 Node 2 Node 3 Node 4 Node 5
CC: 42 tasks, 11 task-graphs- 1 TT task-graph- 10 unpartitioned task-graphs- 10 unmapped tasks
ABS: 35 ET tasks, already mapped
Schedulable solution:2 ET and 8 TT task-graphs
Design Optimization of Mixed Time/Event-Triggered Distributed Embedded SystemsTraian Pop, Petru Eles, Zebo Peng
23Oct 2, 2003
Conclusions
Distributed embedded systems with mixed TT/ET tasks sets
ST/DYN communication protocols
Specific design issues
TT/ET partitioning
Optimization of the ST/DYN Bus Cycle
Optimization Heuristic + mapping of functionality on the nodes
+ timing constraints are satisfied