Design with MicroprocessorsLecture 10

The 8086 Microprocessor. I/O and interrupts

Year 3 CS

Academic year 2018/2019

1st Semester

Lecturer: Radu Dănescu

Bloc diagrams: 8088 and 8086

80888086

Two stage pipeline: EU (execution unit) and BIU (Bus Interface Unit),

decoupled by a FIFO (4/6 bytes)

Registers of 8086

General purpose registers (GPR)

Pointer registers

Segment registers

The status register (Flags)

C (carry) – holds the carry bit after arithmetic or shift instructions

P (parity) – 0 for odd and 1 for even (count of number of ones) – obsolete

A (auxiliary carry) – holds the carry between bits 3 and 4 of the result (DAA/ DAS – BCD

addition/subtraction)

Z (zero) – 1 if the result of an arithmetic/logic instruction is 0

S (sign) – sign of the result of an arithmetic/logic instruction ( S=1 (MSB) – negative)

I (interrupt) – if 1 the interrupt system (INTR input) is enabled (STI/CLI)

D (direction) – increment (1) or decrement (0) the address (DI/SI) in string instruction

O (overflow) – overflow of the result capacity for signed addition or subtraction

T (trap) – T=1 instruction flow is interrupted on conditions from debug/control reg. (debug)

Memory address space• Total addressable memory: 1 MB, using 20 address lines

• Byte level addressing

ISR addresses, from 00000h

4 bytes / interrupt type,

256 interrupt types possible

Jump address on RESET

CS: FFFFh, IP: 0000h

Available

Memory addressing modes• Effective Address = Base + Index + Constant offset

• There are multiple combinations, each element of the effective address is optional

• Physical address: Segment x 16 + Effective address

• 16 bits of Effective Address, 20 bits of Physical Address

Examples

mov al, [bx]

mov al, [si]

mov al, [bp][di]

mov al, [bx][di]200

mov al, ss: [di]470

mov al, [bp+si+100]

8086 generic instruction format

I/O Addressing• Separate I/O address space, ranging from 0000 – FFFF (64 KBytes)

• Two types of instructions – long and short. The long instruction allows to specify the port as a

constant between 0 and 255

• The source or destination register for the I/O operation is always AX (AL)

• The port is specified by a constant, or by DX

Examples

8086 – pin diagramAD15:0 – address and data, multiplexed

on the same pins

A19:A16 – Higher bits of the address

BHE – Byte high enable

INTR – Interrupt request

MN/MX – Selection between minimum

and maximum modes

WR, RD – write, read commands

DT/R – data transmit/receive

DEN – Data enable

ALE – Address latch enable

IO/M – Specifies whether the address

lines refer to the memory space or to the

I/O space

#BHE A0 Explanation

0 0 16 bits addressing (aligned)

0 1 High byte, odd address

1 0 Low byte, even address

1 1 Not allowed

8086/ 8088 comparison

Memory organization

Memory Depth

Word width

8086 (minimum mode) system

Bus forming in 8086 minimum mode

Transceiver

Latch

8086 (maximum mode) system

The control bus

signals are

generated by 8288

Data and address

buses are similar

to the minimum

mode buses

The processor

generates a state

using S2:..S0, used as

command for 8288

Bus forming in 8086 maximum mode

#S2 #S1 #S0 Explanation

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Instruction Fetch

1 0 1 Read from memory

1 1 0 Write to memory

1 1 1 Passive (No bus operation)

The 8288 bus controller

Simplified time diagrams – read and write

Detailed time diagrams – read and write

Read Write

I/O Read and Write – Time Diagrams

In minimum mode, the M/IO signal indicates the used address space (memory

or I/O), the rest of the signals being identical

Interfacing I/O devices

From the combination of the RD, WR, and M/IO signals, explicit signals for

IOR, IOW, MEMW, MEMR can be generated, similar to the ones of the

maximum mode – we can present the same modes in a unified manner

Output device + Input device,

Same I/O address (Port number)

Short pulse output !

A device is activated when:

- The address sent by 8086 is recognized

as the own address – Decoding !

- The I/O command fits the type of the

device – Input or Output

- Two devices can have the same address

if they are of different type

The output problem – data persistenceThe LEDs will be lit only for the

duration of a bus cycle – invisible !

Solution – use a register for holding

the output data after the bus cycle is

complete.

Latch or Flip-Flop.

The input problem – bus decoupling- The data bus is shared (Multiple input

devices share the same lines)

- A device must write data on the bus

only when asked by I/O Read (in)

instructions !

- Use of 3-state buffers

- Data must be stable when the read

command arrives.

Decoding I/O addresses

Decoding using discrete logic circuits

NAND, AND, OR, NOR

The address EFXXh = 11101111XXXXXXXX

Decoding by comparator - Allows selectable addresses

Decoding I/O addresses

Use of a decoder

- G1, G2A, G2B – validation signals (G1 must be 1, G2A and G2B must be zero)

- A, B, C – selection signals for a line

- Allows selecting between 8 I/O devices

For this example:

A7:A5 must be ‘1’

A3 must be ‘0’, A4 must be ‘1’ Address range: F0:F7

Decoding I/O addresses

Data transfer modes

By program Using interrupts

By DMA

Interrupts – Sources of interrupts

– Triggered by Software – the instruction INT n

– Triggered by Hardware – Exceptions – error signaling (divide by 0, trap)

- External – from I/O devices, from memory

Interrupts can be

- Maskable (Can be disabled by the IF flag)

- Non-maskable Interrupt priority

Time requirements

Interrupts –ASM instructions

Interrupt vectors

The Interrupt Vector Table is in

RAM – the jump addresses for

each interrupt type can be

configured by program

Handling interrupt requests

- Masking – the IF bit in the status (flags) register

- INTR - level triggered, internally synchronized on CLK ↑

- INTR High duration – must cover the clock period before the finishing of the

current instruction execution

INTA cycle for external maskable interrupts

The vector type is read by 8086 at the end of the second INTA pulse

An interrupt generating device must be able to :

- Write the interrupt type on the data bus (the index in the interrupt vector table)

- De-activate INTR when the INTA confirmation is received

Interrupts – connecting simple devices

- The interrupt type 30h is generated when the Interrupt Request line is active

- INTA will allow the interrupt type to be written on the bus, and will clear the

flip-flop that holds INTR

Interrupts – connecting simple devices

- Generating multiple interrupt types, depending on the interrupt source

Handling multiple interrupt requests

Polling – when the interrupt request arrives, the processor checks every

possible source, and the interrupt source answers. The order of polling is the

order of interrupt priority.

Daisy Chain – hardware polling method. Limited by the length of the chain,

which adds propagation delays.

The 8259A interrupt controller

8 interrupt request lines, with

programmable priority.

Can be cascaded – 8 slaves, 64

total interrupt requests

The 8259A interrupt controller

Steps of operation when handling an interrupt request

1. PIC (8259) informs the processor about the interrupt request, by activating

(setting to 1) the INTR processor pin.

2. The processor finishes executing the current instruction.

3. The processor sends the Acknowledgment signal (INTA) to PIC

4. PIC puts on the bus the interrupt number (type) for the requested interrupt.

5. The processor uses this number to locate the address of the Interrupt Service

Routine (ISR).

6. The processor saves on the stack the flags, and the CS and IP registers (in this

order).

7. The IF flag is set to zero.

8. The registers CS:IP are loaded with the ISR address, and the interrupt service

routine is executed.

The 8259A interrupt controller