EURASIP Journal on Applied Signal Processing 2004:10, 1604–1615 c 2004 Hindawi Publishing Corporation Design and Implementation of MC-CDMA Systems for Future Wireless Networks S´ ebastien Le Nours CNRS UMR IETR (Institut en Electronique et T´ el´ ecommunications de Rennes), INSA Rennes, 20 avenue des Buttes de Co¨ esmes, 35043 Rennes Cedex, France Email: [email protected]Fabienne Nouvel CNRS UMR IETR (Institut en Electronique et T´ el´ ecommunications de Rennes), INSA Rennes, 20 avenue des Buttes de Co¨ esmes, 35043 Rennes Cedex, France Email: [email protected]Jean-Franc ¸oisH´ elard CNRS UMR IETR (Institut en Electronique et T´ el´ ecommunications de Rennes), INSA Rennes, 20 avenue des Buttes de Co¨ esmes, 35043 Rennes Cedex, France Email: [email protected]Received 28 February 2003; Revised 8 October 2003 The emerging need for high data rate wireless services has raised considerable interest in MC-CDMA systems. In this work, we describe an MC-CDMA system design process for indoor propagation scenarios. The system specifications and simulations are firstly given, and then implementation aspects on a mixed, multi-DSP and FPGA architecture are presented. In order to reduce development cycle, we propose the use of efficient design methodologies to improve development steps such as complexity evaluation, system distribution according to the architecture, and hardware-software code generation. Implementation results of the considered MC-CDMA system are then given. Keywords and phrases: MC-CDMA, multi-DSP-FPGA architecture, codesign methodology, hardware-software distribution. 1. INTRODUCTION The European third-generation (3G) terrestrial mobile sys- tem under deployment aims at offering a large variety of cir- cuit and packet services and greater capacity compared to second-generation (2G) systems. The evolution from 2G to 3G corresponds to adapting a new air interface but most of all to a change of focus from voice to multimedia. Fourth gener- ation (4G), as for it, will be defined by the ability to integrate heterogeneous networks, especially radio mobile networks and wireless local area networks (WLAN), that is, to offer ac- cess to all services, all the time and everywhere [1]. Besides, the rapid growth of Internet services and the increasing inter- est in portable computing devices are likely to create a strong demand for high-speed wireless data services. Presumably, it is anticipated that systems with a maximum information bit rate of more than 2–20 Mbps in a vehicular environment and possibly 50–100 Mbps in indoor to pedestrian environments will be needed, using a 50–100 MHz bandwidth. Key issues to fully meet these evolution perspectives are based upon the most efficient use of scarce spectrum resources, and upon the advent of reconfigurable radio conceivable due to the emer- gence of software defined radio (SDR) equipments [2]. On the one hand, the multicarrier code-division multiple-access (MC-CDMA) modulation scheme has al- ready proven to be a strong candidate as an access tech- nique for broadband cellular systems [3]. Different concepts based on the combination of multicarrier (MC) modula- tion with direct-sequence CDMA (DS-CDMA) have been introduced in 1993 [4, 5, 6, 7]. Since that time, owing to its high spectral efficiency and high flexibility, MC-CDMA scheme has become a promising access technique for 4G air interface. MC-CDMA benefits are for example highlighted in [8]; it is demonstrated that, with respect to universal mo- bile telecommunications system (UMTS) and International Mobile Telecommunications 2000 (IMT2000) requirements based on a 5 MHz bandwidth channel, a net bit rate up to 4 Mbps with a 1/ 2 rate channel code and even 6 Mbps with a3/ 4 rate code could be assigned to a single user for in- door but also macrocellular environments with a vehicular
Design and Implementation of MC-CDMASystems for FutureWireless Networks
Sebastien Le NoursCNRS UMR IETR (Institut en Electronique et Telecommunications de Rennes), INSA Rennes,20 avenue des Buttes de Coesmes, 35043 Rennes Cedex, FranceEmail: [email protected]
Fabienne NouvelCNRS UMR IETR (Institut en Electronique et Telecommunications de Rennes), INSA Rennes,20 avenue des Buttes de Coesmes, 35043 Rennes Cedex, FranceEmail: [email protected]
Jean-Francois HelardCNRS UMR IETR (Institut en Electronique et Telecommunications de Rennes), INSA Rennes,20 avenue des Buttes de Coesmes, 35043 Rennes Cedex, FranceEmail: [email protected]
Received 28 February 2003; Revised 8 October 2003
The emerging need for high data rate wireless services has raised considerable interest in MC-CDMA systems. In this work,we describe an MC-CDMA system design process for indoor propagation scenarios. The system specifications and simulationsare firstly given, and then implementation aspects on a mixed, multi-DSP and FPGA architecture are presented. In order toreduce development cycle, we propose the use of efficient design methodologies to improve development steps such as complexityevaluation, system distribution according to the architecture, and hardware-software code generation. Implementation results ofthe considered MC-CDMA system are then given.
Keywords and phrases:MC-CDMA, multi-DSP-FPGA architecture, codesign methodology, hardware-software distribution.
1. INTRODUCTION
The European third-generation (3G) terrestrial mobile sys-tem under deployment aims at offering a large variety of cir-cuit and packet services and greater capacity compared tosecond-generation (2G) systems. The evolution from 2G to3G corresponds to adapting a new air interface butmost of allto a change of focus from voice to multimedia. Fourth gener-ation (4G), as for it, will be defined by the ability to integrateheterogeneous networks, especially radio mobile networksand wireless local area networks (WLAN), that is, to offer ac-cess to all services, all the time and everywhere [1]. Besides,the rapid growth of Internet services and the increasing inter-est in portable computing devices are likely to create a strongdemand for high-speed wireless data services. Presumably, itis anticipated that systems with a maximum information bitrate of more than 2–20Mbps in a vehicular environment andpossibly 50–100Mbps in indoor to pedestrian environmentswill be needed, using a 50–100MHz bandwidth. Key issuesto fully meet these evolution perspectives are based upon the
most efficient use of scarce spectrum resources, and upon theadvent of reconfigurable radio conceivable due to the emer-gence of software defined radio (SDR) equipments [2].
On the one hand, the multicarrier code-divisionmultiple-access (MC-CDMA) modulation scheme has al-ready proven to be a strong candidate as an access tech-nique for broadband cellular systems [3]. Different conceptsbased on the combination of multicarrier (MC) modula-tion with direct-sequence CDMA (DS-CDMA) have beenintroduced in 1993 [4, 5, 6, 7]. Since that time, owing toits high spectral efficiency and high flexibility, MC-CDMAscheme has become a promising access technique for 4G airinterface. MC-CDMA benefits are for example highlightedin [8]; it is demonstrated that, with respect to universal mo-bile telecommunications system (UMTS) and InternationalMobile Telecommunications 2000 (IMT2000) requirementsbased on a 5MHz bandwidth channel, a net bit rate up to4Mbps with a 1/2 rate channel code and even 6Mbps witha 3/4 rate code could be assigned to a single user for in-door but also macrocellular environments with a vehicular
Future Design and Implementation of MC-CDMA Systems 1605
mobility. Thus, MC-CDMA is nowadays considered as a verypromising technique, specifically for the downlink of the fu-ture cellular mobile radio systems. Then, MC-CDMA is forexample studied within the European IST project MATRICE(MC-CDMA transmission techniques for integrated broad-band cellular Systems)1. This work has been partly carriedout within this project MATRICE which aims at defining anew air interface for 4G systems.
On the other hand, the advent of such wireless commu-nication systems also depends on the use of optimized em-bedded architectures and consequently of advanced designmethods. Due to increased complexity applications, achiev-ing high performances solutions is no more guaranteed byfully software (SW) implementation, using general-purposeprocessors (GPP) or digital signal processors (DSP), or fullyhardware (HW) implementation on application specific in-tegrated circuits (ASIC). Thus, heterogeneous architecturesbased on the combined use of reconfigurable HW compo-nents as field programmable gate array (FPGA) and repro-grammable SW processors such as DSP represent attrac-tive and appropriate solutions for complex radiocommuni-cation systems implementation and rapid prototyping. As aresult, concurrent design, or codesign, methods become con-venient to favour reduced development cycle for SDR systemdesign [9]. These methods notably make possible efficientdesign spaces exploration to achieve an optimized match-ing between developed algorithms and targeted architectures[10].
In this context, an implementation of an airport data linkbased on MC communications was proposed in [11]. Be-sides, special focus on equalisation receiver design [12] orsystem consumption [13] can also be found. In a general way,this work aims at investigating MC-CDMA system design inthe 4G context, from system definition to implementationunder real-time constraints. This paper is dedicated to thestudy of MC-CDMA for indoor propagation scenarios. Thisfirst step is necessary to guarantee the feasibility of the imple-mentation under real-time constraints. According to channelproperties, different configurations for a MC-CDMA down-link air interface are proposed and simulated.
Implementation results on a heterogeneous platformcombining DSP and FPGA are also presented. Our imple-mentation approach is based on specific codesign methodsin order to propose an efficient design flow integrating sys-tem modelisation, algorithms complexity evaluation, archi-tectural exploration, automatic code generation, and imple-mentation on the testbed platform.
This paper is organized as follows. In Section 2, first ofall, the main features of the studied MC-CDMA system arepresented. Furthermore, used heterogeneous platform is de-scribed, and the benefits of our codesign approach will behighlighted. In Section 3, system parameters are presentedand simulation results are given. Section 4 deals with com-plexity analysis of studied MC-CDMA functions, whereasSection 5 presents implementation aspects of our codesign
1www.ist-matrice.org
Simulationand
validationaccording to
systemconstraints
Implementation onheterogeneous target
HWsynthesis
HW-SWinterfacesynthesis
SWsynthesis
Complexity analysis,distribution, and
performances prediction
Architecturedefinition
System modelisation
System specifications
Figure 1: Generic codesign flow.
approach on the mixed architecture. Finally, Section 6 sum-marizes the results and conclusions are given.
2. MC-CDMA SYSTEMDESIGN
codesign flow enables a top-down design from a systemmod-elisation step to implementation on a prototyping board un-der real-time constraints, as illustrated in Figure 1. The firststep aims at establishing MC-CDMA system specificationsaccording to channel properties. Once validated, the systemmodelisation will then be used as an entry point in the ar-chitectural design. This important step deals with HW-SWdistribution according to the specified functions complexityand the available architecture. Accurate modelisation is re-quired to efficiently investigate various implementation solu-tions according to real-time constraints, such as throughputand consumption. Then, automatic synthesis of the adoptedsolution, both for the SW part, the HW part, and the inter-faces, leads to a reduced development time and reliable solu-tion.
2.1. MC-CDMA systemmodelisation
The MC-CDMA air interface allows high-capacity networksand robustness in the case of frequency-selective channels,taking benefits from CDMA capability offered by the spreadspectrum technique, and MC modulation as orthogonalfrequency division multiplex (OFDM). A possible genericdownlink transmission scheme is depicted in Figure 2.
Each user data can be simultaneously processed at thespreading step before MC modulation. In the following,due to their good properties for the downlink [14], Walsh-Hadamard (WH) spreading sequences will be considered.The presented MC-CDMA configuration is based on thetransmission of multiple data per MC-CDMA symbol foreach user. Data dij(n) denotes the ith, 1 ≤ i ≤ Nb, data trans-mitted by user j, 1 ≤ j ≤ Nu, in the nth MC-CDMA symbol.
1606 EURASIP Journal on Applied Signal Processing
Channelestimation
· · ·
...
Numerical andBB conversions
...OFDM
demodulation...
Frequency
deinterleaving
...
...
...
...
Equalisation...Despreading
...dNbj
d1j
Receiver user j
Propagationchannel model
IF and analogRF conversions
...OFDM
modulation...
Frequency
interleaving...
...Spreading
...
Spreading
...
...
dNbNu
dNb1
d1Nu
d11
{
{
Last set oftransmitted symbolsfor each active user
First set oftransmitted symbolsfor each active user
MC-CDMA transmitter
Figure 2: Studied MC-CDMA transmitter and receiver.
The maximum number of available users, which is also equalto the length of theWH spreading sequences, will be denotedNu. The total number of subcarriers is Nc = Nz +Ncu, whereNz and Ncu are the number of unused and used subcarriers,respectively. Therefore, the number of data transmitted byeach user in one MC-CDMA symbol is Nb = Ncu/Nu. Fre-quency interleaving is performed in order to fully exploit thefrequency diversity offered by OFDMmodulation.
At the receiver part, despreading is done according tothe specific user sequence after equalisation in the frequencydomain. The system synchronisation and intermediate fre-quency (IF) and baseband (BB) conversions problems arebeyond the scope of this paper and will not be addressed.Among various equalisation techniques, we especially fo-cus on single-user detection techniques. Channel estimationfunction can efficiently be performed by using pilot subcar-riers insertion. The arrangement of these pilots must guar-antee an optimum sampling of the channel transfer functionin time and in frequency, depending on the bandwidth co-herence and on the time coherence of the channel [15].
Obviously, MC-CDMA system offers high flexibility inresources (spectral efficiency, number of users) allocationwhich consequently induces large design spaces. As a result,high-level design methods are convenient in order to dealwith such complexity and for efficient implementation.
2.2. Description of the proposed codesign approach
Most of radiocommunication systems designed on heteroge-neous platforms are faced by the complexity of mixing SWand HW design flows. Functions distribution according to
HW or SWmostly depends on designers experience. Besides,the matching between algorithm and architecture and es-timation performances for multicomponent architecture israrely addressed.
Thus, as illustrated in similar works [16, 17], a high-level specification is required to improve HW-SW distribu-tion and combined simulation. Our purpose is to propose anefficient top-down design flow, making possible efficient ar-chitectural choices taking into account specified algorithmsand heterogeneous target properties. Besides, in order tofavour reusability and to reduce design process duration, amultisource integration, as well as HW description language(HDL) sources such as C codes, is required. As illustrated inFigure 3, our design process is based on the concurrent use oftwo codesign methods and their associated tools: the code-sign methodology for embedded systems (CoMES) method-ology [18], and the algorithm architecture adequation [19](AAA) methodology; “Adequation” is a French word mean-ing an efficient matching. The first method is used for systemmodelisation and simulation, algorithms complexity evalua-tion, and architectural design, whereas the second one is usedfor functions distribution and code generation.
CoMES modelisation combines a graph model withC-coded algorithms, allowing complete system simulationwithout any assumption on architecture. Functions activ-ity and complexity can then be evaluated using a profilingstep. In a second part, the target architecture can be definedas a set of interconnected HW and SW processors. Finally,functions distribution on the multicomponent architecturecan be studied according to system attributes such as time
Future Design and Implementation of MC-CDMA Systems 1607
System simulation witharchitecture limitationsand implementation
performances evaluations
System simulation withoutarchitectural assumptions
Complexity analysis,and implementation
performances prediction
Architecturalattributes
System modelisation
System specifications
Figure 3: Considered design flow.
IP interfaces
Processing units
Physical links
PCI bus
Slow-portinterface
Quick-portinterface
Periph
erals
C6701 CPU
C6701
Externalmemory banks
Software module
Slow-portinterface
Quick-portinterface
Slow-portinterface
Periph
erals
C6701 CPU
C6701
Externalmemory banks
Software module
Slow-portinterface
Quick-portinterface
Hardware functionsimplementation
Memorycontroller
Virtex
Hardwaremodule
Externalmemory banks
Figure 4: Heterogeneous architecture description.
execution on each component, data communication dura-tions, and intercomponent interfaces behaviour. At this step,we can obtain a fully validated and detailed performancesestimation of the mapped functions on the distributed ar-chitecture. The AAA methodology, as for it, is firstly usedfor functions automatic distribution, taking into account thedifferent complexity parameters given by the previous step.This feedback makes possible accurate system evaluation.Once an efficient matching between functions and architec-ture has been found, the AAA methodology allows for algo-rithms and inter-component communications code genera-tion, as well as for C generation and for VHDL generation.
The next part presents the used architecture for the MC-CDMA system implementation.
2.3. Testbed architecture description
Our prototyping platform is based on a peripheral compo-nent interconnect (PCI) Sundance Multiprocessor mother-board where two DSP-based modules and one FPGAmoduleare plugged. As illustrated in Figure 4, two different commu-nication formats are used: a 8-bit bidirectional format, de-noted by slow port, allowing 20Mbps transfer rate, and a16-bit bidirectional format, denoted by quick port, allowing200Mbps throughput.
1608 EURASIP Journal on Applied Signal Processing
Table 1: Propagation channel parameters.
Parameters Channel parametersMaximum delay τmax 390 nsDelay spread στ 50 nsMeasured 50% coherence bandwidth Bc 11MHzMeasured 50% time coherence Tc 15msTypical Doppler shift fD at 1m/s 17.33Hz
Each SW module uses the TMS320C6701 DSP fromTexas Instrument. This component is based on a very longinstruction word (VLIW) architecture making it possible tocompute 8 operations per cycle at a 167MHz frequency. TheFPGA is a XCV400 Virtex with 400Kgates, corresponding to2400 logic blocks. Memory blocks are also available in theFPGA. Dedicated components are used on the SW modulesto make possible data exchanges between the DSP periph-erals and the communication ports. Besides, HW intellec-tual property (IP) cores are provided to be inserted in theFPGA component to control the communication channels.The FPGA is configured using a bitstream sent by a DSP. Thedescribed codesign approach will be applied to this architec-ture for system implementation.
The next part presents MC-CDMA system parametersand simulation results according to the used channel model.
3. SYSTEMDEFINITION
For indoor propagation scenarios, we considered the BRAN-A channel as defined in [20], with a frequency carrier fc =5.2GHz. In our simulations, the propagation channel willconsist of 18 power loss paths with a flat Doppler spectrumon each path. In Table 1, the required channel parametersused to establish our simulation model for the propagationscenario are summed up.
This channel model has been implemented on the pro-totyping board presented in Section 2 in order to simulatethe studied MC-CDMA system. The system parameters arechosen according to the time and frequency coherence ofthe channel in order to reduce intersubcarrier interferences(ICI) and intersymbol interferences (ISI). Besides, investi-gated MC-CDMA configurations are designed to proposehigh throughput and high capacity solutions for indoor sce-narios. From the systemmodel illustrated in Figure 2, the of-fered net bit rate per user can be expressed as follows:
Du = nNcu
Nu(Tu + Tg
) = nNcu
Nu(Nc/Fs + Tg
) = nNb(Nc/Fs + Tg
) ,(1)
where
(i) n is the bits number per symbol according to the usedmodulation. In the following, QPSK modulation willbe considered (n = 2);
(ii) Ncu corresponds to the number of used subcarriers perMC-CDMA symbol;
(iii) Tu+Tg is the wholeMC-CDMA symbol duration, witha sampling frequency denoted by Fs. Tg is the guard in-
Table 2: Configurations parameters.
Parameters Configuration I Configuration IISampling frequency Fs 20MHz 50MHzNumber of total/usedsubcarriers (Nc/Ncu)
64/48 256/192
Symbol/guard intervalduration (Tu/Tg)
3.2 µs/0.8 µs 5.12 µs/0.8 µs
Subcarrier spacing (∆ f ) 321.5 kHz 195.3 kHzUsed bandwidth (W) 15.4MHz 37.5MHzNumber of users(Nu)—full-load system
4, 8, 16 16, 32, 64
Number of symbols peruser (Nb)
12, 6, 3 12, 6, 3
Net bit rate per user (Du) 6, 3, 1.5Mbps 4, 2, 1Mbps
terval duration. According to τmax value and in orderto avoid ISI, Tg will be taken equal to 0.8 microsec-onds.
The first proposed configuration, which parameters setis summed up in Table 2, is based on HIPERLAN Type 2specifications with a 20MHz sampling frequency. The ra-tios Og = Tu/(Tu + Tg) = 0.8 show a low spectral efficiencyloss due to guard interval insertion, which corresponds to apower efficiency loss equal to 0.97 dB.
In the second studied configuration, a 50MHz samplingfrequency is targeted to achieve a better tradeoff between bitrate and users capacity. In that case, Og = 0.86 leads to apower efficiency loss equal to 0.63 dB. Besides, in both cases,Doppler shift is very low compared to the subcarrier spacing.
An appropriate approach for channel estimation in high-speed packet transmission is the use of a dedicated pilot sym-bol periodically inserted in the transmission frame. Further-more, the very high ratio between the BRAN-A channel timecoherence and theMC-CDMA symbol duration induces veryslow channel evolution during the transmission of each sym-bol. Thus, the considered frame structure, illustrated in ageneral way in Figure 5, includes Np = 1 pilot symbol at thebeginning of each frame and Ns additional MC-CDMA datasymbols per frame.
Future Design and Implementation of MC-CDMA Systems 1609
Table 3: Frame structure parameters.
Parameters Configuration I Configuration IINumber of data symbolsper frame Ns
100/1000 100/500
Frame duration 400 µs/4ms 592 µs/3ms
Then, channel estimation is processed from the pilotsymbol received at the beginning of each frame. As a result,nonideal channel estimation parameters impact on the qual-ity of the transmission could be studied. Moreover, a con-stant power is allocated to pilots for all configurations. Sim-ulations were performed considering a 1m/s mobile speed.Table 3 gives the different simulated frame structures.
Besides, we investigated different detection techniques:maximum ratio combining (MRC), equal gain combining(EGC), orthogonality restoring combining (ORC), and sub-optimal minimum mean square error (MMSE) techniques[21]. This last one is done using a fixed signal-to-noiseparameter at 12 dB for the MMSE coefficients computa-tion. Figure 6 illustrates the BER performance of consid-ered single-user detectors for configuration I with Nu = 8,whereas Figure 7 represents performance for configurationII with Nu = 32, both in the full-load case.
The depicted curves obviously demonstrate efficiency ofMMSE-based detector compared to others techniques. Be-sides, the two detectors using linear channel equalisation,that is, ORC and MMSE detectors, are more sensitive to in-accurate channel estimation than diversity combining detec-tors such as EGC.
According to the presented configurations and the framestructure, a tradeoff between the power allocated to pilotsymbols and the performance degradation resulting fromchannel estimation errors should be found. A similar ap-proach as described in [22] could be used.
In the following parts, we present the MC-CDMA systemimplementation results and the different steps of our designmethodology used from system simulation to integration.
4. MODELISATION AND COMPLEXITYANALYSIS EVALUATION
4.1. Modelisation step
In our design approach and according to specifications givenSection 3, the CoMES methodology and its associated tool isused to firstly model the studied MC-CDMA system with-out any assumption about the architecture. The benefits ofthis approach is that the model will both be used for func-tional and architectural descriptions at an abstract level toease HW-SW distribution and to evaluate implementationperformances. The functional model is based on three com-plementary viewpoints [23]:
(i) the structural organisation viewpoint, which repre-sents data dependencies between functional elements,is firstly specified. At the functional level, data are ex-changed through ideal FIFO (first-in first-out) com-munication ports;
Figure 7: Performances results for configuration II, Nu = 32.
(ii) the behavioral viewpoint defines the set of operationsand their time order for each function. These two com-plementary specifications are graphically defined;
(iii) the algorithm viewpoint is finally specified in C/C++language and describes the set of instructions for eachoperation previously defined.
This description approach leads to an efficient de-sign with reduced errors propagation and to a fully ex-ecutable model for system verification and performancesevaluation. The estimation of system performances uses an
1610 EURASIP Journal on Applied Signal Processing
Data generationstructure
Behavioural description
Modulation Pilotsinsertion
∗Ns
Spreading
· · ·Behavioural model symbols:
Loop
Conditional wait
Data transmission
FIFO communication
Operation
(a)
Functional structures:
F FunctionI/O Data exchange
Functions execution state:
Data read or writeData exchangeFunction activityResource waiting
Functional attributes:
twr Write/read durationcwr Port capacitytf Function duration
...
F Interleaving
I/O Spreaded data
F Spreading
I/O Modulated data
F Modulator
I/O DataE
F Data generationtwr
cwrtf
Temporal execution
Functionsexecution
· · ·
· · ·
· · ·
· · ·· · ·
· · ·
(b)
Figure 8: Example of (a) the MC-CDMA system modelisation and (b) execution graph representation according to associated functionalattributes.
uninterpreted model, taking into account system attributessuch as operation durations, data exchange formats, FIFO ca-pacity, and so forth. The CoMES simulation model is thena true timed model and not only a functional model asused by most of commercial simulators. To illustrate systemattributes influence, Figure 8 shows an MC-CDMA systemmodelisation example and the associated execution graph atthe functional level. At this step, attributes can be set by de-fault and will be more accurately determined once the func-tions durations evaluation step is done.
Figure 9 illustrates CoMES tool system simulation ca-pabilities at the structural viewpoint and at the algorithmviewpoint. Moreover, generic parameters such as spreadinglength, number of users, or equalisation techniques can beset before simulation to obtain a flexible description and toease design space exploration.
Then, the MC-CDMA system could fully be modeledusing the CoMES tool. Besides, BER simulations were per-formed to validate system behaviour and used algorithms.This modelisation and functional validation is the first stepto achieve before function complexity analysis.
4.2. Complexity analysis evaluation
Complexity analysis step aims at defining each function com-plexity and at investigating implementation performancesaccording to the processor target kind. From system mod-elisation and specified algorithms, the CoMES tool allowsto evaluate functions activity and relative complexity thanksto a profiling step. Complexity comparison illustrated inFigure 10 indicates relative functions duration in system exe-cution. Channel model description complexity has not beenrepresented. This step makes it possible to improve functions
Future Design and Implementation of MC-CDMA Systems 1611
Data evolution
BER evolution
Average powerevolution
Figure 9: Example of system simulation applying the CoMES methodology and using the associated tool. On the left-hand side, the struc-tural simulation is based on an execution graph representation of functions activity, and on the right-hand side, algorithmic simulationcapabilities are presented.
Datageneration
QPSKmodulation
Spreading
Interleaving
MCmodulation
MCdemodulation
Equalisation
Deinterleaving
Despreading
QPSKdemodulation
Datareception
0%
5%
10%
15%
20%
25%
Execution
load
Figure 10: Function complexity evaluated for MC-CDMA config-uration using Nu = 32 and Nc = 256.
description and coding style still without any architecturalassumption.
Besides, each function activity can also be measured.Figure 11 illustrates the potential bottleneck represented byMCmodulation and demodulation compared to other func-tions. Then, this function still remains the most computingfunction in the considered MC-CDMA system.
This profiling step helps designers to identify criticalcomputing functions. In addition, for accurate architecturaldesign, we completed this complexity evaluation by con-sidering functions implementation performances accordingto processors targeted on our testbed platform [24]. Thus,whereas OFDM modulation is efficiently performed by an
Datageneration
QPSKmodulation
Spreading
Interleaving
MCmodulation
MCdemodulation
Equalisation
Deinterleaving
Despreading
QPSKdemodulation
Datareception
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Functionactivity
ActiveInactiveResource waiting
Figure 11: Functions activity in system execution evaluated forMC-CDMA configuration using Nu = 32 and Nc = 256.
inverse fast fourier transform (IFFT) algorithm, spreadingcan conveniently be implemented using a fast hadamardtransform (FHT).
Results given in Table 4 highlight benefits of FPGA im-plementation for most of the considered MC-CDMA func-tions. Computation times are measured according to C6701DSP clock, that is, 6 nanoseconds, and considering a 20nanoseconds cycle for the FPGA.
These values measured by implementation of each ele-mentary function on the testbed components are used inorder to find an efficient matching of MC-CDMA systemon the architecture and to evaluate performances achievablewith such a platform.
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Table 4: Function implementation results in microseconds.
Figure 12: Architecture model using CoMES methodology.
5. ARCHITECTURAL DESIGN ANDIMPLEMENTATION RESULTS
5.1. Architectural design: functions distribution studyand implementation efficiency evaluation
The purpose of the architectural design step is to define anefficient matching between the developed functions and theavailable architecture. The CoMES methodology allows tostudy the impact of functions distribution on the architec-ture. Architectural attributes such as SW component concur-rency, cycle duration for each component, SW overhead, andintercomponent communications durations complete the ar-chitecture description. We then modeled our platform as il-lustrated in Figure 12.
Nevertheless, despite the fact that the CoMES tool isstill used as the performances evaluation method, the AAAmethodology is followed to ease the distribution step. In-deed, this method and its associated tool SynDEx makes pos-sible a quasiautomatic distribution and scheduling of the de-fined system on the architecture, taking into account previ-ous evaluated functions durations and communication costs.Heuristic research is done to reduce system execution cycle.An example of function distribution and scheduling on thetarget architecture is illustrated in Figure 13.
Distribution
FPGACommunication
port 1 DSP 1 DSP 2
0 Data generation
Data to modulation
QPSK modulation
Spreading
Interleaving
MCmodulation
MCM to channel
Channel
Channel to MCM
MCdemodulation
Equalisation
Deinterleaving
Despreading
Demodulation
Demodulation todata reception
Data reception
Estimatedcomputation time
Schedule
Figure 13: Matching exploration result.
Thanks to this exploration step, different distributionperformances can easily be investigated, improving the dif-ficult task of HW-SW partition. The retained solution canthen be more accurately evaluated in the CoMES tool interms of pipelined behaviour. The concurrent simulation ofalgorithms allocated on the architecture makes it possible,on the one hand, to optimize the target architecture or, onthe other hand, to evaluate implementation performances atan abstract level. Then, achievable throughputs according tothe architecture configuration can then be evaluated. Table 5gives examples of simulation results following the CoMESmethodology. The ideal case denotes results obtained ne-glecting the communication ports influence. Others casestakes into account the communication kind. It illustratespoor efficiency of a fully SW implementation and the poten-tial bottleneck represented by intercomponent communica-tions.
Future Design and Implementation of MC-CDMA Systems 1613
Table 5: Implementation performances evaluation per user.
ParametersConfiguration I Configuration II
Nu = 8, Nc = 64 Nu = 32, Nc = 256
Fully SW implementationIdeal 181Kbps 36.4Kbps
Slow port 93.9Kbps 31.4Kbps
Quick port 167Kbps 35.8Kbps
HW-SW implementationIdeal 2.9Mbps 780Kbps
Slow port 444Kbps 125Kbps
Quick port 2.5Kbps 645Kbps
DSP 1 DSP 2 FPGA
17.07%
32.83%
50.10%
24.74%
29.76%
45.50%
78.99%
9.40%
11.60%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Data processing
Data communicationResources waiting
Figure 14: Component activity estimation for configuration II,Nu = 32, implemented on HW-SW architecture with quick ports.
Finally, the components activity can be measured for themost satisfactory solution, as illustrated in Figure 14 for theHW-SW implementation using quick ports.
Before implementation on the testbed platform, the laststep of the design process is the generation of the codes bothfor the SW and the HW parts.
As indicated in Figure 3, the AAAmethodology is used in or-der to generate codes at once for the SW, the HW part, andthe interfaces. The code generation process is described inFigure 15. After the distribution step, the tool SynDEx makesit possible to generate distributed executives for each com-ponent. This code takes into account intercomponent syn-chronisations and calls to functions. The code generationuses specific libraries built according to the component kind.The description of theses libraries will not be addressed inthe present paper, the reader should be refered to works de-scribed in [25].
The benefits of this approach are the generation of fullyvalidated codes reducing the verification step once imple-mentation on the testbed is done. The libraries used for SWgeneration already exist [26]. We built the needed library forHW generation [27]. This library uses the different devel-oped functions and the required interfaces. Themain synthe-
System validation onthe prototyping board
DSP 1 DSP 2 FPGA
SynDEx code generation
C and VHDLlibraries
(communications,functions)
Retained architectural solution
Figure 15: SynDEx code generation process.
sis results in terms of FPGA logic elements for each functionimplemented in the HW part are given in Table 6.
For example, in the Configuration I case, the automaticgeneration of the HW part of the transmitter retained so-lution, both for the required interface and the computationfunctions, corresponds to 1132 logic elements and 12 mem-ory blocks. Then, the HW synthesis results made it possibleto fully validate this design at a 50MHz frequency.
6. CONCLUSION
We have presented a codesign approach and associated toolsfor the MC-CDMA system rapid prototyping on a mixed ar-chitecture. This design goes from system specification andsimulation to HW-SW code generation and implementationon a testbed platform. The use of the CoMES model allowssystem simulations at the functional level as well as at the ar-chitectural one. Then, this top-down design approach makesit possible to accurately evaluate system implementation ef-ficiency, according to functions complexity and architectureproperties. Finally, the use of the AAA methodology com-pletes this HW-SW design by covering the distribution andcode generation steps.
The described design process, applied toMC-CDMA sys-tem, facilitates and reduces the development cycle. Then, weeasily investigate different implementation solutions accord-ing to the considered HW platform. Besides, the benefits ofthis approach fit into the SoftWare Radio (SWR) require-ments for efficient design methods.
From our application’s point of view, evaluation resultsand implementation show the ability to obtain high-speeddata rate using a mixed architecture. The demonstrated
1614 EURASIP Journal on Applied Signal Processing
Table 6: Synthesis results in terms of occupied logic elements for the HW implemented functions.
feasibility of the studied MC-CDMA system could lead to itsenhancement of the outdoor propagation characteristics.
ACKNOWLEDGMENT
This work has been partly carried out within the EuropeanUnion IST research project MATRICE (MC-CDMA trans-mission techniques for integrated broadband cellular sys-tems).
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Sebastien Le Nours received the Engineer-ing degree in electronics from the ISENSchool, Brest, France, in 2000. In 2003,he received the Ph.D. degree in electron-ics from the National Institute of AppliedSciences (INSA), Rennes, France. His re-search interests include design methodolo-gies for embedded systems and signal pro-cessing techniques, with particular empha-sis on multicarrier spread spectrum for mo-bile communications. He is currently working as an Assistant Pro-fessor at the UBS University and is associated to the LESTER labo-ratory, Lorient, France.
Fabienne Nouvel received the Engineeringdegree in electronics from the National In-stitute of Applied Sciences (INSA), Rennes,France, in 1985. She worked for 5 years innetworks domains. In 1994, she receivedthe Ph.D. degree in electronics from theINSA, Rennes. Since 1995, she has been anAssociate Professor at INSA in electronics.Her research topics include electronics, sig-nal processing techniques, especially spreadspectrum for embedded indoor and outdoor communications, anddesign methodologies for heterogeneous systems.
Jean-Francois Helard received his Dipl.-Ing. degree from the National Institute ofApplied Sciences (INSA), Rennes, France, in1981. From 1982 to 1997, he was a ResearchEngineer and thenHead of the channel cod-ing for digital broadcasting research groupat the CCETT (France Telecom ResearchCenter) in Rennes, where he worked succes-sively on digital audio broadcasting withinEUREKA 147 DAB (digital audio broad-casting) and terrestrial digital video broadcasting (DVB-T) withinthe framework of the European project dTTb. In 1992, he receivedthe Ph.D. degree in electronics and joined INSA in 1997, where he iscurrently a Professor and Head of the group Systems, Propagationand Radars of the Rennes Institute for Electronics and Telecom-munications (IETR) which depends on the French National Centrefor Scientific Research (CNRS). His present research interests lie insignal processing techniques for digital communications, as space-time and channel coding, multicarrier modulation, spread spec-trum, andmultiuser communications. He is the author or coauthorof more than 48 technical papers in international scientific journalsand conferences, and holds 11 European patents.
