Designing a FIR filter

8/12/2019 Designing a FIR filter

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EECS 217 Project 3

Spring 2013

Finite Impulse Response Filter

Anirban Samanta, 32924289, [email protected] Ravindran, 13206034, [email protected]


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Contents Page

1. Introduction 3

1.1 Understanding Filters 3

1.3 FIR filter 3

2. Our Design 5

3. Implementation 6

3.1 Kogge Stone Adder 6

3.2 Array Multiplier 8

3.3 2 Phase clock 10

3.4 MasterSlave edge-triggered D flip-flop 12

3.5 MasterSlave D flip-flop with Clear-Enable 13

3.6 Decoder 15

3.7 Pipeline 18

3.8 Complete FIR Filter 19

4. Testing the FIR filter 20

5. Conclusion 23

6. References 23


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1. IntroductionThe goal of this project is to use the Cadence VLSI Design Environment to implement a large scale

design. Large scale designs usually involve the use of several components - adders, multipliers, registers

and clocks. Here, we have designed and implemented a Finite Impulse Response Filter Chip. The general

design is similar to TRWs filter chip TDC1028. Several changes have been made with regards to the size

of adders and multipliers and the number of delay stages. A clean design is obtained by using standard

cells to implement the FIR filter. Schematics are created for all the standard cells and the FIR filter chip.

At each stage of the design, the individual blocks are tested for accuracy. Finally, hspiceS is used to

simulate the filter chip and test its correctness.

1.1. Understanding Filters

A filter is a device that removes unwanted components or features from a source signal. This is done by

removing some frequencies and not others in order to suppress interfering signals and reduce

background noise. Different filters work differently. Some offer complete elimination while others

suppress certain aspects of the signal (partial suppression). The drawback of filtering is the loss of

information associated with it.

Filters are classified into several types depending on their type of inputs signals, linearity, response etc.

FIR and IIR filters are filters that differ in their response to the impulse input. Finite Impulse Response or

FIR filters have a finite duration for the impulse input. In other words, the impulse response (or responseto any finite length input) is of finite duration, because it settles to zero in finite time. Infinite Impulse

Response (IIR) filters usually have internal feedback and this can cause them to respond indefinitely.Since this project only deals with FIR filters, their working and design is explained in detail in the

following sections.

1.2. The FIR Filter - Design and Working

Finite impulse response, or FIR, filters express each output sample as a weighted sum of the last N input

samples, where N is the order of the filter.

The basic design involves the amplification of a finite number of delay stages. The final output is the

finite sum of all the amplified delay stage outputs. This is shown in the figure below.


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Figure 1: FIR filter

Mathematically, the output of the FIR filter is a weighted sum of the current and a finite number of

previous input values. The operation is described by the following equation, which defines the output

sequence y[n] in terms of its input sequence x[n]:

Where: is the input signal, is the output signal, are the filter coefficients, also known as tap weights, that make up the impulse response, is the filter order; an th-order filter has terms on the right-hand side. The i

terms are commonly referred to as taps. They are tapped delay lines that usually provide the

delayed inputs to the multiplier.

If the FIR coefficients are symmetrical (often the case), then such a filter is linear phase, so it delays

signals of all frequencies equally.


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Figure 2: Discrete type FIR filter of order N

The major components in the FIR filters are the multipliers and adders. At each delay stage, the discrete

signal data is multiplied with the filter coefficients. The output of the multiplier is then added to the

output from the previous filter stage. The adder inputs for the first stage are usually all 0. Registers are

provided at every stage for storing both data and coefficient values. Registers are usually positive edge

triggered master-slave D latches. A synchronous master clock is provided that controls all the

components in the design. For each clock cycle of this clock, a coefficient is changed. To choose the

coefficient at each stage, a decoder is also available. The outputs of the FIR filters consists of the sum

output and the data output.The FIR filters have several advantages. They require no feedback. This implies that rounding errors are

not compounded by summed iterations. At each stage, the relative error is the same making the

implementation simpler. FIR filters are also bounded-input bounded-output (BIBO) stable since the

output is a sum of a finite number of finite multiples of the input values. The main disadvantage is that

they require significantly more processing, computation power and memory resources than IIR filters.

2. Our DesignThe FIR filter we designed for this project has the following features.

The design consists of 4 pipeline stages. Each stage is designed as a pipeline that includes a 16-bit Kogge-Stone adder, a 6x6 bit array multiplier and a 16-bit register.


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The data input and coefficient inputs are 6 bits each and they are stored in the data andcoefficient registers respectively. There is only 1 data register and 1 Coefficient register which is

connected to all the stages.

The adder we used is the 16 bit Kogge-Stone Adder designed as part of project 2. Input A (SI0-SI15) is the 16 bits from the previous filter stage. Input B is the 12 bits from the multiplier

outputs (B0-B11). The other 4 bits (B12- B15) are grounded. The multiplier used is the 6 bit X 6 bit array multiplier. The output of this multiplier is 12 bits and

they become the input for the KSA adder. Input A of the multiplier is the 6 data bits (DI0- DI5).

The other inputs (B) are the coefficient bits (CI0-CI5) from the coefficient registers. The selection of pipeline is determined by the 2 X 4 decoder. The 2 inputs to the decoder are the

address bits CA0 and CA1 and the 4 outputs are connected to the 4 pipelines.

The decoder outputs are used as a clock in the pipelines for functioning as an enable. The registers are all positive edge triggered master-slave D flipflops. Our design includes 16 bit,

6 bit and 2 bit registers. A clock signal is provided for the filter for use over all of the components. Since we are using the 0.18u technology for our design, the input voltages are 1.8V/0V.

The following section discusses the design and schematic for each of the components.

3. ImplementationImplementation of the FIR filter is done using cells. Cells help in achieving an easy and clean design. In

this section, each of the cells is discussed in detail and their schematic and test results are provided. The

basic gates used in this project are the AND, OR, NOT, NAND, NOR and XOR gates. Their schematic and

tests are not included since they have been used in earlier project reports.

3.1. The Kogge-Stone Adder (KSA)The KoggeStone adder is a parallel prefix form carry look-ahead adder. Carry look-ahead addersimprove speed by reducing the amount of time required to determine carry bits. However, as the size of

the adder increases (N > 16), the delay of passing the carry through the look-ahead stages becomes

dominant. This delay can be reduced by constructing a multilevel tree of look-ahead structures.


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Figure 3: Kogge-Stone Adder (KSA)

Figure 4: Kogge-Stone Adder (KSA) Schematic


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3.2. Array MultiplierThe design of the array multiplier is shown below. The array multiplier is a parallel multiplier that

operates faster than a serial multiplier. Here, we have implemented a 6-bit unsigned array multiplier.

The basic blocks are the full adder (FA) and the AND gate. The total number of full adder blocks is

At each full adder, the output is given bySUM = ((A XOR B) XOR CIn)COUT = ((A AND B) OR (B AND CI) OR (CIn AND A))

Each output is computed by adding the AiBj in the respective column with the carry out from the

previous column. The final 12 bit output includes both combinatorial and propagation delays.

Figure 5: Array Multiplier


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Figure 6: 6-bit Array Multiplier Schematic

Figure 7: 6-bit Array Multiplier Test


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Figure 8: 6-bit Array Multiplier Test Output (101x001=101, the lower three O/Ps)

3.3. Two Phase Clock

A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized

like a metronome to coordinate actions of circuits. In synchronous circuits, a "two-phase clock" refers to

clock signals distributed on 2 wires, each with non-overlapping pulses. Traditionally one wire is called

"phase 1" or "phi1", the other wire carries the "phase 2" or "phi2" signal.

Figure 9. 2-phase clock


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Figure 10: 2-phase clock schematic

Figure 11: 2-phase clock simulation run


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3.4. Masterslave edge-triggered D flip-flop

A masterslave D flip-flop is created by connecting two gated D latches in series, and inverting the

enable input to one of them. It is called masterslave because the second latch in the series only

changes in response to a change in the first (master) latch.

Figure 12 : Clocked D-flipflop

Figure 13: Master Slave D flip flopWorking of the Master-Slave D Flip Flop

For a positive-edge triggered masterslave D flip-flop, when the clock signal is low (logical 0) the

"enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the

"master" latch to store the input value when the clock signal transitions from low to high.As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the

value seen at the input to the master latch is "locked".

Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low

to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the

now "locked" master latch to pass through the "slave" latch.


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When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value

seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in

preparation for the next rising clock edge.

Figure 14: Master Slave D flip flop Schematic

3.5. Master-Slave D Flipflop with Clear-EnableThis is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clock inputs and data

output (Q). The Data on the D input is loaded into the flip-flop CE is High on the Low-to-High clock (C)

transition. When CE is Low, the clock transitions are ignored.


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Figure 15: Synchronous D-flipflop with enable (for the Coeff. Address registers)

Figure 16: D-flipflop simulation run


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Figure 17: 6-bit Register using D-flipflops

3.6. Decoder

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the

original information can be retrieved. It is a combinational circuit that converts binary information from

n input lines to a maximum of 2nunique output lines. Here, we show a 2 X 4 decoder where we have 2

input lines and 4 output lines.

Figure 18: 2 X 4 Decoder


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Figure 19: 2 X 4 Decoder Schematic

Figure 20: 2 X 4 Decoder test setup


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Figure 21: 2 X 4 Decoder (S0-1, selects the values, Q0 can be seen selected for S0=0,S1=0)

Figure 22: 4x16 decoder using 2x4 decoders

4x16 decoder can be easily constructed using 2x4 decoders as has been done here. The output of 1 2x4

decoder is used as enable pins for 4 other 2x4 decoders.


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3.7. Pipeline

The pipeline is our design consists of the adder, the multiplier and the coefficient register. The inputs to

the pipeline are the 16 input SUM bits (SI0- SI15), the data bits from the data register (DI0- DI5) and the

coefficient bits from the K registers (CI0-CI5).

The outputs for the pipeline register are the output Sum bits (SO0-SO15) which form the SUM inputs for

the next filter stage.

Figure 23: The schematic for the pipeline


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3.8. Complete FIR Filter

Figure 23: The complete filter with 16 pipelines

Figure 24: The Filter with 4 pipelines that was used for simulation


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4. Testing the FIR FilterAn impulse response test was performed on the FIR filter. Values were directly provided to the filter and

the output was checked for correctness. The delay of the 4 (due to the 4 pipelines) clock cycles can be

clearly seen. The outputs appear to have noise however the amplitude of these noise signals is in the

order of E-3, hence are practically zero. The intended time period of the results is the first 500ns when

the signals have the intended values. The period after 500ns has new values coming in which get added

onto output streams.

Data Input (DI): 010010 (h12)

Coefficient input (CI) : 111110 (h3E)

Input to the Filter sum inputs (SI0-SI15) : 0000 0000 0000 0000 (h00)

Outputs expected : 0000 0100 0101 1100 (h45C)

Outputs Observed : 0000 0100 0101 1100 (h45C)

Figure 25: Test setup for the filter


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Figure 28: Output values showing clk and SO0-SO3

Figure 29: Output values showing SO2-SO7


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Figure 30: Output values showing SO7-SO12


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5. ConclusionThe FIR filter was designed and each component was simulated and tested for correctness. The impulse

test was performed on the FIR filter chip and the design was simulated using HSPICE. The impulse

response test was performed and the desired results were found to show that the filter works as

intended. This design of filter can be used in many filtering applications requiring the use of a FIR filter.

6. References

[1] 6 bit array multiplier :

http://wiki.arnesenfamily.net/doku.php?id=byu:projects:array_multiplier

[2] 2x4 bit decoder :

http://en.wikibooks.org/wiki/Fundamental_Digital_Electronics/Digital_Decoder

[3]4x16 bit decoder :

https://wiki.engr.illinois.edu/download/attachments/86048908/SOL_HW4_sp11.pdf?version=2&modifi

cationDate=1304477265000

[4] 2 phase clock :

http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-

phase-clock-gen.html

[5] d flip-flop :

http://www.play-hookey.com/digital/sequential/d_nand_flip-flop.html

[6] register:

http://faculty.kfupm.edu.sa/COE/ashraf/RichFilesTeaching/COE022_200/Chapter%205.htm

[8] http://www.engr.sjsu.edu/dparent/ee166/adder_verification.pdf

[9] Principles of CMOS VLSI Design, Second Edition, Neil H. E. Weste and Kamran Eshraghian, Addison

Wesley, 1993

[10] Principles of CMOS VLSI Design, Third Edition, Neil H. E. Weste and David Harris, Addison Wesley,

2004

[11] Wikipedia

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Designing a FIR filter

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