AN-H60 Application Note Application Circuit Designing a Four-Channel, Return-to-Zero, Ultrasound Pulser Using Supertex HV7370 & HV748 ICs By Ching Chu, Sr. Application Engineer Introduction The Supertex HV7370 is a four-channel, high speed, high voltage, ultrasound transmitter damper, and the HV748 is a four-channel, high speed, high voltage ultrasound transmitter pulser. Both integrated circuits (ICs) are designed for medical ultrasound imaging applications. They can also be used as piezoelectric, capacitive or MEMS sensors in ultrasonic nondestructive detection and sonar ranger applications. These high performance CMOS ICs are in 5x5x0.9mm 32- lead QFN (HV7370) and 7x7x0.9mm 48-lead QFN (HV748) packages. The HV7370 can be also used as a damping circuit with Supertex’s HV738 and HV758 pulsers to generate fast return- to-zero waveforms. Depending upon the load capacitance, the frequency limit of this IC is as high as 20MHz. HV7370 consists of four controller logic interface circuits, four level translators, four MOSFET gate drivers and four pairs of high current N- and P-channel MOSFETs that serve as the four push-pull output stages. The output stages of each channel are designed to provide peak damping currents over ±0.85A with up to ±100V pulser (V PP /V NN ) voltage. The HV7370’s N- and P- MOSFET gate drivers are supplied by ±5~12V (typical 8.0 to 11V) on V DN & V DP pins. The voltages V DN and V DP are referenced to ground (0V). The output pins of the HV7370 (PD1~4 and ND1~4) are able to pull down from or up to ±100V on the capacitive loads, which have been charged by the high voltage pulser channels. However, the V PP and V NN of the HV748 high voltage pulser on this demoboard can only go up to ±75V. The damping action of the HV7370 is independently controlled by the damper input logic signals IN1 to IN4.Internally the logic signal controls a direct-coupled low voltage to high voltage lever translator to switch the output MOSFETs. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. +3.3V OSC JTAG EXCLK EN 5 FREQ ENA SEL WAVE TEST MC1 MC0 PWR END ENP OPT 0 to -65V +3.3V 0 to +75V +9V TX1 R3 2.5K C4 330pF 40MHz VPP-9V +75V VNN+8V +3.3V +9V -9V +9 to +75V +9V (Damp1-4) 6 GND Dummy Load R2 Option R1 D1 D2 EN PIN1-4 MC0,1 OTP NIN1-4 VSUB VDD VLL GREF TXN1 VNN TXP1 VPP RGND VPF VSS VNF (1 of 4 Channel Output Shown) HV748 EN IN1-4 VSUB VDD VLL GREF ND4 PD4 RGND VDP VSS VDN (1 of 4 Channel Output Shown) RGND HV7370 CK IN Waveform Generator CPLD L
Transcript
AN-H60Application Note
Application Circuit
Designing a Four-Channel, Return-to-Zero, Ultrasound Pulser Using Supertex HV7370 & HV748 ICs
By Ching Chu, Sr. Application Engineer IntroductionThe Supertex HV7370 is a four-channel, high speed, high voltage, ultrasound transmitter damper, and the HV748 is a four-channel, high speed, high voltage ultrasound transmitter pulser. Both integrated circuits (ICs) are designed for medical ultrasound imaging applications. They can also be used as piezoelectric, capacitive or MEMS sensors in ultrasonic nondestructive detection and sonar ranger applications. These high performance CMOS ICs are in 5x5x0.9mm 32-lead QFN (HV7370) and 7x7x0.9mm 48-lead QFN (HV748) packages.
The HV7370 can be also used as a damping circuit with Supertex’s HV738 and HV758 pulsers to generate fast return-to-zero waveforms. Depending upon the load capacitance, the frequency limit of this IC is as high as 20MHz.
HV7370 consists of four controller logic interface circuits, four level translators, four MOSFET gate drivers and four pairs of high current N- and P-channel MOSFETs that serve as the four push-pull output stages.
The output stages of each channel are designed to provide peak damping currents over ±0.85A with up to ±100V pulser (VPP/VNN) voltage. The HV7370’s N- and P- MOSFET gate drivers are supplied by ±5~12V (typical 8.0 to 11V) on VDN & VDP pins.
The voltages VDN and VDP are referenced to ground (0V). The output pins of the HV7370 (PD1~4 and ND1~4) are able to pull down from or up to ±100V on the capacitive loads, which have been charged by the high voltage pulser channels. However, the VPP and VNN of the HV748 high voltage pulser on this demoboard can only go up to ±75V. The damping action of the HV7370 is independently controlled by the damper input logic signals IN1 to IN4.Internally the logic signal controls a direct-coupled low voltage to high voltage lever translator to switch the output MOSFETs. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier.
+3.3V
OSC
JTAG
EXCLK
EN
5
FREQ
ENASEL
WAVE
TEST
MC1MC0PWR
END
ENPOPT
0 to -65V
+3.3V 0 to +75V+9V
TX1
R32.5K
C4330pF
40MHz
VPP-9V+75V
VNN+8V
+3.3V +9V -9V+9 to +75V
+9V
(Damp1-4)
6 GND
DummyLoad
R2
Option
R1 D1
D2
EN
PIN1-4
MC0,1
OTP
NIN1-4
VSUBVDDVLL
GREF
TXN1
VNN
TXP1
VPP
RGND
VPF
VSS VNF
(1 of 4 Channel Output Shown)
HV748
EN
IN1-4
VSUBVDDVLL
GREF
ND4
PD4
RGND
VDP
VSS VDN
(1 of 4 Channel Output Shown)
RGND
HV7370
C KIN
WaveformGeneratorCPLDL
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AN-H60Application Note
Designing an RTZ Pulser using Supertex’s HV7370 & HV748 This application note describes how to use the HV7370 damper and the HV748 pulser to design a high speed return-to-zero (RTZ) pulser.
The output of the damper must go through two DC blocking diodes to connect to the pulser output as the schematic shows. Having the diode pair D1 connected in series with the pulser output is optional because in the three-level RTZ pulser design, the pulser’s VPP/VNN supplies are the highest/lowest voltage rails, and therefore there is no need for the DC-blocking function.
The diode pair D2 are necessary, however. Because the damper’s MOSFETs have both sources connected to RGND, both damping outputs must have the DC blocking diode in series before they connect to the pulser’s output summing node. These diodes are directing current and blocking any reverse current that would otherwise pass through a MOSFET body diode. If one is going to design a five-level RTZ pulser, then the output of the middle level pulser should also have these current steering diodes. Usually these diodes must be high voltage, high peak current and fast reverse recovery time diodes.
The input stages of both HV7370 and HV748 are high-speed level translators that are able to operate with logic signals of 1.8 to 5.0V and are optimized for 2.5 to 3.3V. In most medical imaging systems, these control signals are from an FPGA. If the control line traces are longer than about 2 inches (50mm), it is suggested that each control line should have a 50Ω resistor in series, located near the FPGA output pin, for impedance matching to the 50Ω impedance of their PCB traces.
In this design example, the control logic signal is generated from an on-board CPLD chip. The control logic line is very short; therefore the series resistors are not needed. The logic level of this CPLD is 3.3V on this design example board. The programmable CPLD uses a 40MHz crystal oscillator as the on-board clock to generate a fast clock signal to control the timing of this RTZ pulser.
There are six-pin JTAG connections for the USB or parallel CPLD programming link-cable. Users can easily modify the test waveforms according their own test pattern requirements.
There is also an external clock input in this design example. By inserting a shorting jumper, which disables the on-board oscillator, the user can instead connect an external 3.3V clock.
There are five push buttons for selecting the test waveform, frequency, select, enable and test functions. There are six color LED indicators associated with these push button control functions. There are four on-board equivalent-loads, and each one has a 330pF capacitor in parallel with a 2.5KΩ 1W resistor via the small copper trace shorted zero Ω resistors connected to the RTZ pulser outputs for each channel. The user can easily evaluate the transducer(s) with this HV7370 and HV748 RTZ transmitter pulser. Just open the short(s) and, using the coaxial cable, directly connect to the output test points to the transducer.
PCB Layout TechniquesIt is important that the thermal slab at the bottom of the HV748 package be externally connected to its VSUB pins to make sure that it always has the highest potential in any condition, because this is the connection of the IC’s substrate.
In order to guarantee that the HV748 VSUB will never be below its other voltage rails, even during the power-up or down time periods, it is strongly recommended that a set of Schottky diodes be added to the PCB of the pulser circuit. Each voltage supply rail must have a 2~3A Schottky diode connected to ground as part of the normal protection scheme used in multi-rail CMOS power supply design. We suggest that you add two more diodes for power up/down protection: one Schottky from VCC, VLL (+3.3V in this design) to VDD, and other one from VDD to VSUB of HV748. Adding these two additional Schottky diodes means that the system can power-up the VCC +3.3V first, then power-up the VDD second, all before turning on the HV748 VSUB voltage. To have the VCC turned on first is very practically important in system power sequence design, because it allows the CPU and FPGA control circuit to be up working first or powered down last, thus allowing all the other voltage rails to be under CPU and logic control. Furthermore, once the CPU and control logic are working, these should immediately initialize all pulser and damper chip enable and control signals to zero. After VCC is powered-up with the said Schottky on board, the VDD and VSUB voltage will be only one or two Schottky diodes’ forward-drop voltage away from the VCC voltage. This will protect the IC from having substrate bias voltage reversal or latch up.
The VDD rail (+8 to +12V) provides internal bias and low side control circuits supply voltage in both HV748 and HV7370. In most cases, the VDD or the unregulated VDD voltage source will also be used for the input power supply of the isolated DC/DC converter for the two floating rails (VPP - VPF) and (VNF - VNN), and for the non-isolated DC/DC converter (for -9V VDP etc.). Turning the VDD supply on is second in the power-up sequence and can be under CPU or logic control.
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AN-H60Application Note
It is also important to make sure that the thermal slab at the bottom of the HV7370 package be externally connected to HV7370’s VSUB pin and that the HV7370 VSUB pin be connected to its VDD or HV748’s VSUB voltage. It is recommended to have 0.1~0.22μF capacitors decoupling for both HV748 and HV7370 VSUB and placed very close to the pins.
Designers need to pay attention to the connecting traces as high-voltage and high-speed traces. In particular, low capacitance to the ground plane and larger trace spacing is required.
Use high-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds. The internal circuitry of the HV7370 and HV748 can operate with high frequencies, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors should be as close to the pins as possible. The GREF and VLL are the low and high logic level reference pins that should connect to the control logic circuit ground and VCC voltage, with a 0.1uF ceramic decoupling capacitor connected in between.
The VDD, VDN, VDP, VPP, VNN and VSUB pins are voltage supplies referenced to ground. The MOSFET gate-driver floating supplies (VPF and VNF) are referenced to VPP and VNN high voltage power supplies respectively. All these power supply rails can be shared for multiple HV748 and HV7370 chips if there are a large number of transmit channels in the system. All the power supply pins of each channel can draw fast transient currents of up to ±0.8 to ±1.25A, so they should be provided with a low-impedance bypass capacitor located close to the pins. Use an X7R or X5R 0.47 to 1.0μF ceramic capacitor for each pin or or pair of pins. All by-pass capacitor ground pads should have low inductance feed-through via connections that are connected directly to a solid ground plane. Minimize the trace length to the ground plane, and insert a ferrite bead low value resistor in the power supply lead to the capacitor to prevent resonance in the power supply lines.
Pay particular attention to minimizing trace lengths and using sufficient trace widths to reduce inductance. Surface mount components are highly recommended. Since the output impedance of pulser HV748’s and damper HV7370’s output stages is very low, in most cases it is desirable to add a 5 to 18Ω pulser current rated resistor in series with the output to obtain better waveform integrity at the load transmission line terminals. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load.
Be aware of the parasitic coupling from the outputs back to the input signal terminals of the HV7370 and HV748. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V, even small coupling voltages may cause problems. The use of a solid ground plane and good power and signal layout practices will prevent this. Testing the Integrated PulserThis HV7370 and HV748 RTZ pulser design example is tested with multiple lab DC power supplies with current limiting functions. The following power supply voltages and current-limits settings are used in the testing: VPP +75V 2.5mA; VNN -75V 2.5mA; VDD +9.0V 20mA; VDN +9.0V 5mA; VDP -9.0V 5mA; VPF and VNF two isolated DC/DC floating 9.0V 5mA.; and VCC and VLL +3.3V 70 to 80mA. The +3.3V supply current is mainly for the VCC current of the +3.3V-only CPLD.
The on-board dummy load 330pF//2.5kΩ is connected to the RTZ pulser output through the zero Ω resistor on board with default as shorted for using the oscilloscope high impedance probe to look at the output waveforms as the typical load condition. For looking into the different loading conditions, one may change the values of dummy loads within the current and power limitations of the device.
In order to drive the user’s piezo transducers with a cable, one should connect each output in series with a small 6.2Ω to 22Ω pulse current rated resistor to match the load and cable impedance properly. This is to avoid large cable and transducer reflections. Usually the ultrasound cable is 50Ω to 75Ω impedance rated.
The on-board test point is designed to work with high impedance probes of the oscilloscope. Some probes may have limited input voltage. When using a probe on the test-points of the pulser outputs, make sure that VPP/VNN does not exceed the probe limits. Using the high impedance oscilloscope probe on the onboard test points, it is important to have as short ground leads to the circuit board ground plane as possible.
There are multiple frequency and waveform combinations that can be selected as bipolar pulses and PW with and without RTZ waveforms. The frequency of the pulses are 10, 5, 2.5MHz, etc. If one needs a specific transducer frequency, an external clock input can be used instead if the on-board 40MHz-oscillator is disabled with a jumper shorted to ground. There are push buttons for selecting the waveform, frequency, phase, and HV748 & HV7370 chip enable functions. Color LEDs indicate the test selection states.
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AN-H60Application Note
The HV7370 & HV748 RTZ pulser circuit schematic, input and output waveforms diagrams, detailed signal definitions, and testing of measured waveforms are shown below.
There are push buttons for selecting the waveform, frequency, phase, and HV748 & HV7370 chip enable functions. Color LEDs indicate the demo selection states.
The HV7370DB1 RTZ pulser circuit schematic, input and output waveforms diagrams, detailed signal definitions, and testing of measured waveforms are shown on the following pages.
HV7370 RTZ Pulser Schematic
VDD = +9V
TP23
TX33
1
2
D11BAV99
VDD
TP31
TP1
VSUBP
C21330p 250V
R192.55K 1W
TX4
D8YLW
R3310 VCC = +3.3V
VCC
VCC
VDP
R3710
TP32
TP38
3
1
2
D13BAV99
TP34
VSUBP
3
1
2
D12BAV99
C29330p 250V
VDD
R242.55K 1W
3
1
2
D14BAV99
VSUBD
C170.22
C100.22
C120.22
C160.22
R3410
TP17
DMP1TP21
C80.22
3
1
2
D2BAV99
TP24
C70.22
VDN
R3810
C15
1u 100V
VCC
DMP2
VDP
VNN = 0 to -75VVPP = 0 to +75V
C11
0.22
VNN
R220
TP39
C260.22
DMP3
R3510
C91u 100V
C25
0.22
VDN
R20
C130.22
3
1
2
D10BAV99
43
D21B
DMP4
VDD
TP15
R3610
MH2 MH3 MH1MH4
TP16
VPP
VPP
TP40
TP20
VDP = -9VVDN = +9V(Or VDD)
C61u 100V
R21INF
3
1
2
D1BAV99
R120
VDN VDP
TP41
16
D20A
16
D19A
BAT5
4DW
-7
TP19
R17INF
16
D21A
BAT5
4DW
-7
R180
END
TP4
21
D15
B110
0-13
TP8
C50.22
R230
TP22
R11INF
+9V
D4YLW
R5
1K
D5YLW
VSUBD
R6
1K
C180.22
TX1
R7
1K
TP10
D7RED
R8
1K
2 34 5 6 910 11
15
17
1819202122
2425
262829303132 35
39
40
43
7
363738
12131416
TP12
R1INF
TP9
12
J1
D6GRN
1 2 3 4 5 6
J3
VCC
TP25
TP5
TP6
D3RED
VCC
VPP
C10.22
C20.22
R45324
C14
1u 100V
R2833K
R44200
C350.22
VCC
C300.22
R43200
C340.22
R2533K
R2633K
SW2
R2733K
SW3 SW4
TP27
SW1
R2933K
SW5
R42200
C330.22
R41200
C320.22
R40200
VCC
VPF
R100
C310.22
21
D16
B1100-13
1
23
J2
TP3
C220.22
SYNC
VCC
R161k
EXTRG
R141K
EXCLK
JTAG
R1550
TP2
EX=0
TP30
C30.22
VCC
TP28
R46INF
VCC
EN1
GND2 OUT
3
VCC4
X140MHz
TP18
R4
1K
R201K
TP13
TP7
VPF
R47324
TP29
END
R3910
R49324
R50INF
VNN
TP35
R301
VSUBPVCC
R51324
R52INF
C4330p 250V
(VPP - VPF) = +9V(Isolated)
+9V-9V
VSUBP
R32.55K 1W
TP36
VDD
C230.22
43
D20B
+9V or VSUBP
C271u 100V
VNF
+75V > VSUBP > VPP
43
D19B
BAT5
4DW
-7
C190.22
R91K
21
D17
B110
0-13
VDD
VNN
C24
0.22
TP33
VNF
82
3
4
5
6
7
9
1011
2829 26
1612
17
18
19
20
21
22
23
24
13 25
15
30 31
32
1
14
27
C281u 100V
R48INF
VNN
DM
P2
(VNF - VNN) = +9V(Isolated)
R3110
TP26
12
34
56
78
910
1112
13
1415
16 17 18 19 2021222324
25
26
27
28
29
30
31
32
33
34
35
3637 383940
41 42 434445
46
47
48
VNF
TP11
3
1
2
D9BAV99
TP14
DM
P3
C20330p 250V
R132.55K 1W
DM
P1
21
D18
B110
0-13
VPF
VPP
DM
P4
TP37
1 2 3 4 5 6 7 8 9 10 11 12
J4 HEADER 12
TX2
VPP
R3210
WA
VFR
E
GN
D
SEL
ENP
TDI
TMS
TCK
VCC
GN
D
NIN3PIN3
DMP2NIN2PIN2
TDO
GN
D
VCC
ENP
PWR
MC
0M
C1
END
VCC
EXTRG
SYNC
CLK
TES
T
DMP1NIN1PIN1
DMP4NIN4PIN4
DMP3CPLD
XC9572XL_VQ44
VDD
VSS
PIN1NIN1
PIN2NIN2
PIN3NIN3
PIN4NIN4
VSS
VDD
OTP
MC1MC0
VSU
BP
VPF
VPP
VPP
VPP
VNN
VNN
VNN
VNF
VSU
BP
RG
ND
TXN4
TXP4
TXN3
TXP3
TXN2
TXP2
TXN1
TXP1
RG
ND
VSU
BPVN
F
VNN
VNN
VNN
VPP
VPP
VPP
VPF
VSU
BP
EN
GR
EF
VLL
HV748K6
VDD
VSS
IN1
IN2
IN3
IN4
VSS
NCVSU
BD
VDP
RG
NDR
GND
VDN
VSU
BD
RG
ND
ND4
PD4
ND3
PD3
ND2
PD2
ND1
PD1
RG
ND
VSU
BD
VDN
VDP
VSU
BD
EN
VLL
RG
ND
RG
ND
HV7370K6
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AN-H60Application Note
HV7370 RTZ Pulser Waveforms
PIN
NIN
TX
VPP
VNN
0V
DMP
Demo Waveform A (8-Cycle) Demo Waveform A` (8-Cycle)
PIN
NIN
Tx1
VPP
0V
DMP
Demo Waveform B (2-Cycle)
VNN
Demo Waveform B`(2-Cycle)
PIN
NIN
TX
VPP
VNN
0V
DMP
Demo Waveform C (4.5-Cycle) Demo Waveform C` (4.5-Cycle)
