Designing of a 8-bits DAC in 0.35µm CMOSTechnology For High Speed Communication

Systems ApplicationVeronica Ernita Kristianti, Hamzah Afandi, Eri Prasetyo Wibowo, Brahmantyo Heruseto and shinta Kisriani

Electrical Engineering, Gunadarma Universityvero_gundar@student.gunadarma.ac.id, hamzah@staff.gunadarma.ac.id

Abstract—The design of an 8-bit DAC used in this research isused for high speed communication systems. The main componentsused are the op-amp (operational amplifier), R-2R Ladder, and theMOS switch. The results of the design of op-amp characteristics meetof offset voltage, Voffset = 0 V. Research carried out by using thetools of Mentor Graphics software with AMS technology 0.35 µmCMOS process. The design of the DAC in this research producesspeeds up to 1000 Msps, these results suggest that the design meetsthe speed of high speed DAC categories ranging from 40-4300 Msps.Measurements of integral and differential nonlinearities of the DACdesign shows INL ± 1 LSB and DNL ± 1 LSB. Later in this research,the design of an 8-bit DAC is applied in the form SOC (System onChip).

Keywords—CMOS, DAC (Digital-to-Analog Converter), Opera-tional Amplifier (Op-Amp), and MOS Switch

I. INTRODUCTION

COmplementary metal-oxide-semiconductor (CMOS) is atechnology for constructing integrated circuits. CMOS

technology is used in microprocessors, microcontrollers, staticRAM, and other digital logic circuits. CMOS technology isalso used for several analog circuits such as image sensors,data converters, and highly integrated transceivers for manytypes of communication. Frank Wanlass patented CMOS in1967 (US patent 3,356,858).[1]

In this research the CMOS technology is used for applica-tions in the DAC (Digital-to-Analog Converter). CMOS designof the DAC in this research is used for high speed com-munication systems. DAC on-chip high-speed high-resolutionbased on the same CMOS process as the digital circuits thatare important for system applications such as Very high-datarate Digital Subscriber Line (VDSL), Direct Digital Synthe-sis (DDS), Wireless Local Area Network (WLAN), Quadra-ture Modulation (QAM), Direct Intermediate Frequency (IF),and Global mobile for mobile telecommunication (GSM), toachieve low power, small chip area, and high-speed perfor-mance. [2]

Fig. 1: High Speed DACs [3]

Based on the above data, the design of the DAC (Digital toAnalog Converter) can be said to be high speed if it have anupdate rate (Msps) between 40 - 4300 Msps.

DAC (Digital-to-Analog Converter) is a device to convertthe input signal in digital form into an output signal in theanalog form (voltage). The resulting DAC output voltageproportional with the digital value into the DAC. Modifiersor conversion tool is needed as the interfacing between ana-log components with digital components. Usually, the ADC(Analog-to-Digital Converter) there is a DAC block, where theADC is a device to convert analog signals into digital signals.Block DAC serves as feedback to correct errors and also tomake the reference voltage during the conversion. One of thecircuits used is a switch capacitor circuit that has high speedand is able to filter out unwanted frequencies

Fig. 2: Diagram Block DAC

This research has the following objectives are design andimplement a circuit of components into an 8 bit DAC for highspeed communication systems using CAD Mentor GraphicsAMS (Austria Micro Systems) technology 0.35 µm CMOSprocess, and set up a 8-bit DAC design results in the form of

SOC (System on Chip).

II. RELATED WORK

In electronics, a digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually binary) code to ananalog signal (current, voltage, or electric charge). An analog-to-digital converter (ADC) performs the reverse operation.Signals are easily stored and transmitted in digital form, buta DAC is needed for the signal to be recognized by humansenses or other non-digital systems. [4]

The most common types of electronic DACs are: pulse-width modulator, delta-sigma DAC, binary-weighted DAC, R-2R ladder DAC, thermometer-coded DAC, and Hybrid DACs.[4]

A. R-2R Topologies for DACs• The Current-Mode R-2R DAC

The R-2R DAC can be classified into two categories:voltage-mode and current-mode. A current-mode R-2RDAC is shown in Fig. 3. The branch currents flowingthrough the 2R resistors are of a binary-weighted rela-tionship caused by the voltage division of the R-2R laddernetwork and are diverted either to the inverting input ofthe op-amp (actually the feedback resistor) or the non-inverting input of the op-amp (actually VREF−).[5]

Fig. 3: Traditional current-mode R-2R DAC [5]

• The Voltage-Mode R-2R DACFig. 4 shows a schematic of a voltage-mode DAC. Theoutput of the N-bit voltage-mode DAC can be written as[5]

(1)If the input code is all zeroes, with VREF− = 0,VREF+ = V DD, and the op-amp in the followerconfiguration, then VOUT = VREF−. If the input codeis all ones, then the output of the DAC is VREF+ − 1LSB.

Fig. 4: Traditional voltage-mode R-2R DAC [5]

• A Wide-Swing Current-Mode R-2R DACWe’ve shown that it is desirable to have a wide outputswing, as is provided by the voltage-mode R-2R DAC,while at the same time having a fixed input commonmode voltage, as is provided by the current-mode R-2R DAC. Fig. 5 shows a wide-swing current-mode R-2RDAC configuration that has a rail-to-rail output swingwhile keeping the input common-mode voltage of theop-amp fixed at the common mode voltage, VCM , or(VREF+ + VREF−)/2. [5]

Fig. 5: Wide-swing current-mode R-2R DAC [5]

Like traditional current-mode R-2R DACs, the DACscheme shown in Fig. 5 operates on currents. Usingsuperposition and assuming VREF− is the reference forcalculations, the current flowing in the feedback resistor,RF , is given by

(2)noting the inversion used in the control logic seen in Fig.5. The output voltage of the DAC is then given, assumingR = RF , by

VOUT = VREF− +VREF+ − VREF−

2+ IF ·R (3)

The matching between the resistors of the R-2R ladderis one of the most important and limiting factors thatdetermine the linearity (e.g., DNL and INL) of the entireDAC. It is helpful, when designing any type of resistorstring DAC, if we can estimate the resistor matchingrequirements based on a desired resolution. [5]

B. Operational Amplifier (Op-Amp)

Operational Amplifier is the IC that generates the outputvoltage Vo, which is the result of the strengthening of thedifference in voltage at both inputs (V1 and V2). [6]

Figure 6 showing standard op-amp notation. An op amp isa differential to single-ended amplifier. It amplifies the voltagedifference, Vd = Vp − Vn, on the input port and produces avoltage, Vo, on the output port that is referenced to ground.[7]

Fig. 6: Standard Op Amp Notation [7]

The basic form of an op-amp is a high gain dc-amplifier witha differential input port and a single output port. A differentialinput has two terminals, which are both independent of groundor common. The signal between these two terminals is theinput signal, which will be amplified. The terminals are callednon-inverting input and inverting input. [7]

C. The MOSFET as a Digital Switch

A simple description treats the MOSFET transistor as aswitch. The gate terminal is analogous to the light switchon the wall. When the gate has a high voltage, the transistorcloses like a wall switch, and the drain and source terminalsare electrically connected. Just as a light switch requires acertain force to activate, the transistor gate terminal needsa certain voltage level to switch and connect the drain andsource terminals. This voltage is called the transistor thresholdvoltage Vt and is a fixed voltage for nMOS and for pMOSdevices in a given fabrication process. [8]

Each transistor works like switch, which its work systemwill be in closed condition or open condition. On the figure10, if input series is signed 0, so transistor type N is opencondition and transistor type P is closed condition so VDDvoltage will pass through that transistor type P and output is1. On the other way, if input is signed 1, so transistor typeP is open condition and transistor type N is closed condition.So the voltage from ground will pass through transistor typeN and the output series is 0. [9]

Fig. 7: A transistor modeled as a switch [8]

Fig. 8: Inverter Series of CMOS[9]

III. RESEARCH METHODS

A. DAC Design for High Speed Communication SystemsMethods

Fig. 9: Stages in DAC Research Design

In the research of this DAC design for high speed commu-nication systems, three phases of the design as shown in Fig.11 is being conducted. The first stage is expected to resultedschematic design of the simulation with a prototype digitalsignal given in. Once the schematic design is complete, thenext phase of activity is the manufacture of layout. The resultsof this stage of the design layout is a clear form which is asettlement in the previous stage, which can then be processedaccording to CMOS technology in this case 0.35 µm CMOStechnology using a form of floor plan or SOC (System onChip) which will then be applied in the fabrication process.Fabrication stage is the stage of completion with carrying outorders to the manufacturer’s chip CMOS chips based on the

results of the design layout and floor plan that has been madein the previous stage.

B. Supporting Component DAC DesignIn designing DAC there are supporting components where

the value of each component (in this case the value of eachtransistor) must be determined. Those determination throughmanual calculation process, then adjusted at the time of sim-ulation. In the calculation process there are some parametersshould be considered, and the accordance parameter with theAMS technology 0.35 µm CMOS process are as follows:

• Constants of MOS is variables (Kn = 155 µA/V s/d 195µA/V dan Kp = 50 µA/V s/d 70 µA/V)

• Threshold voltage of MOS is also variables (VTHn =0,40V s/d 0,64V dan VTHp = -0,53V s/d 0,77V).

1) Operational Amplifier Design (Op-Amp): Operationalamplifiers (op-amp) in the DAC design consist of four parts;there are a constant current source, current mirror, differentialamplifier, and output amplifier.

Fig. 10: Op-Amp circuit

• Constant Current SourceWith the VDD value is 3.3 V and VSS value is -3.3 V.From equation ıD on saturation state can be derived tocalculate the VGS , there is:

VGS =

√2LIDKnW

+ VTHn (4)

VSG =

√2LIDKpW

+ VTHp (5)

VDD = VSG8 + VGS9 + VGS10 + VSS

ID8 = 84.48µA

• Current MirrorVGS voltage on the PMOS M6 and M7 are the sameas the VGS voltage on the PMOS M8. So the equationsobtained are as follows:

ID8L1

W1= ID7

L2

W2= ID6

L3

W3(6)

ID7 = 184.27µA

ID6 = 498.46µA

• Differential AmplifierPreviously, from the current mirror circuit ID7 that havebeen obtained in the calculation of 184.27 µA, performedcalculations to gained the value of VSG. This step needto be done in order to obtain the value (W/L)1−4. Thesolutions are as follows:ID7 =

Kp

wW2L (VSG + VTHp)

2

WL = 54.82

L1,2 = 0.7µm ; W1,2 = 38µm

L3,4 = 0.35µm ; W3,4 = 8µm

• Output AmplifierPreviously, the current mirror circuit iD6 that have beenobtained in the calculation of 498.46 µA, performedcalculations to obtain the value of VSG. This step need tobe done in order to obtain the value (W/L)5. As followsis the solution:498.46µA = Kn

wW2L (VSG + VTHn)

2

WL = 43.7

L5 = 0.35µm; W5 = 15µm

TABLE I: Results Changes Value of the W/L at the Op-Amp

Description First Simulation Second SimulationM1 38/0.7 40/0.7M2 38/0.7 40/0.7M3 8/0.35 20/0.35M4 8/0.35 20/0.35M5 15/0.35 85/0.35M6 29/0.35 29.5/0.35M7 10.9/0.35 10.905/0.35M8 5/0.35 5/0.35M9 1.21/0.35 1.21/0.35M10 1.21/0.35 1.21/0.35

2) MOS Switch Design: As follows are the calculations todetermine the value of W and L in each transistor:

• PMOS

ID =Kp

2W2L (VM + VTHp)

2

Lp = 0.35µm ; Wp = 1.3µm

• NMOS

ID = Kn

2W2L (VM + VTHn)

2

Lp = 0.35µm ; Wp = 0.5µm

3) R-2R Ladder DAC Design: Another supporting com-ponent after the op-amp is a component of the R-2R LadderDAC. In this research, word of bits used is 8 bits, so it isthe required resistor 16 as much as units consist of 7 unit ofresistor R and 9 unit of resistor 2R.

Each resistor then converted into a transistor, by using theequation as follows:

Rn =VDD

Kn

2WL (VDD − VTHn)

2 (7)

• If R = 10 KΩ, then L = 0.35 µm, W = 1.7 µm• If 2R = 20 KΩ, then L = 0.35 µm, W = 0.8 µm

The resistors on R-2R Ladder then modified by using transis-tors.

Fig. 11: R-2R Ladder DAC Circuit (Transistor)

IV. TESTING AND RESULTS

As seen in Fig. 14, which indicates that the line VPOS

(Positive Voltage) as the input voltage and a line indicatingthe output voltage VOUT meet at one point on the voltage of 0volts. This shows that the simulated op-amp to reach the offsetvoltage as one of the characteristics of the op-amp (Voffset =0 volts) is obtain. Evidenced by doing magnification of up totwo to three times, the second voltage VOUT and VPOS stillpass voltage 0 volts.

Fig. 12: Simulation Results of Offset Voltage

Simulations were also performed for AC voltage by using a10 MHz input frequency to find a large open loop gain (AOL),phase margin (PM), and frequency of unity (GBW).

Fig. 13: Simulation Results of Amplification AoL, GBW,and PM Op-Amp

TABLE II: Simulation Result of Amplification AoL, GBW,dan PM Op-Amp

AoL GBW PM63.9 dB 167.7 MHz 67.70

In this simulation stage, the circuit has been in combinationwith an op-amp and MOS circuit switches. By providingvarying values (0 and 1) at the input digital data, and referencevoltage (VREF = 1.5 Volt).

Fig. 14: Simulation Results of 8-bit DAC

Fig. 15: Simulation Results of 8-bit DAC (continue)

TABLE III: The Value of Analog Voltage with VREF 1.5 VBased on The Simulation

D7 D6 D5 D4 D3 D2 D1 D0 VOUT

0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0.00040 0 0 0 0 0 1 0 0.0040 0 0 0 0 0 1 1 0.010 0 0 0 0 1 0 0 0.0150 0 0 0 0 1 0 1 0.020 0 0 0 0 1 1 0 0.0290 0 0 0 0 1 1 1 0.030 0 0 0 1 0 0 0 0.040 0 0 0 1 0 0 1 0.0450 0 0 0 1 0 1 0 0.050 0 0 0 1 0 1 1 0.0570 0 0 0 1 1 0 0 0.060 0 0 0 1 1 0 1 0.070 0 0 0 1 1 1 0 0.0750 0 0 0 1 1 1 1 0.08...

......

......

......

......

1 1 1 1 1 1 1 1 1.49

The design of 8-bit DAC in this research produces speedsup to 1000 Msps, which is based on the category of high speedDAC, the design of 8-bit DAC is included into the categoryhigh speed, so it can be used for the communication system.

TABLE IV: Results of 8-bit DAC Design

Parameter 8-bit DAC [Results of Design]Resolution 8 bit

Rate 1000 MspsCMOS Process 0.35 µm 3.3 V

INL ± 1DNL ± 1

The layout results of the DAC schematic circuit as shownin figure 18.

Fig. 16: Layout 8 bit DAC

In this research the total component of the CMOS transistorsused is 42 pieces and one capacitor to the op-amp, using alayout area width of 221 µm x 96 µm = 21.216 µm2.

From design layout and specifications that have been gen-erated, then the fabrication process can be done. This layoutcan be made into a single chip or grown in an apparatus(Embedded System) as required. In this research the layoutis includes a chip (System on Chip) that is connected to thepins according to the function of each pin as shown in Fig.19.

Fig. 17: System on Chip

V. CONCLUSIONThis research discusses the design of the Digital to Analog

Converter (DAC) which was applied to the SOC (System onChip) for high speed communication systems. DAC circuitconsist of MOS switches, the R-2R Ladder, and the Op-Amp. Then the design is simulated using Mentor Graphics

software technology AMS 0.35 µm CMOS Process. From thesimulation results obtained can be summarized as follows:

1) Op-Amp design at DAC circuit in this research producesa precision offset voltage. Generate an open loop gain(AOL) of 63.9 dB, phase margin (PM) 67.7 degrees,and GBW at 167.7 MHz. The data obtained have metthe objectives of this research.

2) Circuit design switches are used in order to DAC circuitbe able to produce a residual voltage of the linearfeedback from the conversion of digital data.

3) R-2R Ladder circuit design main components beingused is resistor. In designing a layout the size of theresistor layout is very large and less efficient. Becauseof that we need a replacement component that is moreefficient but still have the same quality. In this research,a resistor circuit at the DAC can be replaced with NMOStransistors. And then after being simulated, the resultsobtained do not have any different with the output at thetime of the DAC circuit using a resistor. This is veryadvantageous especially from the standpoint of industrybecause it can save production costs.

4) The design of DAC in this research included into thecategory of high speed because the speed gained fromthe research is 1000 Msps. These results meet thespecifications of high speed DAC as described in figure1.

5) The results of the circuit layout design 8-bit DAC andthe floor plan in the form of SOC (System on Chip) isready for fabrication.

REFERENCES

[1] Wikipedia, “Cmos,” 2010. http://en.wikipedia.org/wiki/CMOS, accesson November 2010.

[2] J.-S. Y. S.-H. L. M.-Jung Kim, H.-Hee Bae, “A 3 v 12b 100 ms/s cmosd/a converter for high-speed communication systems,” SemiconductorTechnology and Science, vol. 3, pp. 211–216, December 2003.

[3] Maxim, High-Speed ADCs, DACs, and AFEs. Maxim Integrated Products,Inc, September 2008.

[4] Wikipedia, “Digital-to-analog converter,” 2011.http://en.wikipedia.org/wiki/Digital-to-analog_converter, access onOctober 2011.

[5] R. J. Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition.Wiley, 2010.

[6] Anonim, “Introduksi operational amplifier,” 2011.http://sunny.staff.gunadarma.ac.id/Downloads/files/2979/BAGIAN+1_Opamp.pdf, access on October 2011.

[7] J. Karki, “Digital video broadcasting,” White Paper: SLOA011, April1998.

[8] C. Hawkins and J. Segura, Introduction to Digital Electronics. Semi,2005.

[9] E. P. Wibowo and N. Huda, Desain Skematik, Layout, dan Simulasidengan Menggunakan Perangkat Lunak Mentor Graphics. Depok: Gu-nadarma University, March 2007.