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Page 1: Detailed Syllabus

09LV01 GRAPH THEORY AND OPTIMIZATION TECHNIQUES 3 0 0 3

BASIC CONCEPTS IN GRAPH THEORY: Undirected graph – degree of a vertex, degree sequence, subgraphs, vertex induced subgraphs, complement of a graph, self complementary graphs, walk, path, connectivity, eccentricity, radius, diameter, vertex and edge cuts, vertex partition, independent set, clique. Digraph – orientation, strongly, weakly and unilaterally connected digraphs, directed acyclic graph. Adjacency matrix and incidence matrix of graphs. Trees, spanning trees, matrix tree theorem. (6)

SPECIAL CLASSES OF GRAPHS: Complete graphs, bipartite graphs, grid graphs, Eulerian graphs - Euler’s theorem. Hamiltonian graphs – Dirac’s and Ore’s theorems, closure of a graph, Bondy-Chvatal theorem, traveling salesman problem. Planar graphs – Euler’s formula, Kuratowski’s theorem, embedding, dual, five color and four color theorems (without proof). Overlap graph, containment graph, interval graph, permutation graph, neighborhood graph and rectangular dual, relationship between these graph classes. (8)

GRAPH ALGORITHMS IN VLSI PHYSICAL DESIGN: Search algorithms – depth first search and breadth first search, spanning tree algorithms – Kruskal and Prim, shortest path algorithms – Dijkstra and Floyd-Warshall, vertex coloring – Welsh-Powell algorithm, matching, perfect matching, bipartite matching – augmenting path algorithm, min-cut and max-cut algorithms. (14)

LINEAR PROGRAMMING: Definition, simplex, two-phase simplex and dual simplex algorithms. (5)

DYNAMIC PROGRAMMING: Multistage decision process, computational procedure, final and initial value problems, continuous dynamic programming, discrete dynamic programming. (9)

Total 42REFERENCES: 1. Sherwani N A, “Algorithms for VLSI Physical Design Automation”, Springer-Verlag, 2007.2. Taha H A, “Operations Research”, Prentice Hall, 2003.3. West D B, “Introduction to Graph Theory”, Pearson Education, 2007.4. Yellen J and Gross J, “Graph Theory and its Applications”, Chapman & Hall, 2006. 5. Gerez S H, “Algorithms for VLSI Design Automation”, John Wiley, 2007.6. Kocay W and Kreher D L, “Graphs, Algorithms and Optimization”, Chapman & Hall, 2005. 7. Papadimitriou C H and Steiglitz K, “Combinatorial Optimization”, Prentice Hall, 1997.

09LV02 DEVICE MODELLING3 0 0 3

INTRODUCTION TO SEMICONDUCTOR PHYSICS: Review of Quantum Mechanics, Boltzman transport equation. Continuity equation , Poisson equation. (2)

INTEGRATED PASSIVE DEVICES: Types and Structures of resistors and capacitors in monolithic technology - dependence of model parameters on structure. (2)

INTEGRATED DIODES: Junction and Schottky diodes in monolithic technologies - static and dynamic behavior - small and large signal models - SPICE models. (8)

INTEGRATED BIPOLAR TRANSISTOR: Types and structures in monolithic technologies - Basic model (Eber - Moll) - Gunmel - poon model - dynamic model, parasitic effects - SPICE model - parameter extraction. (10)

INTEGRATED MOS TRANSISTOR: nMOS and PMOS Transistor - Threshold voltage - Threshold voltage equations - MOS device equations - Basic DC equations Second order effects - MOS models - Small signal AC Characteristics - MOSFET SPICE model level 1,2,3 and 4. (10)

VLSI FABRICATION TECHNIQUES: An overview of wafer fabrication, wafer processing- oxidation - patterning - Diffusion - Ion implantation - Deposition - Silicon Gate nmos process - CMOS process - nwell - pwell -Twin tub - Silicon on Insulator - CMOS process enhancements - Interconnects circuit elements. (8)

EMI ENVIRONMENT: Sources of EMI and EMC, Definitions and units of parameters, Radiation hazards to human beings. (2)

Total 42REFERENCES:1. Sze S M, ”Physics of Semiconductor Devices”, 2nd Edition McGraw Hill, New York, 1981.2. Ben G Streetman, "Solid State Circuits", Prentice hall, 1997.3. Tyagi M S, "Introduction to Semi-conductor Materials and Devices", John Wiley ,2003.4. Tor A Fijedly, “Introduction to Device Modeling and Circuit Simulation”, Wiley-interscience, 1997.5. Daniel Foty, " MOSFET Modeling with SPICE", Prentice Hall, 1997.

09LV03 VLSI SUBSYSTEM DESIGN3 0 0 3

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OVERVIEW OF VLSI DESIGN METHODOLOGY: VLSI design process - Architectural design - Logical design - Physical design - Layout styles - Fullcustom, Semicustom approaches. (4)

LAYOUT DESIGN RULES: Need for design rules - Mead Conway design rules for silicon gate nMOS process - CMOS nwell / pwell design rules - simple layout examples - Sheet resistance - Area capacitance - wiring capacitance. (6)

MOS INVERTER: nMOS inverter - steered input to an nMOS inverter - Depletion mode and enhancement mode pull ups - CMOS inverter - DC characteristics, Transient characteristics. (8)

LOGIC DESIGN: Pass transistor and transmission gate - static CMOS design, Pseudo nMOS, dynamic CMOS logic - Clocked CMOS logic - precharged domino logic. (7)

SEQUENTIAL LOGIC: Clocked sequential circuits - Two phase clocking - charge storage - Dynamic sequential circuits - JK Flip-flop circuit, Memory Design. (8)

VLSI BUILDING BLOCKS DESIGN: Adders, Shifters, PLA design - Arithmetic logic unit design -Multipliers Design using Booth's algorithm, Modified Booths Algorithm. (9)

Total 42REFERENCES:1. Jan M Rabaey, “Digital Integrated circuits - A design", Prentice Hall, Dec 2004.2. Kang, “CMOS Digital integrated Circuits”, McGraw Hill, 2002.3. Neil Weste and Kamran Eshranghian “Principles of CMOS VLSI Design”, Addison Wesley, 2000.4. Saida M Sait and Habib Youssef, “VLSI Physical Design Automation: Theory and Practice”, World Scientific

Publishing Company, 1st edition Nov 1999.5. Mead C and Conway L, “Introduction to VLSI Systems”, Addison Wesley, 1979.6. Glaser L and Dobberpuhl D, “The Design and Analysis of VLSI Circuits”, Addison Wesley, 1985.

09LV04 COMPUTER AIDED DESIGN OF VLSI SYSTEMS3 0 0 3

INTRODUCTION: VLSI Design cycle - Role of CAD tools in the VLSI Design process (2)

DATA STRUCTURES AND ALGORITHMS: Data Structures - Graph Theory – paths, trees, search algorithms, Complexity of algorithms, dynamic programming, Integer linear programming, Genetic algorithm, Simulated Annealing.

(8)

SIMULATION & SYNTHESIS: Compiler driven simulation-Event driven simulation - Switch level simulation - Circuit simulation - logic synthesis – two level synthesis ,Binary decision diagrams ,ROBDD principles (8)

PHYSICAL DESIGN AUTOMATION: Partitioning - KL, FM algorithms, Placement – Simulation based algorithms- Simulated Annealing , Force Directed Algorithm, Partitioning based algorithms- Breuer’s Algorithm, Terminal propagation Algorithm , Cluster Growth Algorithm , Floor planning – slicing floor plan , Constraint Based Floor Planning, Integer Program Based Floor Planning – Pin Assignment. (8)

ROUTING: Grid routing – Maze Routing Algorithms, Global routing - Shortest Path Based Algorithms, Steiner tree based Algorithms, detailed routing – Left Edge algorithm, Dog-Leg Algorithm , Greedy Channel Routing, Switch Box Routing algorithms- over the cell routing, Clock Routing. (8)

LAYOUT SYNTHESIS AND OPTIMISATION: Layout generation and Optimization of standard cell layout, gate matrix layout and PLA, Layout Compaction – one dimensional and two dimensional compaction (8)

Total 42REFERENCES:1. Sherwani N A, “Algorithms for VLSI Physical Design Automation”, Kluwer, 1999.2. Sait S M and Youssef H, “VLSI Physical Design Automation”, World Scientific, 1999. 3. Sabih H Gerez, “Algorithms for VLSI Design Automation”, John Wiley & Sons, 1999. 4. Micheli G D, “Synthesis and Optimization of Digital Circuits”, Tata McGraw Hill, 2004.

09LV05 HARDWARE DESCRIPTION LANGUAGE3 0 0 3

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BASIC CONCEPTS OF HARDWARE DESCRIPTION LANGUAGE:,Comparison between HDL and High Level Language Hierarchy, Concurrency, Logic and Delay Modelling, Structural, Data flow, Behavioral Styles of Hardware Description, Architecture of event driven simulation. (7) VHDL: Data Types, Operators, Classes of Objects, entities and architectures , Attributes – concurrent statements- sequential statements- signals and variables- Behavior, dataflow and structural modeling- Configurations, functions- procedures- packages - test benches- Design Examples (10)

VERILOG: Signals, Identifier Names, Net and Variable Types, operators, Gate instantiations, Verilog module, concurrent and procedural statements, UDP, sub circuit parameters, function and task, -test benches- Design Examples (15)

TIMING ISSUES: Modeling delay, Timing Modeling, Timing Assertion, Setup and hold times for clocked devices. (5)

SYSTEM MODELLING: Processor model, RAM model, UART Model, Interrupt Controller (5)

Total 42REFERENCES:1. Bhasker J, “A VHDL Primer”, Prentice Hall, 1999.2. Bhaskar J, “VHDL Synthesis Primer”, Prentice Hall, 2nd Edition 1998. 3. Bhasker J, “A Verilog Primer”, Prentice Hall, 1999.4. Bhaskar J, “Verilog Synthesis Primer”, Prentice Hall,1999.5. Stefan Sjoholm and Lennart Lindh, “VHDL for Designers” 1997.6. Michael D Ciletti, “Advanced Digital Design with Verilog HDL”, Pearson education,2005.7. Douglass Perry, “VHDL”, Tata McGraw Hill, McGraw-Hill Professional, 4th Edition, May 2002.8. Volnei A Pedroni, “Circuit Design with VHDL”, Prentice Hall, 2004.9. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Prentice Hall NJ, USA, 2003.10. Neil Weste and Kamran Eshranghian “Principles of CMOS VLSI Design”, Addison Wesley, 2000.

09LV06 LOW POWER VLSI DESIGN3 0 0 3

INTRODUCTION: Need for Low power VLSI chips - Low Power Design Methodology - Logic synthesis for Low power - Sources of Power dissipation. (8)

POWER ANALYSIS AND ESTIMATION: Gate level Analysis, Architecture level Analysis, Data Correlation Analysis, Monte-Carlo Simulation, Probabilistic Power Analysis. Statistical Techniques - Estimation of Glitching Power - Sensitivity Analysis - Circuit Reliability - Power Estimation at the circuit level - High level Power Estimation - Information Theory based approaches - Estimation of maximum power. (12)

POWER OPTIMISATION TECHNIQUES: Circuit Level – Transistor and Gate Sizing, Equivalent Pin Ordering, Network Restructuring and Reorganization, Special Latches and Flip Flops, Low Power Digital Cell Library, Adjustable Device Threshold Voltage. Leakage current in deep sub micrometer transistors- Transistor Leakage Mechanism – Leakage Current Estimation. Logic Level – Gate Reorganization, Signal Gating, Logic Encoding, State Machine Encoding, Precomputational Logic. Architectural and System Level – Power and Performance Management, Switching Activity Reduction, Parallel Architecture with Voltage Reduction, Flow Graph Transformation. Advanced Techniques- Adiabatic Computation, Pass Transistor Logic Synthesis, Asynchronous Circuits. (12)

LOW POWER STATIC RAM ARCHITECTURES: Organization, MOS Static RAM Memory Cell, Banked Organization, Voltage Swing Reduction, Power Reduction. (5)

LOW VOLTAGE CMOS VLSI TECHNOLOGY: BICMOS and Silicon On Insulator (SOI) Technology. (5)

Total 42REFERENCES:1. Kaushik Roy and Sharat C Prasad “Low Power CMOS VLSI circuit Design”, John Wiley and Sons, 2000.2. Gary B Yeap K, "Practical Low Power Digital VLSI Design”, Kluwer Academic Publishers, 1998.3. Kuo J B and Lou J H, “Low Voltage CMOS VLSI Circuits”, John Wiley and Sons, Singapore, 1999.4. Anantha P Chandrakasan and Robert W Brodersen, “Low Power Digital CMOS Design”, Kluwer Academic

Publishers, Holland, 1995.

09LV07 ANALOG VLSI CIRCUITS 3 0 0 3

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ANALOG CIRCUIT BUILDING BLOCKS: Switches, active resistors - Current sources and sinks - Current mirrors/amplifiers - Voltage and current references, Comparator, Multiplier. (8)

AMPLIFIERS: MOS and BJT inverting amplifier - Improving performance of inverting amplifier - CMOS and BJT differential amplifiers - Characterization of Op-Amp - The BJT two stage op-amp - The CMOS two stage op-amp -Op-amps with output stage, Folded Cascode op-amp, Transconductance Amplifier. (11)

FILTERS: Low pass filters - High pass filters – Band Pass filters – Phase Locked Loops (6)

DATA CONVERTER FUNDAMENTALS: Ideal A/D and D/A converters, Quantization noise, Signed codes, Performance limitations. (6)

D/A AND A/D CONVERTERS: D/A converter : Current scaling, Voltage scaling and Charge scaling D/A converters - Serial D/A converters - Serial A/D converters, Parallel - High performance A/D converters. (6)

LAYOUT ISSUES: CMOS design rules - layout of CMOS - BJT- Capacitors – Resistors - Mixed layout issues: Floor planning, power supply & ground, fully differential matching, Guard rings and shielding. (5)

Total 42REFERENCES:1. Randall L Geiger, Phillip E Allen and Noel R Strader, "VLSI Design Techniques for Analog and Digital Circuits",

McGraw Hill, International Edition, 1990. 2. Jose E Franca Hannis Tsividis, “Design of Analog - Digital VLSI Circuits for Telecommunication and Signal

Processing”, Prentice Hall, International Edition, 2002. 3. David A Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley and Sons, 2002. 4. Phillip Allen and Douglas Holberg, “CMOS Analog Circuit Design”, Oxford University Press, 2000.5. Benhard Razavi, “Data Converters”, Kluwer Publishers, 2000.6. Jacob Baker R, Lee H W and Boyce D E, “CMOS Circuit Design, Layout and Simulation”, Prentice Hall of India,

1998. 7. Mohammed Ismail and Terri Faiz, “Analog VLSI Signal and Information Process”, Mc-Graw Hill Book Company,

1994.8. Paul R Gray and Robert G Meyer “Analysis and Design of Analog Integrated Circuits”, John Wiley and

Son,2001.

09LV08 TESTING AND TESTABILITY3 0 0 3

INTRODUCTION: Motivation for testing and design for testability - Fault models (3)

COMBINATIONAL CIRCUIT TESTING: Test generation algorithms for combinational logic circuits - Fault Table, Boolean difference, Path sensitization, D - algorithm PODEM,FAN algorithms . (12)

SEQUENTIAL CIRCUIT TESTING: Functional testing –Fault model based testing- Time frame expansion. (5)

FAULT SIMULATION TECHNIQUES: Serial, Single-fault propagation, Deductive, Parallel and Concurrent Simulation. (3)

DESIGN FOR TESTABILITY: Key testability concepts – Ad Hoc design for Testability – scan based design - Signature analysis - Compression techniques-Built-in self-test -Architectures (9)

SPECIAL TESTING PROBLEMS: Memory testing techniques- Micro processor and Microcontrollers testing – Register decoding - Instruction decoding - data storage, transfer, manipulation functions - Testing analog components. Testability features for board test. FPGA testing. (10)

Total 42REFERENCES:1. Vishwani D Agarwal, “Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits”, Springer,

2000.2. Abramovici M, Breuer M A and Friedman A D, “Digital Systems Testing and Testable Design”, Wiley, 1994.3. Robert J Feugate and Jr Steven M, “Introduction to VLSI testing”, Prentice Hall, Englewood Cliffs, 1998.4. Parag K Lala, “Digital Circuit Testing and Testability”, Academic Press, 1997.

09LV09 HARDWARE DESIGN VERIFICATION TECHNIQUES3 0 0 3

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INTRODUCTION: - -Testing Versus Verification- Verification and Design Reuse. (2)

VERIFICATION TECHNIQUES AND TOOLS: Functional Verification, Timing Verification, Formal Verification. Linting Tools-Simulators-Third Party Models-Waveform Viewers-Code Coverage-Issue- Tracking Metrics. (8)

VERIFICATION PLAN: Verification plan-Levels of Verification-Verification Strategies–Specification Features – Test cases -Test Benches (8)

STIMULUS AND RESPONSE: Simple Stimulus- Output Verification –Self Checking Test Benches – Complex Stimulus and Response – Prediction of Output (8)

ARCHITECTING TESTBENCHES: Reusable Verification Components– VHDL and Verilog Implementation – Autonomous Generation and Monitoring – Input and Output Paths- Verifying Configurable Design. (8)

SYSTEM VERILOG: Data types, RTL design, Interfaces, clocking, Assertion based verification, classes, Test bench automation and constraints. (8)

Total 42REFERNCES1. Janick Bergeron, “Writing Test Benches Functional Verification of HDL Models”, Springer 2nd Edition, 2003.2. Andreas Meyer, “Principles of Functional Verification”, Newnes, 2003.3. Samir Palnitkar, “Design Verification with e”, Prentice Hall, 2003.4. Kropf T, “Introduction to Formal Hardware Verification”, Springer Verlag, 2000.5. Chris spear, “SystemVerilog for Verification: A Guide to Learning the Testbench Language Features”, Springer,

2006.6. Janick Bergeron, Edward Cerny, Alan Hunter and Andrew Nightingale, “Verification Methodology Manual for

System Verilog”, Springer, 2005.

09LV10 DESIGNING WITH CPLDS AND FPGAS3 0 0 3

COMBINATIONAL CIRCUITS: Shannon’s expansion theorem - Design using Multiplexers, Decoders - Design of static hazard free and dynamic hazard free logic circuits. (9)

SEQUENTIAL CIRCUITS: Mealy machine, Moore machine, Trivial / Reversible / Isomorphic sequential machines, State diagrams, State table minimization, Incompletely specified sequential machines, State assignments, Design of synchronous and asynchronous sequential logic circuits working in the fundamental mode and pulse mode, Essential hazards- Unger's theorem. (12)

PROGRAMMABLE LOGIC DEVICES: Basic concepts, Programming technologies, Programmable Logic Element (PLE), Programmable Logic Array (PLA), Programmable Array Logic (PAL), Design of state machine using Algorithmic State Machines (ASM) chart as a design tool. (9)

CPLDS AND FPGAS: Architectures of CPLDs and FPGAs.- Design of combinational and sequential circuits using CPLDs and FPGAs- Design examples. (12)

Total 42REFERENCES:1. Charles H Roth, “ Digital system Design with VHDL”, Thomson, 1998.2. James E Palmer and David E Perlman, “Introduction to Digital Systems ", Tata McGraw Hill, 1996.3. Robert Dueck, “Digital design with CPLD applications and VHDL”, Thomson, 2004.4. Bob Zeidman, “Designing with CPLDs and FPGAs”, CMP, 2002.5. Michael John Sebastian Smith, “Application Specific Integrated Circuits”, Addison-Wesley Professional, 1st

Edition, 1997.

09LV11 MIXED SIGNAL VLSI DESIGN 3 0 0 3

INTRODUCTION TO ACTIVE FILTERS & SWITCHED CAPACITOR FILTERS: Active RC Filters for monolithic filer design: First & Second order filter realizations - universal active filter (KHN) - self tuned filter - programmable filters - Switched capacitor filters: Switched capacitor resistors - amplifiers – comparators - sample & hold circuits – Integrator- Biquad (8)

CONTINUOUS TIME FILTERS & DIGITAL FILTERS: Introduction to Gm - C filters - bipolar transconductors - CMOS Transconductors using Triode transistors, active transistors - BiCMOS transconductors – MOSFET C Filters - Tuning Circuitry - Dynamic range performance - Digital Filters: Sampling – decimation – interpolation - implementation of FIR and IIR filters. (7)

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DIGITAL TO ANALOG & ANALOG TO DIGITAL CONVERTERS: Non-idealities in the DAC - Types of DAC’s: Current switched, Resistive, Charge redistribution (capacitive), Hybrid, segmented DAC’s - Techniques for improving linearity - Analog to Digital Converters: quantization errors - non-idealities - types of ADC’s: Flash, two step, pipelined, successive approximation, folding ADC’s. (10)

SIGMA DELTA CONVERTERS: Over sampled converters - over sampling with out noise & with noise - implementation imperfections - first order modulator - decimation filters - second order modulator - sigma delta DAC & ADC’s. (6)

ANALOG AND MIXED SIGNAL EXTENSIONS TO VHDL: Introduction - Language design objectives - Theory of differential algebraic equations - the 1076 .1 Language - Tolerance groups - Conservative systems - Time and the simulation cycle - A/D and D/A Interaction - Quiescent Point - Frequency domain modeling and examples. (6)

ANALOG EXTENSIONS TO VERILOG: Introduction - data types –Expressions – Signals- Analog behavior –Hierarchical Structures –Mixed signal Interaction. (5)

Total 42REFERENCES:1. David A Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley and Sons, 2002. 2. Rudy van de Plassche “Integrated Analog-to-Digital and Digital-to-Analog Converters”, Kluwer, 1999. 3. Antoniou, “Digital Filters Analysis and Design”, Tata McGraw Hill, 1998. 4. Phillip Allen and Douglas Holberg “CMOS Analog Circuit Design”, Oxford University Press, 2000. 5. Benhard Razavi, “Data Converters”, Kluwer Publishers, 1999. 6. JacobBake R, Harry W Li, and David E Boyce “CMOS, Circuit Design Layout and Simulation”, Wiley- IEEE Press,

1st Edition Aug, 1997. 7. Tsividis Y P, “Mixed Analog and Digital VLSI Devices and Technology”, Mc-Graw Hill, 1996.

09LV12 RF CIRCUIT DESIGN3 0 0 3

PASSIVE RF COMPONENTS AND TRANSMISSION LINE ANALYSIS: High frequency Resistors, Capacitor and Inductors – Transmission Line Analysis: Line equation, Micro strip line, Voltage Reflection Co-efficient, propagation constant phase velocity and special termination - Smith Chart-Impedance transformation - Analysis of parallel RL circuit and parallel RC circuit. (8)

SINGLE AND MULTI PORT NETWORK THEORY AND RF FILTER DESIGN: Definition - properties - interconnection of networks - ABCD parameters and S parameters - RF Filter Resonator and filter configuration - Butterworth and chebyshev filters. Design of micro strip filters. (8)

DESIGN OF MATCHING NETWORK: Matching by Discrete Components - Design of two-component matching network, Design of T and p matching network- Matching by micro strip line - Design of matching network - Design of stub matching.

(8)RF ACTIVE COMPONENTS, THEIR MODELING AND RF AMPLIFIER DESIGN: Components: RF Diode: PIN diode and Gunn Diode. RF Bipolar junction Transistor, RF field effect transistor - Modeling: Diode model, Transistor model, and FET model – RF Amplifier: Characteristics, power relations and Stability considerations. (9)

RF OSCILLATOR AND MIXER DESIGN: Basic oscillator model - Design of fixed frequency oscillator - Dielectric resonator oscillator - voltage controlled oscillator - gun element oscillator - Basic concepts - Design of single ended mixer- Double ended mixer. (9)

Total 42

REFERENCES:1. Reinhold Ludwig and Pavel Bretchko, “RF Circuit Design”, Pearson Education Asia Publication, 2001. 2. Matthew M Radmanesh, “Radio Frequency and Microwave Electronics Illustrated”, Pearson Education Asia Publication, 2001.3. Peter P Kenington, “High Linearity RF Amplifier Design”, Artech House, 20024. Razavi B, “RF Micro Electronics”, Prentice Hall PTR, 1998.5. Lee T H, “The Design of CMOS Radio Frequency Integerated Circuits”, Cambridge University Press, 1998.

09LV13 SEMICONDUCTOR MEMORY DESIGN AND TESTING3 0 0 3

RANDOM ACCESS MEMORY TECHNOLOGIES: Static Random Access Memories (SRAM): SRAM cell structures, MOS SRAM Architecture, MOS SRAM cell and peripheral Circuit Operation, Bipolar SRAM Technologies, Silicon on insulator

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(SOI) Technology. Advanced SRAM Architectures and Technologies, Application Specific SRAMs. Dynamic Random Access Memories (DRAM): DRAM Technology Development, CMOS DRAM, DRAM cell theory and advanced cell structures, BiCMOS DRAM, soft error failures in DRAM, Advanced DRAM Design and Architecture, Application Specific DRAM. (9)

NON-VOLATILE MEMORIES: Masked Read only Memories (ROM), High Density ROMs, Programmable ROM, Bipolar ROMs, CMOS PROMs, Erasable(UV) Programmable ROM(EPROM), Floating, Gate EPROM Cell, One time Programmable EPROM (OTPEPROM), Electrically Erasable PROMS, EEPROM Technology and Architecture, Non volatile SRAM, Flash Memories (EPROM or EEPROM), Advanced Flash Memory Architecture. (8)

MEMORY FAULT MODELLING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE: RAM Fault Modeling, Electrical Testing, Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing. Ram FAULT Modelling, BIST Techniques for Memory. (8)

SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS: General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification. Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures (9)

ADVANCED MEMORY TECHNOLOGIES AND HIGH-DENSITY MEMORY PACKAGING TECHNOLOGIES: Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories- Magnetoresistive Random Access Memories (MRAMs)-Experimental Memory Devices. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions. (8)

Total 42REFERENCES:1. Ashok K Sharma, “Semiconductor Memories Technology, Testing and Reliability”, Wiley, 2002.2. Ashok K Sharma, “Advanced Semiconductor Memories – Architecture, Design and Applications, Wiley, 2002.

09LV14 VLSI SIGNAL PROCESSING3 0 0 3

INTRODUCTION:An overview of DSP concepts-linear system theory,DFT,FFT,realization of digital filters.Typical DSP algorithms, DSP applications. Data flow graph representation of DSP algorithm. (7)

PIPELINING AND PARALLEL PROCESSING: Introduction - Pipelining of FIR Digital filters - Parallel processing - Pipelining and parallel processing for Low power. (8)

TRANSFORMATIONS-RETIMING: Introduction - Definitions and Properties - Solving system of Inequalities - Retiming Techniques. UNFOLDING: Introduction - An algorithm for unfolding - Properties of unfolding - Critical path, unfolding and retiming - Application of unfolding.FOLDING: Introduction - folding Transformation - Register Minimization Techniques - Register Minimization in folded Architectures (12)

FAST CONVOLUTION: Introduction - Cook - Toom algorithm –modified Cook - Toom algorithm Winogard algorithm- modified Winogard algorithm, Algorithmic strength reduction in filters and transforms-DCT and inverse DCT-parallel FIR filters (7)

POWER ANALYSIS:Scaling versus power consumption-power analysis-power reduction techniques-power estimation techniques-low power IIR filter design-Low power CMOS lattice IIR filter (8)

Total 42REFERENCES:1. Keshab K Parhi, “VLSI Digital Signal Processing Systems Design and Implementation”, Wiley - Inter

science, 1998. 2. Kung S Y, While house H J and Kailath T, “VLSI and Modern Signal Processing”, Prentice Hall, 1985.3. Jose E France and Yannis Tsividis “Design of Analog - Digital VLSI Circuits for Telecommunications and

Signal Processing”, - Prentice Hall, 1994.4. Madisetti V K, “VLSI Digital Signal Processing”, IEEE Press (NY), USA 1995.

09LV15 VLSI TECHNOLOGY3 0 0 3

MATERIAL PROPERTIES & CRYSTAL GROWTH: Crystal structure- axes & planes, Crystal defects-Point defects & dislocations Crystal growth- Bridgman, Czochralski techniques & Zone process, Doping in the melt. (7)

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DIFFUSION & ION IMPLANTATION: Nature of diffusion-interstitial, Substitutional, interstitial substitutional movements, Diffusion constant, Dissociate process, Diffusion equation- D is constant & function, Diffusion systems, problems in Si Diffusion, Evaluation Techniques Ion Implantation: Penetration range, Implantation Damage, Annealing, Implantation Systems (10)

OXIDATION & EPITAXYOXIDATION: Thermal Oxidation-Intrinsic, Extrinsic silicon Glass, Oxide formation, Kinetics of Oxide growth, Oxidation systems, Faults, Anodic OxidationEPITAXY: Vapour Phase Epitaxy (VPE)- transport, reaction and growth, Chemistry of growth, Insitu etching, Selective epitaxy, imperfections, Liquid Phase Epitaxy, LPE system, Evaluation of epitaxial layers (8)

ETCHING & LITHOGRAPHY:LITHOGRAPHY: Pattern generation & Masking, Printing & Engraving-Optical, E-Beam, ion Beam, X-Ray, Photoresists, DefectsETCHING: Wet chemical etching- anisotropic etchants, Etching for non-crystalline films-Plasma etching, Plasma-assisted etching, Cleaning (9)

DEVICE & CIRCUIT FABRICATION: Isolation- Mesa, Oxide, PN-junction isolations, Self Allignment, Local Oxidation, Planarisation, Metallisation and Packaging. Circuits – N, P and CMOS Transistors, Memory devices, BJT Circuits – Buried Layer, PNP and NPN Transistors, Diodes, Resistors, Capacitors. (8)

Total 42REFERENCES:1. Sorab K Gandhi “VLSI Fabrication Principles – Silicon and Gallium Arsenide”, Wiley Interscience Publications,

New York 1983. 2. Sze S M “VLSI Technology”, McGraw Hill, New York, 1983.3. Chang S Y and Sze S M, “ULSI Technology”, McGraw Hill, New York, 1996.4. Groove A S, “Physics and Technology of Semiconductor Devices”, Wiley Interscience Publications, New York,

1983.5. Sze S M, “Physics of Semiconductor Devices”, 2nd Edition McGraw Hill, New York, 1981.

09LV16 NANO ELECTRONICS 3 0 0 3

TECHNOLOGY AND ANALYSIS: Film Deposition Methods – Lithography – Material removing techniques – Etching and Chemical – Mechanical Polishing – Scanning Probe Techniques. (8)

CARBON NANO STRUCTURES: Carbon Clusters – Carbon Nano tubes – Fabrication – Electrical, Mechanical and Vibrational Properties- Applications of Carbon Nano tubes (6)

LOGIC DEVICES: Silicon MOSFET’s – Novel materials and alternative concepts - Ferroelectric Field Effect Transistors – Super conductor digital electronics – Carbon Nano tubes for data processing. (10)

RANDOM ACCESS MEMORIES AND MASS STORAGE DEVICES: High Permitivity materials for DRAM’s – Ferro electric Random Access Memories - Magneto-resistive RAM. Hard Disk Drives – Magneto Optical Disks – Rewriteable DVDs based on Phase Change Materials – Holographic Data Storage (11)

DATA TRANSMISSION AND INTERFACES AND DISPLAYS: Photonic Networks – Microwave Communication Systems. Liquid Crystal Displays – Organic Light emitting diodes. (7)

Total 42

REFERENCES:1. Rainer Waser, “Nano Electronics and Information Technology”, Wiley VCH, April 2003. 2. Charles Poole, “Introduction to NanoTechnology”, Wiley Interscience, May 2003.

09LV17 MICROSENSORS AND MEMS 3 0 0 3

OVERVIEW OF MICRO SENSORS AND MEMS: Introduction –MEMS and micro system products- Microsystems and Micoelectronics -Applications of micro systems in Automotive industry and in other industries (6)

MATERIALS FOR MEMS AND MICRO SENSORS: Silicon-silicon compounds-silicon piezo resistors-gallium arsenide-quartz-piezoelectric crystals-polymers-packaging materials (12)

MICROSYSTEM DESIGN: Design considerations-design constraints-selection of materials-manufacturing process, signal transduction-packaging- process design-photolithography, Thin film fabrications ,geometry shaping - mechanical design-design of silicon die for micropressure sensor (12)

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MICRO SENSORS: Introduction- microsensors- biomedical sensors-pressure sensors-thermal sensors-chemical sensors-moptical sensors-microactuation –mems with micro actuators (12)

Total 42

REFERENCES:1. Tai-Ran Hsu, “MEMS and Microsystems Design and Manufacture”, Tata McGraw-Hill, 2002.2. John A Pelesko, “Modelling MEMs and NEMS”, CRC press, 2002.

09LV18 EMBEDDED SYSTEMS3 0 0 3

IINTRODUCTION: Building Blocks of an embedded system - Overview of dedicated and automated systems and their requirements Characteristics of embedded computer applications– The product design cycle – Design challenges in embedded system Design- Design Technology (5)

PERIPHERALS: Timers, Counter and Watch dog Timer – UART – Pulse Width Modulator – LCD Controllers – Key Pad Controllers – Stepper Motor Controllers – Analog to Digital Converters (6)

MEMORY AND I/O INTERFACING: Memory Types – ROM –EPROM – EEPROM – Flash Memory - RAM – SRAM - RAM – Cache Memory – Memory Management Unit - Interrupts – DMA – Serial Protocols - I2 C – CAN – USB – Parallel Protocols – PCI Bus – ARM Bus (9)

EMBEDDED MICROCOMPUTER SYSTEMS: Motorola 68HC11 Family Architecture, Registers, Addressing modes, Programs – Interfacing methods – Parallel I/O, Parallel port interfaces, High Speed I/O interfacing – Interrupt – Interrupt Service Routine – Timing generation and Measurements – Input Capture and Output Compare- Frequency Measurements – Serial I/O devices – RS 232, RS 485, Analog Interfacing – Applications . (12)

REAL TIME OPERATING SYSTEMS: Tasks and Task States – Tasks and data – Semaphores and shared Data Operating System services – Message queues – Timer functions – Events – Memory Management, Interrupt Routines in an RTOS environment, Basic Design using RTOS – RTOS scalability and tool support – Multiple task and Multiple processes – Content Switching- Compiler Selection – Overview of loading software into remote targets.

(10)

Total 42REFERENCES:

1. Frank Vahid and Tony Givargis, “Embedded System Design: A unified Hardware / Software Introduction”, John Wiley and sons, 2002.

2. Arnold Berger, “Embedded System Design: An Introduction to Processes, Tools & Techniques”, CMP Books, Dec 2001.

3. RajKamal, “Embedded System-Architecture, Programming, Design”, Tata McGraw Hill, New Delhi, 2003.4. David E Simon, “An Embedded Software Primer”, Addison Wesley, 1999.5. Steve Heath, “Embedded Systems Design”, Butterworth – Heinemann, Nov 1997.6. Wayne Wolf, "Computers as Components: Principles of Embedded Computer Systems Design”, Morgan–

Kaufmann, Sep 2000.7. Valvino J W, “Embedded micro computer system: Real time Interfacing”, Brooks/ cole, 2000.8. Muhammad Ali Mazidi, “The 8051 MC and Embedded system”, Pearson Edition, 2000.

09LV19 SYSTEM ON CHIP 3 0 0 3

INTRODUCTION TO PROCESSOR DESIGN: Abstraction in hardware design- MUO – a simple processor – Processor Design trade off- Design for low power consumption. (3)

ARM ARCHITECTURE: Acorn RISC Machine – Architecture Inheritance – ARM Programming Model- ARM Development Tools – 3 and 5 Stage Pipeline ARM Organization - ARM Instruction Execution and Implementation – ARM Co-Processor Interface. (6)

ARM ASEEMBLY LANGUAGE PROGRAMMING: ARM Instruction Types – Data Transfer, Data Processing and Control Flow Instructions - ARM Instruction Set – Co-Processor Instructions. (8)

ARCHITECTURAL SUPPORT FOR HIGH LEVEL LANGAUGE: Data Types – Abstraction in software Design – Expressions – Loops – Functions and Procedures – Conditional Statements – Use of Memory. (6)

MEMORY HIERARCHY: Memory Size and Speed – On Chip Memory – Caches – Cache Design – an Example- Memory management. (3)

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ARCHITECTURAL SUPPORT FOR SYSTEM DEVELOPMENT: Advanced Microcontroller Bus Architecture – ARM Memory Interface – ARM Reference Peripheral Specification – Hardware System Prototyping Tools – Armulator – Debug Architecture. (8)

ARCHITECTURAL SUPPORT FOR OPERTAING SYSTEM: An Introduction to Operating Systems – ARM System Control Coprocessor- CP15 Protection Unit Registers – ARM Protection Unit – CP15 MMU Registers – ARM MMU Architecture – Synchronization –Context Switching Input and Output. (8)

Total 42REFERENCES:1. Steve Furber, “ARM System on Chip Architecture”, Addison- Wesley Professional, 2nd Edition, Aug 2000. 2. Ricardo Reis “Design of System on a Chip: Devices and Components” Springer, 1st Edition, July 2004.3. Jason Andrews “Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded

Technology)” Newnes, BK and CD-ROM (Aug 2004).4. Rashinkar P, Paterson and Singh L, “System on a Chip Verification – Methodologies and Techniques”, Kluwer

Academic Publishers, 2001.

09LV20 ADVANCED COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

3 0 0 3

INTRODUCTION TO PARALLEL PROCESSING: - Evolution of computer systems. Generation of computer systems – Trends towards parallel processing- Parallel processing mechanisms- parallel computer structure- Architectural classification schemes – Application. (6)

MEMORY AND I/O SUBSYSTEMS: Hierarchical Memory structure – Virtual memory system - cache memory management- Memory allocation and management – I/O subsystems (5)

PIPELINING: Principles - Classification of pipeline processors - Reservation tables – Interleaved memory organization – Design of arithmetic pipeline – Design of instruction pipeline (5)

VECTOR PROCESSING: Need – Basic vector processing architecture - Issues in vector processing – Vectorization and optimization methods. (6)ARRAY PROCESSING: SIMD Array processors – SIMD interconnection networks – Parallel algorithms for array processors – associative array processing. (6)

MULTIPROCESSOR ARCHITECTURE: Functional structures - Interconnection network – Multi cache problems and solutions – Exploiting concurrency for multiprocessing. (7)

PRINCIPLES OF PARALLEL ALGORITHM DESIGN: Design approaches-Design issues-Performance measures and analysis-Complexities-Anomalies in parallel algorithms - Pseudo code conventions for parallel algorithms-Comparison of SIMD and MIMD algorithms. (7)

Total 42REFERENCES:1. Kai Hwang, “Advanced Computer Architecture: Parallelism, Scalability and Programmability”, Tata McGraw Hill,

1992. 2. Seyed Roosta “Parallel Processing and Parallel Algorithms”, Springer Series, 1999.3. John L Hennessy “Computer Architecture a Quantitative Approach”,Harcourt Asia Pvt. Ltd., 1999.4. John L Hennessy and David A Patterson “Computer Architecture a Quantitative Approach”, Morgan Kaufmann,

4th edition, 2006.

09LV21 VLSI FOR WIRELESS COMMUNICATION3 0 0 3

OVERVIEW OF MODULATION SCHEMES: Classical Channel - Wireless Channel Description - Path Loss - Channel Model and Envelope Fading - Multipath Fading: Frequency Selective and Fast Fading - Summary of Standard Translation.

(5)

RECEIVER FRONT END: Filter Design - Rest of Receiver Front End: Non idealities and Design Parameters - Nonlinearity –Noise - Derivation of Noise Figure. (5)

AMPLIFIER DESIGN: Low Noise Amplifier Design - Wideband LNA - Design Narrowband LNA - Impedance Matching - Automatic Gain Control Amplifiers – Power Amplifiers (7)

MIXERS: Balancing Mixer - Qualitative Description of the Gilbert Mixer - Conversion Gain – Distortion - Low Frequency Case: Analysis of Gilbert Mixer – Distortion - High-Frequency Case – Noise - A Complete Active Mixer. Switching Mixer - Distortion in Unbalanced Switching Mixer - Conversion Gain in Unbalanced Switching Mixer - Noise in Unbalanced Switching Mixer - A Practical Unbalanced Switching Mixer. Sampling Mixer - Conversion Gain in Single Ended Sampling

207

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Mixer - Distortion in Single Ended Sampling Mixer - Intrinsic Noise in Single Ended Sampling Mixer - Extrinsic Noise in Single Ended Sampling Mixer- Demodulators. (12)

FREQUENCY SYNTHESIZERS: Phase Locked Loops - Voltage Controlled Oscillators - Phase Detector – Analog Phase Detectors – Digital Phase Detectors - Frequency Dividers - LC Oscillators - Ring Oscillators - Phase Noise - A Complete Synthesizer Design Example (DECT Application). (8)

LOOP FILTER: General Description - Design Approaches. (5)

Total 42REFERENCES:1. Bosco H Leung “VLSI for Wireless Communication”, Pearson Education, 2002.2. Emad N Farag and Mohamed I Elmasry, “Mixed Signal VLSI Wireless Design - Circuits and Systems”, Kluwer

Academic Publishers, 2000.

09LV22/09LC04 ADVANCED DIGITAL SIGNAL PROCESSING3 0 0 3

MULTIRATE SIGNAL PROCESSING: Introduction - Sampling and Signal Reconstruction - Sampling rate conversion - Decimation by an integer factor - Interpolation by an integer factor - Sampling rate conversion by a rational factor - Sampling rate converter as a time variant system - Practical structures for decimators and interpolators - Direct form and Polyphase FIR structures - FIR structures with time varying Coefficients. (12)

MULTIRATE FIR FILTER DESIGN: Design of FIR filters for sampling rate conversion - Multistage design of decimator and interpolator - Applications of Interpolation and decimation in signal processing - Filter bank implementation - Two channel filter banks - QMF filter banks - Perfect Reconstruction Filter banks - Filter banks with tree structure - DFT filter Banks - Octave Filter Banks. (10)

POWER SPECTRAL ESTIMATION: Estimation of spectra from finite duration observations of a signal - The Periodogram - Use of DFT in Power spectral Estimation - Non-Parametric methods for Power spectrum Estimation - Bartlett, Wech & Blackman - Tukey methods - Comparison of performance of Non - Parametric power spectrum Estimation methods. (10)

PARAMETRIC METHODS OF POWER SPECTRUM ESTIMATION: Parametric methods for Power spectrum Estimation - Relationship between auto correlation and model parameters - AR (Auto - Regressive ) process and Linear prediction - Yule-Walker, Burg & Unconstrained Least squares methods - Moving Average (MA) and ARMA models - Minimum variance method - Pisarenko's harmonic De composition Method. - MUSIC method. (10)

Total 42REFERENCES:1. Fliege N J, “Multirate Digital Signal Processing”, John Wiley and sons, 1994.2. Hayes M H, “Statistical Digital Signal Processing and Modeling”, Wiley, New York, 1996.3. Sanjit.K Mitra, “Digital Signal Processing-A Computer Based Approach”, Tata McGraw Hill, 2003.4. Proakis J G and Manolakis D G, “Digital Signal Processing Principles, Algorithms and Applications”, Prentice-Hall of

India, 2002.5. Manolakis D G, Ingle V K and Kogon S M, “Statistical and Adaptive Signal Processing”, McGraw – Hill, Singapore,

2000.6. Vaidyanathan P P, “Multirate Systems and Filter banks”, Prentice Hall, 1993.

09LV23 RELIABILITY ENGINEERING

3 0 0 3

HISTORY OF RELIABILITY: Factors influencing system effectiveness - Various definitions of reliability - Operational readiness, availability, maintainability, serviceability - Concepts of reliability - Modes of failure - Measures of reliability. (5)

MATHEMATICAL CONCEPTS OF RELIABILITY: Probability functions - Elements of probability theory - Permutations - Probability statistics - Reliability density functions - Moments - Specific functions in developing failure pattern model. (5)

RELIABILITY AND HAZARD FUNCTION FOR KNOWN DISTRIBUTION: Exponential distribution - Normal distribution - Log Normal distribution, Weibull - Distribution and Gamma distribution. (5)

RELIABILITY DATA ANALYSIS: Data collection and reliability analysis - Computation of mean and variance - Survival curves - Computation of reliability functions - Confidence bounds - Application of Weibull distribution - Reliability allocation and basic allocation. (5)

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SYSTEM RELIABILITY MODELLING: Series and parallel system, time dependent situation and series parallel system - Partial redundancy - Redundancy effectiveness for simple method - Open and short circuit failures - Redundancy involving switching - Standby redundancy (6)

RELIABILITY PREDICTION: Monte Carlo method - Random observation from probability distribution - Application of Monte Carlo method - Final design prediction procedure - Development of Reliability formula (6)

MAINTAINABILITY AND AVAILABILITY: Objectives and forms of maintainability - Measures of maintainability - Availability - Intrinsic availability - Equipment availability. (5)

RELIABILITY PHYSICS MODELS: Stress strength models - Accelerated testing - Interpretation of life test data - Human reliability engineering (5)

Total 42REFERENCES:1. Von Alven, W H, “Reliability Engineering”, Prentice Hall Inc., New Jersey, 1964.2. Govil, A K, “Reliability Engineering”, Tata McGraw Hill Book Company, 1983.3. Kapur K C and Lamberson L R, “Reliability in Engineering Design”, John Wiley and Sons, New York, 1977.

09LV24 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY 3 0 0 3

EMI ENVIRONMENT: Sources of EMI, conducted and radiated EMI, Transient EMI, EMI-EMI-EMC Definitions and units of parameters, Radiation hazards to human beings. (6)

EMI COUPLING PRINCIPLES: Conducted, radiated and transient coupling, Common impedance ground coupling, Radiated common mode and ground loop coupling, radiated differential mode coupling, near field cable to cable coupling, power main and power supply coupling. (8)

EMI SPECIFICATIONS/STANDARDS/LIMITS: Units and specifications of EMI, National and International EMI standardizing organisations - Civilian standards & Military standards. (7)

EMI MEASUREMENTS: EMI test instrument/systems, EMI test, EMI shielded chamber, Open area test site, TEM cell antennas, conducted sensors/injectors/couplers, military Test method and procedures, Calibration procedures. (8)

EMI CONTROL TECHNIQUES: Shielding, Filtering, grounding, bonding, Isolation transformer, Transient suppressors, Cable routing, signal control, Component selection and mounting. (8)

EMC DESIGN OF PCBS: PCB traces, Crosstalk, Impedance control, Power distribution decoupling, Zoning, Motherboard Designs, Propagation delay performance models. (5)

Total 42

REFERENCES:1. Clayton R Paul, “Introduction to Electromagnetic Compatibility”, John Wiley & Sons, 1992. 2. Bernard Keiser, “Principles of Electromagnetic Compatibility”, Artech House, 3rd Edition, 1994.3. Henry W Ott, “Noise Reduction Techniques in Electronics in electronic Systems”, A Wiley -Interscience

Publication, John Wiley and sons, 1988.4. Kodali V P, “Engineering EMC Principles, Measurements and Technologies” IEEE Press, 1996.

09LV41 INDUSTRIAL VISIT AND TECHNICAL SEMINAR1 0 2 2

The student will make atleast two technical presentations on current topics related to the specialization. The same will be assessed by a committee appointed by the department. The students are expected to submit a report at the end of the semester covering the various aspects of his/her presentation together with the observation in industry visits. A quiz covering the above will be held at the end of the semester.

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09LV51 VLSI DESIGN LABORATORY 0 0 3 3

1. Design of static and dynamic digital circuits2. IC layout design using L-Edit3. Design of combinational and sequential circuits using VHDL. 4. Design of combinational and sequential circuits using Verilog. 5. Writing Test benches in VHDL / Verilog 6. Design Implementation using FPGA boards

09LV52 ADVANCED VLSI DESIGN LABORATORY-I 0 0 3 3

1. Design and Simulation of analog circuits using synopsis EDA tool (CosmosSE)2. Design and Simulation of analog circuits using Cadence EDA tool (Virtuoso and spectre)3. Timing and power analysis for analog circuit design using Synopsys EDA tool(Prime Time and Prime power)4. Generation of synthesis report using Mentor Graphics EDA tool (Leonardo spectrum)

09LV53 ADVANCED VLSI DESIGN LABORATORY-II 0 0 3 3

1. Design,Implementation,layout generation and verification of an analog building block using a EDA tool (Synopsys, Cadence,Mentor graphics)

2. Design,Implementation,layout generation and verification of an digital building block using a EDA tool (Synopsys, Cadence,Mentor graphics)

210


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