Development of 3.3V Flash ZE~PROM Cell and
k a y
b~ Jeewika Ranaweera
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy
Department of Electrical and Cornputer Engineering University of Toronto
1999
O Copyright by Jeewika Ranaweera 1999
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Development of 3.3V Flash zE'PROM Ceii and Array
Doctor of Philosophy, 1998
Jeewika Ranaweera Department of Electrîcal and Computer Engineering
University of Toronto
Abstract
Most of the conventional flash E~PROM ceIls have major limitations for Iow voltage
applications and s&er from slow programming speeds. This thesis descn i s a Zener based
MOS flash memory c d (ZE~PROM), programmed by hot electrons generated by a heavily
doped reverse biased p+n+ junction attached to the drain. The Zener based programming
rnethod provides a practical solution to some of the limitations of conventional channel hot
electron programming method. This celi operates with a single supply of 3.3V and achieves
an order of magnitude reduction of programming time compared to conventional flash
memory ceils. The reduced Zener breakdown current also enables many bits to be
programmed simultaneously. The ceil can be irnplemented in a NOR type mernory array. It
uses an orthogonal write technique to achieve fast programming with low power dissipation
and reduced drain disturbance. The modeling of the charge transfer behavior of the
ZE*PROM cell is investigated using 2-D device simulations to specify the charging and
discharging of the floating gate during programming and erasing.
Experimental ZE~PROM arrays were implemented in a 0.8pm iithography CMOS
process fiow in which the n- LDD step was replaced with a one sided p+ boron implant with
a doping level of -10~~crn-~ . This minor change to a standard CMOS process, makes the
concept highly attractive for embedded memory applications. A programming time of
850ns at 3.3V supply was achieved on fabricated test devices.
1 would Like to express my sincere gratitude to Professor C.A.T. Saiama and to
Professor W.T. Ng for their insightful guidance and invaluable assistance throughout the
course of this work.
1 am ais0 indebted to Mehran Aliabad for the countless hours of valuable discussion
both technically and personally. Special thanks to Elvira Guiersen and Ivan Kaiastrisky for
many helpfd suggestions.
My sincere thanks to Alberto Dibu-Caiole for his assistance in developing the ON0
layers. My appreciation extends to ail the staff and students in the Mîcroe1ectronic
Research Laboratory including Jaro Pristupa, Dana Reem, Anthoula Kampouris, Dod
Chettiar, Li Zhang Hou, Hormoz Djahanshahi, Sbahla Honarkhah, Dusan Suvakovic,
Mehrdad Ramezani, Sameh KhaIil and Diana Gradinam for a l l their help.
A special word of thanks to my husband Senaka who has been a constant source of
support and encouragement. And to my son Mano, for king the best baby a mother could
have.
Financial support provided by the Naturd Sciences and Engineering Research
Councii of Canada, Nortel, Gennum, Mitel and Micronet are gratefuliy acknowLedged.
Table of Contents
CHAPTER 1
h t ï d ~ ~ t i ~ ~ . ~ . ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ . ~ ~ ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ - ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ ~ . ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ - - ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ l 2 1.1 Flash E PROM Development ............. .... ................................................ 1
2 ..................................... 1.2 Basic Operating Principle of a flash E PROM ce ll 4
1.2.1 Basic Programming Mechanism ........ .. . . . . . . . . . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ . . . ~ ~ ~ ~ ~ ~ . 6
........................................................... 1.2.2 Basic Erasing Mechanism .... 8
1.3 Array Architectures ..................................................................................... 9
.............................. 1.3.1 NOR Type Array Architecture ................ ....,... 10
1 .3.2 NAND Type Array Architecture ............................................. 11
1.3.3 V i a 1 Ground Array Architecture .............. ..... .......................... 12 1.4 Reliability of flash E'PROM ............................................................... 13
1.4.1 Drain Disturb .................................. ..,, 14 1.4.2 DC Program ............................................................................... 15
1.4.3 DC Erase .................. .-.. ...................~......................................... 16
.................................................................................. 1.4.4 Read Disturb 16 2 .................................... 1 -5 Limitations of Conventional flash E PROM Cells 16
................................................................ 1.6 Objective and Outline of Thesis 17
CHAPTXR 2 2 .............................................. The 33V ZE PROM Ce1 and A m y ArcKhchire 0 0 0 0 ~ ~ 0 ~ ~ 2
Introduction ............................................................................................... 22
. ....................---... Celi Structure and Operations ................... .. ..... 23
2.2.1 Programming ............................................................................... 2 4
2.2.2 Erasing .......................................................................................... 25
2-23 Reading .......................................................................................... 25
Analyticai Mode1 of the ZE~PROM Celi .............................................. 2 6
2.3.1 The Capacitor Mode1 ....................................................... .. 26
2.3.2 1-V Characteristics ....................................... - ............ 28 2D Device Simulations .............................................................................. 31
2.4.1 Programming .............................................................................. 32
iii
2.4.2 Erashg .............................................................................. 3 8
2.4.3 Reading .......................................................................................... 41
2.4.4 Summary of Device Simulations ................................................... 41 2.5 Array Architecture and Orthogonal Programming ........... ............. 42
......................................................................... 2.5.1 Drain Disturb 4 4
.................................................................................. 2-52 GateDisturb 45
2.6 Sumrnary ................................................. ...- C&APTER 3
...... Fabrication and ChpraeterizPtioo of the ~ P R O M CeM and Array ................... 48
............................................................................................... Introduction 48
............................................................................................. Process Fiow -49
3 .2.1 Process Specifications ................................................................... 49
3.2.2 Process Flow ................................. ,,. .............. .. . 50
Process Simulation ResuIts ............................................. d
Expenmental Development of Critical Process Steps .................. ...... 64
3 .4.1 Thin Gate Oxide ............................................................................ 64
3.4.2 ON0 Interpoly Dielectric .............................................................. 69
.....-............... ......................... 3.4.3 The p+nf Zener Junction .. 7 4
Layout Mes .............................................................................................. 76
........................................................................... Process Characterization 8 0
............... Characterization of the Implemented ZE~PROM cell and array 85
......................................................................... 3.7.1 Programunhg 8 5
3.7.2 Erasing .......................................................................................... 86
....................................................... 3.7.3 Program and erase uniformity 87
............................................................. ................. 3 .7.4 Reading ... 89
.................................................................. 3 .7.5 Disturb Characteristics 90
3 .7.6 Endurance Characteristics ........................................................ 96 2 Integrating the ZE PROM array in a full process ........................... .. ..... 97
Scaling of the Ceil ................................................................................... 101
Summary ................................................................................................. 102
........................................................................ A . f Fabrication Rocess Flow 109
APPENDIX B The h Based Layout Design Rules . m ~ œ œ œ œ œ ~ œ œ œ œ œ œ ~ œ ~ m œ ~ ~ m m œ m œ c m m m œ m œ œ m m œ œ œ œ œ œ œ œ œ œ œ œ m m œ œ l2û
............................................................. B.1 Active are= (Mask#L. LOCOS) 120
B . 2 Fioating gate poly: (Mask #2, FGPOLY) .............................................. 121
B.3 Control gate poly: (Mask #3, CGPOLY) ................................................. 121
............... B.4 P+ Zener region and substrate contacts: (Mask #4, PZENER) 122
B -5 Source and drain diffusion: (Mask #5, NDEV) ................................... 122
................................................................. B . 6 Contacts: (Mask #6, CON) 1 2 3
B . 7 Metal layer: (Mask #7, METZ) ................................................................ 123
List of Figures
CHAPTER 1
Figure 1 . 1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Figure 1.6
Figure 1.7
Figure 1.8
Figure 1.9
Figure 1.10
Figure 1.1 1
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
DifFerent non-volatile memory cells ........................................................... 2
The storage of charge in the floating gate of the ceU .................................. 4
The influence of charge in the floating gate on the threshold voltage of the
ce11 .............................................................................................................. 5 2 ..................................................................... Flash E PROM programming 6
Energy band representation of hot electron injection on to the floating gate
..................................................................................................................... 7
.................................................... Erasing condition of a flash memory celi 8
Energy band diagram representing the F-N tunnelhg of electrons fiom the
floating gate to the source region ................................................... ... 9
...................... Schematic diagram of a NOR-type flash E~PROM array ... 10
...................... Sc hematic diagram of a NAND- type Bas h E~PROM array 11
............... Schematic diagram of a V i a 1 Ground flash E~PROM array ... 12
The disturb conditions experienced in a NOR type flash E~PROM array 15
2 The proposed ZE PROM ce11 structure ..................................................... 23 2 ........................... ...................... Programming of the ZE PROM ceil ,.. 24
Erasing of the ZE~PROM cell .................~....~~~~~..~.~~~.~~~~~.............~......~~..~~ 2 5
Reading of the Z~PROM ce ll ................................................................. 26
......................... The equivalent capacitance mode1 of the Z~PROM ceH 27
The surface vie* of the ZE~PROM cell ......................................... .. 29
The cross sections of (a) ZE~PROM ceii and (b) conventionai flash
memory cell, showing the dimensions used for numerical simulations .... 33
Floating gate voltage vs . programming t h e of cells A and B .................. 34
Floating gate voltage versus floating gate charge of cells A and B ........... 35
Figure 2.10
Figure 2.1 1
Figure 2.12
Figure 2.1 3
Figure 2.14
Figure 2.15
Figure 2-16
Figure 2.17
Figure 2.18
Figure 2.19
Figure 2.20
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3 -8
Figure 3.9
(a) Hot electron current and (b) floating gate charge during programming
of ceils A and B ........................................................ .......................... 36
Drain current during programming of cells A and B ................................ 37
Electron Injection efficiency during programming .................................... 38 2 Floating gate voltage during erasing of a ZE PROM ceL ........................ 39
Floating gate voltage versus Boating gate charge during erasing of a 2 ........................................................................................... ZE PROM ceU 39
F-N tumehg current during erasing of a E~PROM ce11 ..................... 40
FIoating gate charge during erasing of a ZE*PROM cell .......................... 40 2 Read current in a ZE PROM ceU ...................................... ................... 4 1
The ZE*PROM implemented in a NOR type array architecture ............... 42
Orthogonal prograrnming (cells P and R) of the Z~PROM array (h is
................................................. flowing in all the celis connected to B U ) 43
Drain disturb, by hot hole injection, in the unselected cells of the array
(cell Q). while ceiis P and R are king programmed ........................ .... ..44
Cross-sectional diagram of the proposed ZE'PROM ce11 ......................... 50
2 Cross-sectional diagrams of the ZE PROM process ................................ 56
Doping profile of the gate structure and the b u k region . The coordinate
............................. y=.0.58 mm corresponds to the top of the control gate 61
Doping pronles dong the nf drain of the Zener Junction . The coordinate
y4mm corresponds to the silicon surface ................................................ 62
Doping profiles dong the p+ region of the Zener junction . The coorduiate
y=0mm corresponds to the silicon surface ................................................ 62
Doping profile of the Zener Junction in lateral direction at 100A from the
silicon surface . The coordinate x = û p corresponds to the edge of the
channel at the source side .......................................................................... 63
Experirnental HF C-V characteristics for the 85A thin gate oxide ........... 66
Breakdown distribution obtained from 50 capacitors on a wafer .............. 68
The ON0 intcrpoly dielectric composition ..................................... .......... 70
Figure 3.10 The energy band structure of the ON0 dielectric .......................... ..........- 7 1
Figure 3.1 1 Leakage current vs. control gate voltage in ON0 and oxide test structure73
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16
Figure 3.17
Figure 3.18
Figure 3.19
Figure 3.20
Figure 3.2 1
Figure 3.22
Figure 3.23
Figure 3.24
Figure 3.25
Figure 3.26
Figure 3.27
Figure 3.28
Figure 3 -29
Figure 3.30
Cntical breakdown voltage vs. the number of oxide and ON0 dielectric
capacitor samples .-......-.............*.... .-......., . . . . . . ................. 74 + + Experimental breakdown characteristics of the p n junction .................. 75
2 Layout design d e s for a 0 . 8 ~ ZE PROM cell .... .................................. 77
Test masks layout used in the fabrication process ...................*.........-.. 79
Micrograph of the test mask (area 6000pmx6100p) ........................ 8 1
2 Micrograph of a 2E PROM ceiI ...... .-..... ............................................ 82 2 Micrograph of a ZE PROM array ............................ ..... ....... ................82
SEM micrograph of ceii cross section across the width of the device ...... 83
Threshold voltage vs. progranunhg tune of a Z~PROM ceU ................. 86 2 Threshold voltage vs. erase time of a ZE PROM ceil .... ........................... 87
Programmed and virgin V, disaibution for a 8x8 Z~PROM array .......... 88
Read current vs. source voltage as a function of control gaie voltage ...... 89
Read current vs. source voltage as a function of the p+ diffusion width... 90
Drain and gate disturb conditions in the unselected celis (Q, S, T, U and 2 V) of a ZE PROM m y ...... ..............- . --...--................................. . . 9 1
ThreshoId voltage as a function of stress time to illustrate drain disturb
characterïstics, due to the p+nf junction, in unselected programmed and 2 erased ZE PROM ceils ..-- ...... . . . . .. . . . . . .+. .. . . .. .. -. - -.m.-. . . - . . . . . . . . . . . . . . . . 9 2
Threshold voltage as a function of stress time to demonstrate the gate
disturb (undesired programming and erasing) of the unselected erased and
programmed ZE*PROM ceils that share a common word line ................. 93
Safi wrïte time (time to cause a V, shift of 0.W) vs. the inverse of source
voltage applied during reading of a ZE~PROM cell at two different
temperatures ..........,...... ..-.-.-....-.-...... - . . .......... ............................... 95
Threshold voltage vs. writelerase cycles to v e m the endurance 2 c haracteristics of the ZE PROM cell ......-. .,..... ..... . ..... ...... .... . ... ..... ........... 97
Process flow of a modified CMOS process in which the additional 2 ZE PROM steps are identified (shaded) ........... . ..-- -.--.....-. -................ 98
Figure 3.3 1 Simulated and experimental programming time as a function of the gate
....................................... length for different flash ZE*PROM ceiis 102
Figure A- 1
Figure A.2
Figure A.3
Figure A.4
Figure AS
Figure A.6
Figure A.7
Figure A.8
Figure A.9
Figure A . 10
Cross-section after dry etching the nitride ......................................... 109
. Cross-section showing the Kooi effect after LOCOS formation ............ 1 10
................ Cross-section after gate oxidation and V, adjustment implant 111
.................. Cross-section a£ter patterning of the floating gate poly layer 112
Cross-section after etching of the gate structure ..................................... 114
......................................................... Cross-section after SWS formation 115
Cross-section after sourceidrain formation ............................................. 116
................................................ Cross-section after aiuminum sputtering 117
.................................................. Cross-section fiom the program section 118
Cross-section of the read section ......................................................... 118
2 TABLE 3.1 ZE PROM cell process summary .............................................................. 57
TABLE 3 2 Description of the rnasks in the ZE*PROM process ................................. 76 TABLE 3.3 Layout design d e s for the ZE~PROM cell ............................................. 78
................. TABLE 3.4 Summary of the ZE~PROM process and electncal parameters 84
Introduction
1.1 Flash E~PROM Development
In 1970, Frohman-Bentchkowsky [Il developed a programmable memory cell based
on a MOS field effect transistor, with the addition of a floating-gate buried in the insulator
between the substrate and the control-gate as shown in Fig. l.l(a), In this celi, electrons
are injected into the floating-gate via hot electron injection and removed fiom the float-
ing-gate by ultraviolet light. This ceil is known as the UV-EPROM (Ultra violet Electrï-
cally Programmable Read Only Memory). In the late 1970s, several attempts were made
to develop Elechicaily Erasable and Programmable Read Only Memory (EEPROM or
E~PROM) cells that use electron tunnelhg through a thin tunnel oxide for programming
and erasing operations [l] as shown in Fig. l.t(b). The E*PROM ce11 is a two transistor
ce11 that consists of a select transistor in senes with a programmable transistor. It exhiliits
limited endurance (the number of write/erase cycles that a memory can endure before faiI-
ure) due to thin tunnel oxide breakdown. It bas slow programming speeds (-lûms), and
has lower density as compared to a UV-EPROM cell. To overcome the tunnel oxide break-
down problem and the slow programming speed of the E~PROM c d , the FCAT (Floating
Si-gate Channel Corner Avalanche Transition) memory ce11 was proposed in 1978 and is
illustrated in Fig. l.l(c) [4]. It uses a reverse-biased junction in avalanche to inject hot
1
electrons and hot holes over a süicon dioxide b b r for proogramming and erasing respec-
tively. However, this method was thought to have deleterious effects on cell reiiability and
endurance due to the large junction breakdown current and operating voltages used, as
well as the injection of hot holes into the gate oxide- Tunnel oxide
floating-gate I
psubstrate
control-gate 1
p-substmte
p-substrate
(a) W-EPROM ceLi [2] (b) E*PROM transistor [3]
(c) FCAT ceil, surface view and cross sections at xx and yy [4]
Deeper source
\
I p-substrate I I p-substrate I (d) ETOX celi 121 (e) NAND ce11 CS]
Figure 1.1 Different non-volatile memory ceUs
2
In 1984, the combination of hot electron programming and tunnel erase
was used to develop a single transistor 'Yiash'' E'PROM cell [l]. The flash acronym
cornes from the fact that the cell cannot be erased one byte at a tirne but
erasure must occur for the entire chip or large blocks of the chip. The cell
occupies a smaLler area and offers better endurance reliability over the previously
described non-volatile memory cells. The flash E~PROM cells that are available
on the market today, use either hot electron injection or twiaeling for programming,
while all use tunneling for erasing. These cells attempt to optimize the trade-off
between cell size, process complexity and performance. Out of ail these flash
memory cells, the most commoniy used one is the E T O X ~ cell (EPROM Tunnel
Oxide) developed by Intel [2]. A cross-section of the ETOX cell is s h o w in
Fig. l.l(d). The cell uses a very thin nuinehg gaie oxide of -100A and has
a deeper source junction compared to the drain to facilitate the tunnel erase
procedure. The drawback of the ETOX cell is that it requires a dual power
supply for cell operation. The strongest competitor to the ETOX approach is the
NAND cell developed by Toshiba [SI and shown in Fig. l.l(e). It uses tumeling
for both programming and erasing mechanisms. Due to the low current requirements
of the tunneling mechanism, the voltages required for cell programming and erasing
can be generated on chip. This cell also has a smaller ce11 area compared to
that of the ETOX tell, The NAND memory array achieves its dense layout by
sharing a single bit line contact between a large number of memory cells arranged
in series in a single column. WhiIe the NAND type flash E~PROMS are very
useful for low-power and high density mass storage applications, the typical prograflltning
time is on the order of milliseconds.
There are many other approaches for flash ceil designs that seek to blend
the advantages of the ETOX and NAND cells. These approaches also address
one or more features of an ideai non volatiIe memory, which are: fast reading,
writing and erasing, high density, and high endurance.
In the foilowing section, the basic operathg pnnciple of a conventional
flash rnemory cell that uses channel hot electron injection for programming and
tunneling for erasing will be descriid.
1.2 Basic Operathg hinciple of a flash E~PROM ceiJ
The basic operating principle of the flash memory ceii, Uustrated in Fig.
1.2, involves the storage of charges in a floating polysilicon layer or gate that
is completely surrounded by a dielecaic, usually thermal oxide.
p-substrate
Figure 1.2 The storage of charge in the floating-gate of the ceU
By manipulating the charge in the fioating-gate (43, the threshold voltage,
(V,) of the transistor can be modified to switch between two distinct values.
These are conventionaily defined as the "0" (programmed state), and the "I"
(erased state) as illustrated in Fig. 1.3. The V, shift caused by the stored charge
Qfg on the floating-gate is given by:
where Cfg is the capaciiance between the floating-gate and the control-gate, VQ
and Vte correspond to the threshold voltage of the prografnmed and the erased
States respectively.
The information content of the device is detected by applyhg a voltage
to the control-gate between the two possible threshold voltages. In one state, the
transistor is conducting current, while in the other, the transistor is cutoff. To
provide a non-volatile device, the injected charge must remain stored in the floating-gate
when the power supply is rernoved-
661" cw' h without with
Vte
Figure 1.3 The influence of charge in the floating-gate on the threshold voltage of the ceil
At high drain biases, the electrons that are accelerated by the electric field
at the drain side of the channel gives rise to impact ionization at the drain, in
which both electrons and holes are generated. The highly energetic holes are
coUected at the substrate contact and form the so-cailed substrate current. The
electrons, on the other hand, are coiiected at the drain, Some of these electrons
gain enough energy to surmount the Si02 energy barrïer. If the oxide field favors
injection, these
floating-gate as
electrons overcome the oxide barrier and are injected into the
shown on the energy band diagram in Fig, 1.5 161,
Silicon Oxide Poly-Si Channel Gate floating-gate
Figure 1.5 Energy band representation of hot electron injection on to the floating-gate
The magnitude of the hot electron gate current is dependent on both the
applied control-gate and drain voltages. This means that the gate current is determined
by the number of hot electrons and their energy (which is Iargely dependent on
the Iateral elecûic field in the channel of the transistor). The gate current also
depends on the oxide field, which determines the fraction of hot electrms that
can actually reach the gate. Processing and geometrical parameters such as the
7
gate oxide thickness and the effective channel Iength aiso Wuence the amount
of injection current,
1.2.2 Basic Erasing Mechsnism
Erase in a conventional ceil is achieved by applying a positive voltage on
the source, and a negative voltage or ground to the control-gate as depicted in
Fig. 1.6. The high fields across the gate oxide results in electrons tunnelhg out
of the floating-gate to the source by Fowler-Nordheim (F-N) tunneling 17, The
field in the gate oxide depends on the floating-gate capacitive coupiing to the
source, the control-gate and the channel. Once the electrons are removed fiom
the Roating-gaie, the V, of the device is Iowered to the erased state.
= - or GND v'g r\
l p-su bs trate I
Figure 1 -6 Erasing condition of a 0ash memory cell
In F-N tunneling, when a large voltage is applied across the floating polysilicon
gate-SiO2-silicon structure, its energy band diagram will be as shown in Fig. 1.7.
Due to the high electric field, electrons in the polysilicon conduction band see
a triangular energy barrier with a width dependent on the applied field. At sufficiently
high fields, the width of the barrier becornes small enough that electrons can
tunnel through the oxide barrïer from the Boating-gate into the source region. A
significant tunnel current can be observed when the oxide thickness is reduced
Figure 1.7 Energy band diagram representing the F-N tunnelhg of electrons fkom the
floating-gate to the source region
The nuineling current density J through the oxide is exponentially related
to the applied electric field by the equation
(-B )/E J = Ae
where A and B are constants and E is the electric field [7]- To keep the erasing
voltages low, the hmnellîng oxide thickness needs to be small, consistent with
reliability and manufacturability requirements. High fields present during the tunneling
operation can result in severe degradation of the tunnelling oxide, which cm
cause Mure of the memory cell.
1.3 Array Architectures
The flash memory celis can be configured into different types of array
architectures. These include the NOR, NAND and Virtual Ground architectures.
9
1.3.1 NOR lPpe Army Architecture
The NOR-type array show in Fig. 1.8 is comouly used to implement
flash E~PROMS CS]. In the horizontal direction, the control-gates of the ceiis are
connected together by polysilicon to fom the word ihe (WL). In the vertical
direction, the drain and source contacts of the cells are comected to metal bit
lines (BL) and source b e s (SL) respectively. CeU address enables a specîfic word
and bit line and in combination they select one memory cell w i h h the array-
Al1 non-selected word and bit lines are connected to ground.
BL1 BL2 BL3 BL4
1
Word Line B k Bit Line SL = Source Line
2
I SL 1 SL2 SL3 SL4
Figure 1 -8 Schematic diagram of a NOR-type flash E~PROM array
In this array, read and write operations are done in a sunilar manner
except for the clifferences in the applied voltages. The advantage of this architecture
is the larger read current which leads to a fast access tirne for the memory cell.
Intei's ETOX cells are configured in a NOR-type array architecture [8].
10
1.3.2 NAND TPpe Array Architecture
NAND flash memory is a relatively recent architecture pioneend by Toshiba
[SI. Fig. 1.9 shows the interconnection of transistors in a NAND array- The high
density in this array is obtained by reducing the number of bit line contacts
required within the array. The memory ceiis are isolated at each end of the
column by select gates.
BLO BLI I
WL= Word Line B k Bit Line
Metal a+ - -
1 1 i f Polysilicon
I I W L O
I I
I I I I
I i
1 1 1 I -15
I I SLO SLl
Figure 1.9 Schematic diagram of a NAND-type flash E'PROM array
In this architecture, the intemal program and erase operations are done by
using F-N tunneling. NAND flash memory applies voltages to the substrate and
to the control-gate. nie required voltages can be generated on chip due to the
low currents in the tunneling mechmism. This makes the NAND ceil ideai for
low voltage portable applications.
The F-N tunneling mechanism is a relatively slow process when compared
to hot-electron injection. Typical programming times are on the order of milliseconds.
The access time is dso slow because of the s m d read currents that result fiom
the ceIls that are connected in series in the array. To overcome these limitations,
reading and Wnting of the array are done in paraUe1.
1.3.3 Voirtual Ground Array Architecture
Another array architecture that does not have bit line contact openings to
achieve minimum device area is called the virtual ground architecture 191. This
architecture uses diffbsed bit lines instead of metal bit lines and is illustrated in Fig, 1.10.
Diffused bit Iines I I -1
I - I 1 - 1 - I I I I I I D
I I I I l I I I
- I I - I - 1
I I I L I I t I I
BLL BL2 BL3 B U BL5
I I l I
m2 I WL= Word Line
1 - f BL= Bit Line
I - 1 f I t
Figure 1.10 Schematic diagram of a V i a I Ground flash E*PROM array
I - 1 - 1 1 -
t 1 I I I
I i
I I I
I I
I I
I I
While the virtud ground architecture leads to reduced m a , it exhibits many
disadvantages. When a certain word h e (WL) and a bit line (BL) are selected,
two ceils are addressed dong the same word line row. For example, when WL1
and BL3 are addressed, both ceiis A and B are selected. Therefore, ceU B too
would be erroneously programmed or read. To avoid this, all the bit Lines to the
right of BL3 have to be raised to the same voltage as BL3. This causes the
drains and the source regions of the cells to the right of cell A to have the
same potential thus complicating the addressing of the memory.
The high resistance in the dBbsed bit lines is another undesirable feature
of this array. To compensate for the potential drop dong the bit Line, a large
drain voltage is required. The read current also degrades due to the high resistance
in the bit lines.
1.4 Reliability of flash E~PROM
Degradation due to progrderase cycling is the most important reliability
issue for flash memory devices. The limiting factor on the number of program
and erase cycles obtahable is usudy due to the degradation of the gate oxide
[Il]. Holes generated during erase at the source side get injected into the gaie
oxide resulting in V, degradation. Electron trapping in the oxide also occurs after
several programming cycles. Trapped electrons decrease the rate of programming
as the electrons that flow through the oxide now encounter locally repulsive fields.
Therefore, as the number of cycles increases, the trapped charges begin to slow
down the movement of electrons back and forth to and from the fioatuig-gate.
This leads to an increase in program and erase tirnes, which is of significant
concern for the system designer. This condition c m be minimized by proper growth
of the gate oxide to reduce the density of electron ûaps.
Another cntical concem in the fiash E~PROM cells using thin oxide based
processes is the storage of charge (10 years) under normal chip operating conditions.
Leakage through the tunnel dielectrïc or interpoly dielectric is the basic charge
loss mechanism- The two worst case conditions for charge loss, are control-gate
high and drain low, and control-gate low and drain high. These two conditions
lead to leakage through the interpoly dielectric and leakage through the tunnel
dielectric thus producing erroneous data k i n g stored in a cell. The disturb mechanisms
that affect data integrity are drain disturb, DC program, DC erase and read disturb ClO].
1.4.1 Drain Disturb
Drain disturb occurs when programmed cells are sharing the same bit line
with a ce11 that is king programmed. This situation is Uustrated in Fig. 1.1 1
where an aiready programmed ceil A is experiencing drain disturb while ce11 B
is being programmed. Under this condition, the word line of ceU A is grounded
and the bit line is pulled to Vdd. Th" creates a high field between the drain
and gate for cells sharing the bit Line with the ceil that is king programmed.
If these cells are in the programmed state, this may cause some electrons to
tunnel from floating-gate to the drain leading to a lower threshold voltage thereby
erroneously erasing the ceils. For these cells to be immune to this leakage, no
change in the stored charge on the floating-gate must be observed for the total
time that it would take to program al1 the cells dong a bit line.
Figure 1.1 1 The distub conditions experienced in a NOR type flash E~PROM array
Erased cells which share a common word Line with a ce11 that is king
programmed, suffer from DC program. When a high voltage is placed on the
gate of the ce11 that is bekg programmed, the erased ceiIs sharing the cornmon
word h e are exposed to this voltage as weli- The high electric field across the
gate oxide of these erased cells may cause some electrons from the substrate to
tunnel across and accumulate on the floating-gate, thereby raising the threshold
voltage. This condition is shown in Fig. 1.1 1 where ce11 C is experiencing the
gate disturb condition while ce11 B is being programmed. For the celi to be
immune to this leakage, no change in the stored charge on the floating-gate must
be observed for the total time that it would take to program ail cells dong that word line.
1.4.3 DC Erase
DC erase occurs to programmed celIs sharing a common word line with
a celi that is king programmed In this case, the high electric field causes some
of these programmed cells to loose electrons by conduction through the interpoly
dielectric. Fig. 1.1 1 shows ceil D leaking charge whiie ceil B is being programmed.
This cm leave cell D in an erased state.
1.4.4 Read Disturb
During prograrn and read operations of the Bash memory ceils, the voltages
applied to the control-gaie and to the drain are both positive and curent flows
through the device. The only ciifference between the read and the prograrn condition
is the magnitude of the voltages applied at the drain and gate of the cell. Therefore,
even a smail drain voltage can result in electron injection resulting in erroneous
programming of the ceU.
1.5 Limitations of Conventional flash E~PROM CeUs
One of the major limitations of flash E~PROM devices which rely on conventional
channel hot electron injection for programming, is the need for an external higbvoltage
power suppiy (>SV) to program within a reasonable time. In this programming method,
when the channel length is reduced to the sub-half micron regirne, the drain voltage must
also be reduced to avoid punchthrough breakdown. This limits the electric field at the
drain thus reducing the hot electron generation efficiency. Therefore, this p r o g r d g
method lirnits the possibility of using flash E*PROM for low voltage (Q.3V) applications.
The channel hot electron p r o g r h g method also generates very high source-to-dfain
currents (in the range of milliamperes). This limits the number of cells that cm be pro-
grammed at one tirne.
The corner avalanche injection method used in the FCAT cell does not result in fast
programming since the avalanche injectors are not located directly below the Boating-gate.
It also suffers fiom ceU reliability problems due to the large voltages used for program-
ming and the hot hole injection method used for erasing.
In the ETOX ceil erase operation, the high voltage (+12V) applied to the
source terminal generates hot holes that get trapped in the gate oxide. These
trapped holes result in V, degradation as the number of program and erase cycles
increases.
The slow programming speed (-10p) is another major drawback of existing
flash cells. This limitation, prevents their application as replacement for RAMs
and electronic hard disks.
Charge leakage through the interpoly dielectric and gate oxide is aiso of
critical concern in terms of reliability The disturb conditions such as drain disturb,
DC program, DC erase and read disturb affect data integrity of the flash memory ceIl.
1.6 Objective and Outline of Thesis
A flash E~PROM MOSFET ce11 using Zener breakdown at a heavily doped p+n+ junc-
tion was previously proposed by the author as part of her M.A.Sc thesis[l6]. The structure
involved two nfpf injectors one each at the source and drain sides of the charme1 and was
implemented in a 3pm process. The celL was proven operational at Sv
Given the increasing demand for portable applications, device dimensions as weil as
supply voltages must be scaled down to achieve higher packing deasity, higher speed and
Iower power dissipation. The objective of this thesis is to propose, implement and charac-
terize a modified 3.3V Zener-based MOS memory ceIl (&PROM) [12] programmed by
+ + hot electrons generated using a single, heavily doped reverse-biased p n Zener injector
attached to the drain. The ceil is implemented in a submicron (0.8p.m) CMOS compatible
process and achieves higher density., better programmr'ng speed reduced disturb condi-
tions and enhanced endurance characteristics, as compared to the previously proposed cell
[16]. The use of a 3.3V supply makes the present Z~PROM ceil suitable for a variety of
portable applications. In addition, the cell provides a practical soIution to some of the Lm-
itations of conventionai flash memory cells that use the channel hot electron programming
method.
A novel orthogonal write architecture, suitable for a ZE~PROM array is also pro-
posed. This write architecture minimizes drain disturb time and power dissipation while
maintainhg a programming speed of the order of several hundreds of nanoseconds in the
ZE~PROM ceils.
In Chapter 2, the 3.3V ZE~PROM cell and array architecture are presented.
The ceil operation is discussed by means of an analytical device mode1 and two
dimensional device simulations.
Chapter 3 discusses the fabrication process and the characterization of the
ZE~PROM cell and array. The fabrication of the test rnemory cells are carried
out in a 0.8pm, double polysilicon, CMOS process. Two-dimensional process simulations
are performed to define the process parameters. The characterization of the thin
+ + gate oxide, oxide-nitride-oxide (ONO) interpoly dielectric and the p n Zener junction
18
are investigated on fabricated test structures. The experimental ceil characteristics
such as programming, erasing, reading, endurance and reliability obtaiwd on fabricated
devices and arrays are also discussed in detail-
FinaMy, in Chapter 4 concIusions are drawn regarding the implications of
this ceii design and topics for future research are presented.
References
C. Hu, 'Wonvolatile Semiconductor Memories Technologies, Design and
Application", pp- 1-2, IEEE Press, New York, 1991.
B. Dipert and L. Hebert, 'Flash Memory goes mainstream", IEEE Spectnun, Vol.
30, pp 48-52, October 1993
A. KoIodny, S.T.K. Nieh, B. Eitan and J. Shappir, "Analysis and modehg of
floating-gate EEPROM ceiis", IEEE Transaction on EIectron Devices, Vol. 33, pp.
835-844, 1986-
M. Honuchi and H. Katto, "FCAT - A Iow voltage high speed alterable n-channel
nonvolatile memory device", TEEE Transaction on EIectron Devices, Vol. 26, pp.
914-918, 1979.
M. Momodomi, R. Kirisawa, R Nakayarna, S. Aritome, T.Endoh, Y Itoh, Y Iwata,
H. Oodaria, T. Tanaka, M. Chiba, R- Shirota and F. Masuoka, "New device
technologies for SV-ody 4Mb EEPROM with NAND structure ceil", IEDM
Technical Digest, pp. 412-415, 1988.
B. Eitan and D. Frohman-Bentchkowsky, "Hot eIectron injection into the oxide in
n-cbannel MOS-devices," LEEE Transaction on Electron Devices, Vol 28, p. 328,
198 1.
M. Lenzlinger and E.H Snow, 'Fowler-Nordheim tumeling in themaiiy grown
Si02," Journal of Applied Physics, Vo1.40, pp.278-283, 1969.
B. Dipert and M. Levy, 'Designhg with flash Memory", pp. 25-32, Annabooks,
San Diego, 1994.
W. Kammer, B. Sani, P. Kauk, R. Kazerounian and B- Eitan, "A new virtual ground
array architecture for very high speed, high density EPROMs," International
Symposium on VLSI Circuits, Proceedings, pp. 83-84, 199 1-
A. Ahmed, ''Flash Memory Reliability", EDN, p. 32, June 1994.
[ I l ] S. Haddad, C. Chang, B. Swamùiathan, J. Lien, ''Degradation due to hole trapping
in flash memory cells,? IEEE Electron Device Letter, Vol. IO, pp. 1 17-1 19, 1989.
[12] J. Ranaweera Kalastirsky, E. Gulersen, W.T- Ng, and C-A.T. Salama, "A Method
of Fabricating a Fast Programming flash E'PROM ceIl," U.S. patent application,
June 1996.
1131 J. Ranaweera, 1. Kalastirsky, E. GuIersen, W.T. Ng and C.A.T. Salama, "A novel
programming method for high speed, low voltage flash E'PROM cells", Solid State
Electronics, Vol, 39, pp- 98 1-989, 1996.
1141 J. Ranaweera, 1. Kalastirsb, A. Dibu-Caiole, W-TT Ng, and CAT- Salama,
6Terformance Limitations of a flash E~PROM cell, programmed with Zener induced
hot electrons", IEEE Non Volatile Memory Workshop. Paper #Z2, 1997.
[LS] J. Ranaweera, W-TT Ng and C.A.T. Salama, "Simulation, Fabrication and
Characterization of a 3.3V flash ZE~PROM array implemented in a 0.8pm
process", Solid State Electronics, accepted for publication.
[la J. Ranaweera, "Developrnent of a Hash EEPROM celi suitable for 5-V operation,"
M.A.Sc. Thesis, University of Toronto, April 1995.
CHAPTER 2
The 3.3V ZE~PROM Cell and Array Architecture
2.1 Introduction
Conventionai channel hot electron programming relies on biasing the device
at a large drain voltage to achieve a high channel electric field for hot electron
generation. A high positive gate voltage is used to obtain a high gate-to-drain
field to assist electron injection into the Roating-gate. Due to the high drain
voltage required for cell prograrnming, fiash E*PROM celis that employ the conventional
channel hot electron method are not readily suitable for low voltage applications.
Therefore, it is necessary to find alternative methods of injecting electrons to
program the ceil at lower voltages.
In this chapter, a flash E~PROM cell structure that incorporates Zener junction
breakdom to achieve very fast programming at low voltages is presented. This
ce11 uses hot electrons injected from the drain side to charge the floating-gate.
The ce11 exhibits excellent programmability at a supply voltage of 3.3V and has
considerable potentiai for applications in which hirther reduction in power supply
voltage are necessary
This chapter is organized as follows. First, the Zener based ZE*PROM cell
structure is presented and the methods of programming, erasing and reading are
22
discussed. The analytical mode1 of the ZE~PROM ceil based on a simple capacitor
model is developed. The device performance is then analyzed using two-dimensional
numerical simulations. This is followed by a discussion of the array architecture
used in implementation of the orthogonal programming technique that is needed
to reduce drain disturb and power dissipation,
2.2 Cell Structure and Operations
The optimized version of the ZE~PROM cell Cl-41, illustrated in Fig. 2.1, has a pç
pocket implant extending part-way across a portion of the width of the drain region to gen-
erate hot electrons for programmhg.
floating-gate
Figure 2.1 The propsed ZE~PROM ceil structure.
The heavily doped pfn+ junction in the reverse-biased condition is capable of gen-
erating the hot electrons required for programming at relatively low voltages. These hot
electrons result from Zener breakdown [a. If the doping densities of both the p and n sides
23
are greater than 10'~cm-~, the depletion layer at the junction is very thin and the eIectnc
field necessary for Zener breakdown is reached at voltages less than SV [a. Since the d o p
ing concentration of the n+drain region of the cell is on the order of 102°cm'3, the drain
breakdown voltage depends principaily on the ciophg of the pf region.
22.1 Programming
To program the Z~PROM ceII show in Fig. 2.2, the p*nf junction is reverse
biased to create an elecnic field of -106 Vkm and generate energetic hot electrons inde-
pendently of the channel length. At these fields, the electrons gain sufticient energy to sur-
mount the energy barrier between the silicon substrate and the SiOz gaie insulator. By
increasing the doping concentration of the p+ region, the depletion region can be narrowed
and the magnitude of the electric field peak c m be increased 151. Also associated with this
increase in the p+ region doping is a decrease in breakdown voltage. Therefore, the applied
drain voltage can be lowered
1 p - substrate V
ron populai ion.
Figure 2.2 Programming of the Z~PROM ceii
2.2.2 Erasuig
As depicted in Fig. 2.3, erasing is performed by Fowlec-Nordheim tunnelhg of
electrons fiom the floating-gate to the source. In this erasing method a negative voltage is
applied to the control-gate while the source is connected to the supply voltage.
vcg-
Figure 2.3 Erasing of the ZE'PROM ceii
2.2.3 Reading
Since the pC region adjacent to the drain region exhibits a low breakdom voltage,
which contributes to soft programming, the source region must be used in the read opera-
tion as illustrated in Fig. 2.4. In this ce11 design, the reduced channel width available for
reading also yields lower read current compared to the conventional Rash memory cells.
This can be compensated by using a larger device width, or if programming speed is not
critical, reducing the width of the pf dinusion.
1 p - substrate v I r
Figure 2.4 Reading of the ZE~PROM cell
2.3 Analytical Model of the ZE~PROM Cell
Similar to other flash memory cells, the presence of a floating, but conductive gate
inside the gate dielectric has important consequences from the device modeling point of
view. In this section, the floating-gate potential due to capacitive coupling during pro-
gramming, erasing and reading operations, and an analytical model for 1-V characteristics
are derived. This aoalytical model is a useful tool in predicting the behavior of the fabri-
cated ZE~PROM ceiis.
2.3.1 The Capacitor Model
To gain insight into the basic charge-transfer characteristics of the ZE~PROM
structure, a capacitive equivalent circuit was developed as shown in Fig. 2.5. The voltage
on the floating-gate is contrded through capacitive-coupling with the extemal nodes of
the device. Cfg is the capacitance between the controi-gaie and the fioating-gate, 5, s, Cd and Cs are the couphg capacitances between the floating-gate and the substrate, the p+
region, the drain and the source respectively.
Figure 2.5 The equivalent capacitance mode1 of the ZE~PROM ceil
When the device is operating in the program mode, the current through the thin
tunnel oxide is integrated and appears as a charge Qfg on the fioating-gate. The accumula-
tion of the charge on the floating-gate is reflected as a change in the threshold voltage V, of
the device. The relationship between Vt and Qfg is given by
where V~ corresponds to the initial Vt when Qfg = O. The threshold shift is proportional to
the charge stored on the floating-gate.
Charge balance implies that
Cfg(Vcg -Vfg) = Cr(Vfg - Vr) +Cp (Vfg - Vb) + Cp + (Vfg - Vb) +Cd(Vfg - Vd) (2-2)
From Eq. 22 , the floating-gate voltage Vfp due to capacitive coupling, can be derived for
the typical bias voltages applied during programming and expressed as
where CT, the total capacitance of the Boating-gate, is then defined as
Two important coupiing factors: k, the control-gate couplhg factor and d, the drain
coupling factor can be defined as follows
These factors detennine the fraction of the control-gate and the drain voltage that is capac-
itively coupled to the floating-gate.
Expressed in terms of the coupling factors, Eq. 2.4 becomes
Due to the additional capacitor %, Vfg due to capacitive coupling in the
E~PROM cell is lower than in a conventional flash E~PROM ceil. This condition tends to
slow the pefiorxnance of the device. However, the ZE~PROM ceii is capable of high speed
programming due to the energetic hot electrons created by the high electric field at the
Zener injecter.
The floating-gate voltage during the read operation is detennined by capacitive
coupling between the floating-gate and control-gate, and the floating-gate and source
28
voltages, Since the capacitive coupihg of the fioating-gare c m affect the read
current, it is important to v e e how it impacts the 1-V charactenstics. The
influence of extemal voltages and ceii dimensions, on the read speed can also
be derived fiom the 1-V charactenstics of the ZE~PROM cell.
The surface view of the ceiI together with its dimensions are shown
in Fig. 2.6. The channel Iength, channel wÏdth and the width of the p+ region
are L, W and Wp respectiveiy.
gate '
Figure 2.6 The surface view of the ZE*PROM celi
During the read operation, Vfg due to capacitive coupling can be expressed as
Similar to conventionai flash memory celis, the device equations for the
ZE~PROM can be obtained by ceplacing Vg in the conventional MOS transistor
29
equations with Va. The device parameters such as the oxide thickness and
Vt also must be rnodified with values measured at the control-gate [q. Since
Vt is higher and the oxide thickness is larger with respct to the control-gate,
they can be expressed as foUows
and
w here,
1-V characteristics for the ZE~PROM ceil in the linear and saturation
regions can be obtained by rewriting the conventional long channel MOS device
equations and using Eqs. 2.6, 2.7 and 2.8.
Id = P[(v~ - Vt)Vd - f $1 vaiid for IVdl<lVgVJ, or in the iinear region
of the MOS devices, can be expressed as
Since the source region is used for reading, &-J and Vd are changed to T,
and V,. Substituting Eq. 2.6 results in
Is = P
where
pcox P = T (W - W ) and Eq. 2.1 L is valid for P
can be transformed
is valid for V > V -V , or in the saniration region l d l - l g tl
to
w here
Due to the V term in Eq. 2.12, the channe1 c m be tumed on
~ C o x fj=- (W - W ) and Eq. 2.12 is valid for (VsI L - L P CT
-g i.
by the source voItage and the
current even when IV,&IVJ.
Cs +-vs- cg C
fg vt
with the increase of V, and
'
transistor can go into depIetion mode to conduct
Therefore, the read current wiiI continue to rise
saturation will not occur, This condition can be
seen in Section 2.4.3, Fig. 2.17 where the sirnulated 1-V characteristics are
described for 0 . 8 ~ E*PROM cells. When the gate length is reduced to
shorter chamel lengths, the read current will further increase resulting in faster
accessing of the ceil.
When Wp=W/2, the read current in the memory cell decreases by a
factor of 2 to represent the portion of the ce11 width used in the read operation.
This leads into a slower read speed in the ZE~PROM cell.
2.4 2D Device Simulations
The ZE~PROM ceas programming and erasing operations were simuiated
by using TMA MEDICI'S Programmable Device Advance Application Module with
Fowler Nordheim and hot carrier gate curent models, Impact ionization and band-to-band
tunneling were included in simuIating the programming to obtain the total electron
current contribution to the gate current,
2.4.1 Programming
To demonstrate the ability of the Zener induced programming method to increase the
injection efficiency as compared to the conventional hot electron programming method,
numerical simulations of a conventional flash ceii and a E~PROM ceii were performed.
To compare the two programming methods, devices with 0 . 8 ~ gate lengths (L),
-85A thin gate oxides and -200A thick interpoly dielechics, as illustrated in Fig. 2.7,
were considered. The p-type substrate doping was 6 ~ 1 0 ~ ~ c r n - ~ and the nf source/drain
region junction depth was 0.3p.m with a peak doping concentration of l x l ~ ~ ~ c r n ~ ~ . The p+
region of the Z E 2 p ~ 0 ~ cell had a peak doping of l x l ~ ~ ~ c r n - ~ with a junction depth of
0.25pm. The junction depths and doping concentrations of the nf/p+ regions, dimensions
of the gate structure, and the substrate doping were selected to closely emulate the process
parameters of the fabricated test structures.
To initiate the transient p r o g r d n g operation, time steps between lns to 1OOp
were specified. Both devices were biased with V&2V and Vd=3.3v Figs. 2.8 through
2.12 show the simulation results for Vfg, Qfg, hot electron cunent (kd, drain current (h)
and injection efficiency (If&) during programming of a conventional flash E~PROM ce11
as well as a Z E 2 p ~ 0 ~ cell. In these figures, the ZE~PROM ceil is referred to as cell A and
the conventional ceil as cell B.
p - substrate '-25-t- v 1 p - substrate 1/
(a) Cell A (b) Cell B
Figure 2.7 The cross sections of (a) ZE~PROM ceU and (b) conventionai flash memory
cell, showing the dimensions used for numerical simulations.
The drain voltage of 3.3V and the doping level of the p+n+ junction contribute to the
electrïc field responsible for hot electron generation. At the beginning of the programming
operation, the voltage coupled to the floating-gate is dependent on the capacitance values
of the memory ceil. Fig. 2.8 shows how Vfg for cells A and B changes with the program-
ming time.
Due to the additional p+ region, cell A has a lower initiai Vfg compared to ce11 B. This
result is consistent with the capacitive coupling of the p+ region predicted in the analyticai
mode1 (Eq. 2.4) of the Z~PROM cell. Fig. 2.8 also shows that at approximately Sons,
with hot electron injection, Vfg in cell A decreases due to the negative charging of the
floating-gate while Vfg in ceIl B remains unchanged. This is related to the hot electron
generation efficiency of the pfn* junction in celi A-
Programming time (Sec)
Figure 2.8 floating-gate voltage vs. progrmmïng time of ceils A and B
At the beginning of the hot electron injection process, the field in the oxide causes the
electrons to flow through the oxide. Fig. 2.9 shows how the fioating-gate voltage is
reduced when the floating-gate charges up- This is more evident in ce11 A than in ceIl B.
This condition reduces electron injection causing the gate current to drop as the electron
injection process becomes self-limiting. As the floating-gate becomes fully charged, the
gate current is reduced almost to zero because the oxide field prevents M e r injection of
electrons. As illustrated in Fig. 2.10(a), the reduction in gate current is larger in ce11 A than
in cell B-
Figure 2.9 kF oating-gate voltage versus floating-gate charge of ceiis A and B
In ce11 A, the hot electron curent is highest at the beginning of the writing process but
begins to drop after about 400ns as the negative charge injected on to the floating-gate
becomes significant (-1xl0-~~~) as shown in Figs. 2.1O(a) and (b). This in tum leads to a
lower floating-gare potential and a decrease in hot carrier injection. Fig. 2.10(b) aiso
shows that after lns of prograrnming, cell A has already acquired a charge on to the float-
ing-gate that is more than three orders of magnitude larger than ce11 B. At lOOps, the chan-
ne1 hot electron programming methcd used in ce11 B is still unable to generate enough
charge while ceiI A is already programmed. Figs. 2.8 to 2.10 show that the ZE~PROM cell
can be programmed in 60hs while the conventional ceii remains unprograrnmed at
100p.s.
NOTE TO USERS
Page(s) not included in the original manuscript are unavailable from the author or university. The manuscript
was microfilmed as received.
This reproduction is the best copy available.
UMI
The device simulations were also performed to compare the power dissipation and the
injection efficiency of ce& A and B. Fig. 2.1 1 shows that during programming. the drain
current in cell B is more than an order of magnitude larger than the drain current (or Zener
breakdown current) in ceLl A. Therefore, ceU A dissipates much less power than ceU B
dunng the programming of a single cell. The drain current together with the higher magni-
tude of the electric field ( -10~~fcrn) , created by the heavily doped p%* junction in ceIl A.
lead to higher injection efficiency as compared to cell B, as illustrated in Fig. 2.12. These
simulation results show Zener induced hot electrons are more effective for high speed pro-
gramming at a 3.3V supply than the conventionai channel hot electron methoci.
Programming time (Sec)
IO-^
Figure 2.1 1 Drain current during programming of ceils A and B
Ceil B / ~ 7 i a ~ h E~PROM,
n
E S. \ cn
E" 4 V
u " L O - ~
Cell A
(ZE~PROM,
lod I I r 1 w
las IO-' 1 o - ~ i o - ~ 104
Programming time (Sec)
Figure 2.12 Electron injection efficiency during programmhg
2.4.2 Erasing
Erasing of the Z~PROM ceU is performed by tunneling of electrons from
the floating-gate to the source. This is accomplished by applying a positive potentid
to the source region and a negative potentiai to the control-gate. A typical erase
characteristic of the simulated ZE~PROM celI is discussed next.
For this operation, 3.3V at the source and -12V at the control-gate were
used. Under these bias conditions, there is a sufficiently strong electrïc field in
the oxide between the floating-gate and the source for the negative charge to
tunnel through the oxide. As in the case for the programming operation, to initiate
the transient erasing operation, time steps between lps to lOOms were specified.
Figs. 2.13 and 2.14 show how the floating-gate potential increases as the negative
charge is removed by the erase operation.
Erasing tirne (Sec)
Figure 2.13 floating-gate voltage during erasing of a ZE~PROM ce11
Figure 2.14 FLoathg-gate charge versus floating-gate voltage during erasing of a
Z~PROM cell
The Fowler-Nordheim tunneiing curent is highest at the beginniag of the
erase cycle but decreases as the floating-gate becomes less oegative as shown in
Fig. 2.15. This reduces the field in the thui gate oxide and the threshold voltage
V, of the ceU decreases. Mer -50ms. the stored charge in the fioating-gate is
removed as shown in
10-~
IO-9
10-Io l 1
10-l4 {o-~ - - L O - ~ 1 &
ras in^ time (Sec)
Figure 2.15 F-N tunneling current during erasing of a Z~PROM ceIl
Erasing time (Sec)
Figure 2.16 floating-gate charge during erasing of a ZE*PROM ceU
2.43 Reading
The simulated 1-V characteristics of a ZE~PROM cell of 0 . 8 ~ gate Length
are shown in Fig. 2.17. The source voltage ranges from O to 2 . N and the
control-gate fiom OV to 3.3V.
A steeper slope c m be seen in the saturation region of the 1-V characteristics
compared to conventional MOS transistors. This difilerence is due to the capacitive
couphg between the source region and the floating-gate, which prevents the memory
celi fiom gohg into saturation. r - . - - . - - - - , - - - - . - - - - . - - - - , . - - - . - - - - . - - - - . - . - - , - - - .
O- 14- vcg=3.3v -
v, WolW
Figure 2.17 Read current in a ZE*PROM ceIl
2.4.4 Siimmary of Device Simulations
The simulation results demonstrate the ability of the Zener induced progr&ng
method to increase the injection efficiency as cornpared to the conventional hot
electron programming method. As predicted by the device equations in the analytical
model, the extra p+ region in the ZE~PROM celi results in a Lower initial VQ
compared to that of a conventionai memory ceii. However, the ZE*PROM celi
is capable of fast programming due to the energetic hot electrons created by the
Zener injector. The simulation results show ihat it is possible to program a ceIl
in 60011s at 3.3V by using Zener induced hot electrons. The erasing is done by
the Fowler Nordheim tunneling mechanism and it takes -50ms to remove the
stored charge from the floating-gate. This result is consistent with the erase time
for conventional flash memory ceils that use the same erasing mechanism. S i d a r
to other flash memory cells, the capacitive coupiing of the floating-gate cm strongly
distort the 1-V characteristics of the LE~PROM ceiI. The reduced channel width
available for reading also results in slower reading.
2.5 Array Architecture and Orthogonal Pmgramming
The ZE~PROM ceiis can be implemented in a NOR type memory array as shown in
Fig. 2.18. The rows of the array are accessible through plysilicon lines that contact the
control-gates of the ceus. The drain and source regions of a column are comected to two
dedicated metal bit and source lines.
Pol ysilicon
Figure 2.18 The ZE*PROM implemented in a NOR type array architecture
When programmllig a ZE~PROM array with n word lines. ail the p+nf junctions that
are comected to the same bit-he wiil be conducting n x h and dissipate a power of
(n x Vd x h). The bit-he current and the power dissipation are independent of the num-
ber of cells king programmed simuitaneously within the bit-line. Therefore, aU the
required cells in one bit-line c m be programrned together (orthogonal programming),
before selecting the next bit-iine. This resdts in programming the required cells in the
bit-line within the programming tirne and power used for a single Z~PROM ceil. To pro-
gram celis P and R in the memory array shown in Fig- 2-19, the BLI is comected to 3.3V,
the substrate is grounded, the metal source Iine (SL1) is Ieft floating and 12V is applied to
the selected word h e s WL1 and WL3.
SLl S L ~ SL3 (Floating) (OV) (OV)
Figure 2.19 Orthogonal programming (cells P and R) of the ZE~PROM anay (h is
flowing in aiI the cells connected to BL1)
Under these bias conditions, ail the unselected ceiis attached to BLl aiso are exposed
to Zener breakdown at the drain. Once the required cells attached to BLl are programmed,
the ceUs attached to BL2, BL3, etc. can be programmed one bit h e at a tirne. For exam-
ple, aU memory cells attached to the bit he, can be programmed simultaneously within
the programming the of a single memory ceIl.
2.5.1 Drain Disturb
When a bit-line in the array is connected to 3.3V to program selected
memory cens, the drain regions associated with the selected bit-he breaks down
generating hot electron-hole pairs. The generated hot electrons are injected into
the floating-gate of the ceUs with control-gates biased at 12% thus programming
these ceiis. Simuitaneously, unselected cells dong the bit-üne (V@V and Vp3.3V)
have hot holes injected into their gate oxide (drain dishirb) as illustrateci in Fig. 2.20.
(3.3V) (OV) BL1
(OV) E3L2 BL3
Figure 2.20 Drain disturb, by hot hole injection, in the unselected ceus of the array (cell
Q), while celIs P and R are king programmed
This undesired injection of hot holes associaîed with ZE'PROM celi progtamming
can be minimized by using the orthogonal programming technique- In an array
with n word Iines, the maximum drain disturb time using orthogonal programmhg
is n times less than in a conventionai word-line by word-line p r o g m ~ g technique.
2.5.2 Gate Disturb
Similarly to drain disturb, gate disturb can occur when an unselected cell is exposed
to bigh word-line voltages as one ceiI dong the same word h e is k i n g programmeci- In
this condition, unprogrammed cells cm have electrons tunnel fiom the n+ drain and source
regions into the floating-gate increasing the threshold voltage of the ceii. Another form of
gate disturb occurs when an unselected programmed ce11 is exposed to a programming
voltage on the word Lne. In this condition, the stored electrons can tunnel fiom the float-
ing-gate to the control-gate through the Oxide-Nitride-Oxide (ONO) inter-poly dielechic.
This results in a reduced threshold voltage for the cell. With the orthogonal programming
technique, the ceus must be immune to the gate disturbance for the total time that it takes
to program all the cells dong the word-line.
A ZE'PROM cell, operating with 3.3V was presented in this chapter. One
of the most attractive features of the ce11 is the capability of programming the
ce11 in nanoseconds by using only a 3.3V supply. This is extremely fast by
cornparison with state-of-the-art Rash E*PROM cells.
An analytical mode1 for the cell was developed to ve- the 1-V characteristics
of the cell. The ceil operation was studied by using the two dunensional device
simulator MEDICI. Ceii performance such as programming and erasing times were
verified and compared with a conventional flash memory ceil.
An array architecture and an orthogond programming technique suitable
for reducing drain disturb and power dissipation were aiso described. The fihication
steps of the ceil and array are discussed in detail in the next chapter.
Cl] J. Ranaweera, 1- Kalastirsky, A- Dibu-Caiole, W.T- Ng, and C-A-T, SaIama,
"Performance Limitations of a flash E'PROM cefi, programmed with Zener induced
hot electrons", IEEE Non Volatile Memory Workshop, 1997.
[2] 1. Ranaweera, 1. Kaiastirsky, E. Gdersen, W . Ng, and C-A-T- Saiama, "A Method
of Fabrkating a Fast Rogramming flash E~PROM ceiI," US. patent application,
June 1996,
[3] J. Ranaweera, 1. Kalastirsky, E. Gulersen, W-TT Ng and C.A.T. Salama, "A novel
programming method for high speed, low voltage flash E~PROM ceiis", Soiid State
Electronics, Vol. 39, pp. 98 1-989, 1 996.
[4] J. Ranaweera, W.T. Ng and C.A.T. Sdama, "Simulation, Fabrication and
Characterization of a 3.3V fi ash ZE*PROM atfay implernented in a 0 . 8 ~
process", Solid State Electronics, accepted for publication.
[SI D.A. Neamen, "Semiconductor Physics and Devices", Chap.8, R D . Irwin, Inc.,
MA 1992.
[6] E.S. Yang, 66Mïcroeiectronic Devices", Chap.3, McGraw-Hill, Inc., Illinois 1988,
[7] S.T. W n g , "On the 1-V characteristics of floating-gate MOS transistor", IEEE
Trans. Electron Devices, Vol. 26, pp. 1292-1294, 1979.
Fabrication and Characterization of the ZE~PROM Cell and Afiay
3.1 Introduction
The purpose of this chapter is to discuss the processing steps used to
fabncate the ZE~PROM test structures and arrays, and to hilly characterize the
structures experimentaliy. The ZE~PROM process is designed to be compatible
with a 0 . 8 ~ CMOS process. The cntical steps in the fabrication process of the
ce11 include the growth of the thin (85& high quality gate oxide, the interpoly
dielectric consisting of an oxide-nitride-oxide (ONO) sandwich with 200A of equivalent
oxide thickness and the formation of the heavily doped p+n+ Zener junction attached
to the drain. The preliminary design of the process parameters was obtained using
TMKs TSUPREM-4 two dimensional process simulator Il] and M e r refined by
experimental results. The layout d e s used for mask making are aiso described
in detail. The fabricated test structures were characterized with respect to programming,
erasing, reading, disturb conditions and write/erase endurance.
The complete process Bow used to implement the ZE~PROM ceii and array
is described in Section 3.2. Process simulations discussed in Section 3.3 were
used to predict the preliminary process specifications. Section 3.4 discusses the
experimentai development of the thin gate oxide, the ON0 dielectric and the p+nt
Zener junction, Section 3.5 descri'bes the mask layout design d e s as well as
the test stnictures used in the implementation. Sections 3.6 deais with the process
characterization issues and Section 3.7 presents the results obtained of the characterization
of the test structures. Finally, Sections 3.8 and 3.9 discuss the integration of a
Z E 2 p ~ 0 ~ ceil into a CMOS compatible process module and m e r scaüag of
the memory ceU-
3.2 Process Flow
The fabrication process flow is presented in this section. The dZficulties
occurring in the process implementation and methods of resolving them are described.
The starting material for this process is l-m, p-type <100> orientation
silicon. This optimized process flow uses a 0.8pm minimum line width and involves
seven masking steps. It is compatible with conventional CMOS processes.
3.2.1 Process Specifications
The cross-sectional diagram of the proposed Z~PROM celi is show in
Fig. 3.1. Device parameters such as the thickness of both polysilicon layers (360a)
used in the formation of the control and floating-gates are k e d by the requirernent
for compatibiiity with existing CMOS processes.
The thin-gate oxide is 85A thick, and the ON0 interpoly dielectrïc has a
200A equivalent oxide thickness. The pfnC Zener junction is designed to have a
high p+ concentration (-10~~cm-~). Simuitaneously, the n+ doping concentration in
the drain region must counter-dope the pf region in the vertical direction across
the Zener junction. An alloy of Al+2%Si is used for metaliization to avoid aluminum
spüces through source and drain junctions. The junction depth of the source and
drain is designed to be 0 . 3 p . The p+ Zener is 0 2 5 p deep. Process parameters
such as the time, temperature, dose and energy associated with diffusions, oxidations
and implantations are designed to achieve the process specification and to be
compatible with CMOS processes.
Gate Oxide @SA) ,pl Boating-gate (360d)
Figure 3.1 Cross-sectional diagram of the proposed ZE*PROM ceil
3.2.2 Process Flow
Cross-sectional diagrams at various stages of the process are illustrated in
Fig. 3.2. A total of seven masks are used for this experimental process. A detaüed
description of the fabrication process is given in Appendix A and include a discussion
of each step of the process-
To prepare the wafers for LOCOS isolation, a thin oxide is grown on the
bare wafers and a Si3N4 layer is deposited in the LPCVD. The device active
area is then defined with mask #1, as shown in Fig. 3.2(a). Dry etching of the
Si3% and oxide layers is carried out next, as shown in Fig- 3.2(b). Wet oxidation
is then used to grow a thick LOCOS oxide, as shown in Fig. 3.2(c). A wet
etch is carried out to remove the oxide and Si3N4 layers in the active area and
a thin gate oxide is then grown foilowed by a boron implant which is used for
threshold voltage adjustment, as show in Fig. 3.2(d).
The first polysilicon layer for the floating-gate is obtained by LPCVD of
arnorphous silicon followed by an annealing step. The use of amorphous silicon
rather than polysilicon results in a smoother surface to grow the interpoly dielectric.
Improved surface smoothness, aüows a thin oxide to be grown on this heavily
doped amorphous silicon without sacrificing the quality of the oxide. A phosphorus
implant is used to reduce the sheet cesistance of the floating-gate as shown in
Fig. 3.2(e). A Rapid Thermal Oxidation (RTO) is performed for crystallization of
the amorphous silicon layer, to redistribute phosphorus in the polysilicon and to
grow a thin oxide on the polysilicon. This oxide layer is necessary for better
adherence of photoresist into polysilicon. The first polysilicon layer is pattemed
with mask #2 to serve as the floating-gate as shown in Fig. 3.2(f). M e r this
step, the polysilicon layer covers only the device active area as shown in Fig.
3.2(g). The reason for this is to remove the first polysilicon fkom the LOCOS
and thus avoid overlapping of the first polysiücon Iayer by the second one anywhere
outside the device area.
Next, the interpoly ON0 dielectric is formed The second polysilicon layer
is forrned by LPCVD of amorphous silicon followed by a phosphorus implant
as in the case of the first poly layer as shown in Fig. 3.2@). Then, the second
61
polysilicon layer is pattemed to serve as the control-gate by using mask #3 as
shown in Fig. 3.2(i). A thick LPCVD oxide layer is used as a mask in the
Reactive Ion Etching @IE) of the polysilicon and ON0 layers as shown in Fig.
3-20}. During the etching of the polysilicon layers and the interpoly ONO, the
thick mask oxide is exposed to the correspondhg etching gas arnbient. Therefore
the thickness of this mask oxide is chosen to withstand the RIE etchhg procedure
of the entire gate s t m c m
After forming the stacked gate structure. the p* region of the Zcner junction
and the p+ contacts to the substrate are implanted using mask #4 as shown in
Fig. 3.2(k). A LPCVD oxide layer is then deposited. It is used for the formation
of the Side Wdl Spacer (SWS) as shown in Fig. 3-20). This oxide is densified
during the anneding step used for pf regions drive-in. It is followed by an RIE
anisotropic oxide etch to form the SWS as show in Fig. 3.2(m).
The source and drain regions are implanted through mask #5 after the
formation of the SWS as shown in Fig. 3.2(n).
Mask #6 is used to define the openings in the oxide for metal contacts
to the substrate, source, drain and control-gate as shown in Fig. 3.2(0).
Mask #7 is used for metai patteming as shown in Figs. 3.2(p) and (q).
The front and rear views of the finai structures obtained are shom in Figs. 3.2(r) and (s).
A description of the process steps for the ZE~PROM fabrication is presented
in Table 3.1.
Photoresist
p-substrate
p-substrate
Doping (Phosphorus)
amorphous silicon p-substrate
gate oxide
7 Photoresist
p-substrate Y
polysilicon psubstrate
Doping (Phosphonis) +
1 p-substrate 1
I p-substrate I LPCVD Oxide
I
p-substrate - Gate Oxide
Do~inn of D+ Zener reeion (Boron) Photoresist
p-substrate
LPCVD oxide
1 p-substrate
p-substrate
Photoresist
p-su bs trate I
1 LPCVD oxide p-su bstrate
1 p-substrate 1
p-substrate
(0 source drain
p-substrate
source drain
p-substrate
(s)
Figure 3.2 Cross-sectional diagrams of the ZE~PROM process
I Define regions for
LOCOS isolation
I Sacrificial oxide growth
l Gate oxide growth
I - - --
Threshold voltage adjust-
ment
I Deposition of the first
polysilicon layer
Doping of the 6rst pol-
ysilicon layer
Redistribution of phos-
phorus in the gate
Dry oxidation, 950°C for 60 minutes,
thicknesc-30d
Photolithography (mask #l), Dry etch-
ing of aitride and oxide
Wet oxidation, 1 10°C for 85 minutes,
thiclaiess=7~0A, Wet etch of oxide,
nitride and oxide
Wet oxidation, 1000°C for 30 minutes,
thickness= 1 OOO& oxide wet etch
Dry oxidation, l 100°C for 5 minutes,
90%N2, 8%02, 2%HC1, thickness=85A
Boron implantation, dose=4x 10'~cm-~,
energy=30KeV - --
LPCVD amorphous silicon @560°C,
thickness=360d
Phosphorus implantation, dose=8x lois
cm-', energyr30KeV
RTO @llûû°C for 30 seconds, 0'
ambient
-
Fig. 3.2Ca)
Fig. 3,2(b:
Fig. 3.2(c:
Fig. 3.2(d)
Fig. 3.2(e)
Defining regions of the 1 Photolithography (mask#2), wet etch
floating-gate ( of oxide and poly
Bottom oxide of ON0
P w t h
Dry oxidation, 950°C for 8 minutes,
86%N2, 12%02, 2%HCl, thick-
ness=80A
Deposition of nitride
layer
LPCVD @750°C for 10 minutes, thick-
n e s s = t ~ A
Top oxide of ON0
&ro*
Wet oxidation, 950°C for 40 minutes,
thickness=4d
Deposition of the second
polysilicon Iayer
LPCVD amorphous silicon @ S60°C,
thickness=3600A
Doping of the second
polysilicon layer
Phosphorus implantation,
dose=8~10~~cm-~, energy=30KeV
Depositionofmaskoxide
for RIE of gate structure
LPCVD oxide deposition thick-
ness4OOOA - -
Redistribution of phos-
phorus in the gate
--
RTA @llOO°C for 30 seconds, NZ
arnbient
Defining the gate stmc-
ture
Fig. 3.2(f)
Photolithography (mask #3), RIE of
polysilicon, oxide and nitride layers
Screening oxide deposi-
tion
- -
Fig. 3.2(i)
LPCVD oxide, thickness=5~A -
Fig. 3.20)
Defining the p+ regions 1
1 for Zener and substrate
contacts
Photolithography ( m a s a ) , Boron
implantation. dose=8x 1 0 l4d2 ,
energy=2SKéV
Deposition of oxide for
sws LPCVD oxide, thickuess=3~00A
Re-oxidation and activa-
tion of boron
Dry oxidation, 950°C for 15 minutes,
thickness=100O,k,
Formation of SWS RIE of the oxide - - - -
Screening oxide deposi- 1 LPCVD oxide, thiclaiess=~00A
tion --
Defining the n+ regions
for source and drain
Photolithography (mas k#5), Arsenic
implantation, dose=% l~~'crn-~ ,
energyd 20KeV - . . - - -
Deposition of oxide for
isolation
LPCVD oxide, thickness=88000~
Activation of Arsenic Dry oxidation, 1000°C for 20 minutes,
thic kness= 1 OOOA, -- - ---
Contact window opening Photolithography (maskW), oxide wet
Figure #
Fig. 3.2(k)
-
Fig.
-
Fig. 3.2(0)
- -- - - -
Fig. 3.2(p) Metallization Sputtering of M+2% Si, thick-
nessû.8prn
TABLE 3.1 ZE'PROM ceii process summary
The entire process 0ow was simulated starting from the LOCOS oxidation
up to the metailization Ievel. Al1 the furnace oxidation and annealing steps, the
time steps needed for stabilizing and ramping up and down of the temperature
were included in the simulation to describe the actual process condition. The final
doping profiles across the drain and the channel of the device are presented in this section.
Fig. 3.3 shows the doping profiles in vertical direction throughout the stacked
gate structure and device channel region after ail ion implantation and diffusion
steps in the process. Boron that appears in the control-gate is a result of the
ion implantation used to obtain the pC Zener junction. Boron at the surface of
the substrate is a result of the ion implantation used for threshold voltage adjustment.
This boron implant counter-dopes the phosphorus that had penetrated from the
floating-gate to the channel region through the thin gate oxide.
s t e ~ Proces Figure # 1
De fining the metal lines
S intenng
Photolithography (mask#7), aluminum
wet etch
Furnace anneal in f o d g gas, 4 5 0 ~ ~
for 25 minutes
I
Fig. 3.2(q)
ON0 Gate oxide Contra1 1 Fl~ating )
-- Phosphorus
- - Boron
Figure 3.3 Doping profile of the gate structure and the b u k region. The coordinate
y=-0.58 pm corresponds to the top of the control-gate
The p+n+ Zener junction is designed to have a high concentration in the
p+ region (-1x10~~crn-~). At the same time, the nt doping concentration at the
drain region has to counter-dope the pf region in the vertical direction across
the Zener junction. This is crucial to avoid low voltage junction breakdown throughout
the drain region. The simulated doping profiles in the Zener region in the vertical
direction across n+ and p+ regions are shown in Figs. 3.4 and 3.5 respectively.
- . - - - - . - - - - - - - - - a
- Net Active
- Arsenic
r
IO^^------------ 0.0 0.5 1 .O 1.5 2.0
Distance, y (Microns)
Figure 3.4 Doping profiles along the n+ drain of the Zener Junction. The coordinate
y=Opm corresponds to the silicon surface
Figure 3.5 Doping profiles along the pf region of the Zener junction. The coordinate
E'
y a p m corresponds to the silicon surface
- Net Active r - Arsenic
- - Boron r
- 0-0 0.5 1 .O 1.5 2.0
Distance, y (Microns)
These doping profiles can k used to extract the junction depths of the
p+ and n+ regions of the Zener injector.
The doping profile of the Zener junction dong the lateral direction at
100A fiom the silicon d a c e is show in Fig. 3.6. The doping concentrations
at the Zener juoction is - l x l ~ ~ ~ c r n - ~ which is sufficient to generate hot electrons
at 3.3V applied to the drain as was demonstrated in Szction 2.4. - - -
- - - - coordinate x=0.8pm corresponds
to the edge of the gate stnicture on the drain side
- Net Active
- Arsenic
- - Boron
0.0 0.5 1 .O 1.5 2.0 2.5 3 .O Distance, x (Microns)
Figure 3.6 Doping profile of the Zener Junction in laterai direction at 100A from the
silicon surface. The coordinate x = O p corresponds to the edge of the channel
at the source side
The most important parameters that could be extracted fiom the process
simulation were the oxidation time and temperature, the dose and energy needed
for the Zener junction, the depth and lateral diffusion of the p+ junction and the
nC sourceldrain regions. The diaision of impurities in the channel region and in
the polysilicon layers can also be optimized using the simulator.
3.4 Expeiimental Development of Critical k e s s Steps
The development and characterizaiion of the critical process steps, which
include the 85A thùi gate oxide, the ON0 interpoly dielectnc and the Zener
junction formation are discussed in this Section.
3.4.1 Thin Gate Oxïde
It has k e n reported [2-41 that oxides grown at high temperatures have a
higher defect density than those grow-n at lower temperattues. Oxides obtained by
HC1 oxidation show a significant decrease in defect density when grown at lower
temperatures around 900°C. However, it is also known that below 1060~C the
passivation ability of HCI oxides is not effective 151. Furthemore, charges at the
oxide-silicon interface are not at m-nimm if the oxides are grown at Iow temperatures
[5]. Taking these facts into consideration and noting that the condition of the
oxide-silicon interface is primarily dictated by the oxidation temperature, a high
temperature (1100~~) diluted-oxygen oxidation scheme is an obvious strategy to
obtain high-quality 85A thin oxides.
Thin oxide growth must be slow enough to obtain uniformity and reproducibility.
Incorporating nitrogen together with oxygen and HCI during the oxidation cycle
can reduce the oxidation rate. This method offers an attractive way of growing
very uniform and homogeneous thin oxides in a controlled manner.
For thin Si02 films to be considered for gate insulator purposes, two major
properties are of paramount importance: the level of ionic contamination and the
dielectric breakdown strength. Also, there are two major electrical properties of
the Si-SiO2 interface: fixed oxide charge and interface trap density, which must
be considered. Oxide charges adversely affect the device performance if present
at high densities. Interface traps aiso pose a stability problem since the trapped
charge density can change with time during device life the. 0- dielectric
breakdown strength must also be high for proper device operation.
Optimized gate oxide recipe
The procedure used to grow the thin gate oxide was as foilows. Once the
wafers were cheniicdy cleaned, they were inserted into a 900°C fumace in the
presence of N2. Next, the fumace temperature was ramped up to llûû°C. The
oxidation step was carried out for 5 minutes in a gas mixture of 90%N2, 8%02
and 2%HCL*. The addition of N2 during the oxidation contributes to a slower
growth rate of the oxide thus making it possible to increase the oxidation temperature
to 1 100°C. HCl was intentionaily introduced into the oxidation ambient to improve
both the oxide and the underlying silicon properties. Immediately after the thin
oxide was grown, the wafers were annealed in N2 for 30 minutes at llûû°C.
This annealing step in N2 reduces the amount of fixed oxide charge Q, [6].
Following the annealing, the hmace was rarnped down to 9ûû°C and the wafers
were rernoved from the fimace.
Experimental characterization of the gate oxide
The oxide thickness, substrate doping, the flat-band voltage, effective oxide
charge, interface trap density and threshold voltage were extracted directly from
the experimental high frequency C-V measurements of the MOS capacitors. The
thickness of the gate oxide was also measured by using an automated 6lm thickness
* Flow rates are changed to 02=û.8SUM (Standard Liters Per Miaute), N2=9SUM and HCl=lOSCC/M (Standard Cubic Centimeters Per Minute)
measurement system?. The endurance of the oxide was determined by cychg.
Finally, the breakdown voltage of the gaie oxide was determined fiom the 1-V
characteristics using a voltage ramp technique.
High-Frequency ( MHz) CV measurementsr
The C-V characteristics were measured using a HP4280A lMHz Capacitance
Meter, a Mercury probe and HP9816 controller. The resulting C-V characteristic
for a typicd MOS capacitor is shown in Fig. 3.7.
0.10 1 -4.0 -2.0 0.0 2.0
Gate Voltage (V)
0.35 -
0.30 -
0.25 -
Figure 3.7 Experimentai HF C-V characteristics for the 85A thin gate oxide
Area = 0.0O432cm2 Doping = 1.1 x l ~ " c m - ~ qX = 8 . 7 k Vm = -0.54V
8 .57~10 '~ cni2 D, = 9.13~10 '~ ~ r n - ~ e ~ ' v, =1.2v
The gate oxide thickness is detennined from the capacitance in strong accu-
mulation. The average doping in the surface region of MOS structure is calcuiated
from the ratio of capacitances in strong accumulation and strong inversion 171- The
flat-band voltage VFB is determined as the gate voltage, which corresponds to
the theoreticaily cdcuiated flat-band capacitance using the extracted value of the
doping concentration. From Vm and the mercury-silicon work function difference,
the effective oxide charge at Elat-band Q, and the interface trap density Di, are
calculated. The low values obtained of Q, and Di, serve as a measure of the
quality of the thin oxide. A large number of samples were measured for this
experiment and the resulting parameters exhibited a variation of 5%. The results
from wafer to wafer also exhibited a variation of S%.
Cyc iing:
Before analyzing the capacitor structures for destructive breakdown, they
were continuously cycled for 25,000 tirnes or more by applying a steady voltage
repeatedly between the two capacitor plates. This test was used to determine the
endurance of the thin oxide Iayer and its ability to sustain the voltage Ievels
applied during multiple cycles of progamming and erasing.
In a real ZE*PROM stmcture, the maximum voltage that would be appiied
across the thin gate oxide is approximately 4V (capacitively coupled from 12V
at the control-gate). For this experiment, the voltage applied across the thin oxide,
was selected to be SV to ensure a certain safety margin.
Randornly selected capacitors were successfully cycled for 25,000 cycles
by applying N repeatedly. The cychg results were consistent fiom wafer to wafer.
Further characterization of the capacitor structure with the 85A thin oxide
was carried out by rarnping up the gate voltage in a positive direction to +SV
and then ramping it backwards to OV. Negligiible leakage cumnt (-10-~A/crn~)
was observed under both ramping cycles.
Dielectric breakdown measusemenc
The destructive breakdown voltage in these devices is defined as the point
at which a three orders of magnitude increase in leakage current occurs when
the sample is subjected to a gradudly increasing ramped voltage. The breakdown
voltage histogram shown in Fig. 3.8 was determined by ramping the device
to 1 N and by testing 50 samples on each wafer.
30 1
Unacceptable
3 6 9 12 Critical Breakdown Voltage (V)
Figure 3.8 Breakdown distribution obtained fiom 50 capacitors on a wafer
Out of the total number of samples tested, 90% had a breakdown voltage
higher than 5V. The capacitors that had less than 5V of breakdown voltage were
located on the edge of the wafer.
From these experimental results, it is possible to conclude that the 85A
thin gare oxides grown with diluteci oxygen exhi'bit high breakdown voltages and
low leakage currents.
3.4.2 ON0 Interpoly Dieiectric
The dielectric in floating-gate memones serves two somewhat conflicting
functions. It prevents the stored charge fiom leaking off the floating-gate during
read and storage, and dows charge carriers to 0ow to and from the fioating-gate
during programming and erasing. Since the asperities at the rough floating polysilicon
gate surface create field enhancernent at the tips, the charge leakage is more
likely to occur through the interpoly oxide than through the gate oxide [8]. The
asperities also reduce the average electric field or voltage that is required to
produce a certain F-N tunneling current. Enhanced conduction through the interpoly
oxide limits the use of very thin interpoly oxides desirable for large coupling
ratios. The use of ON0 stacked dielecuics in lieu of a simple oxide is effective
for interpoly oxides thinner than 350A. One advantage of the ON0 stack is that
eiectrons leaking fiom the floating-gate get trapped at the nitride interface, building
up an electric field that opposes fuaher charge Loss. This yields a lower Ieakage
current for the ON0 as cornpared to an equivalent oxide. The other advantages
of ON0 are the larger permittïvity of the nitride as compared to that of oxide
(higher voltage coupling), the smaller defect density and the higher breakdown
voltage of the stacked dielectric as compared to that of a single oxide layer [9].
ON0 layer thickness vs. charge retention
The ON0 interpoly dielectric composition, show in Fig. 3.9, strongly affects
the ce11 characteristics. The charge retention capabilîty strongly depends on ON0
69
layer thickness. To find the optimum thicknesses of the layers, the foilowing factors
were taken into consideration.
Figure 3.9 The ON0 interpoly dielectric composition
Top oxide thickness:
A thick top oxide in the ON0 nIms results in smalier leakage current
for relatively high control-gate voltages [IO] due to the blocking effects of that
oxide against hole injection. Fig. 3.10 shows the energy band diagram of the
ON0 structure. When the top oxide is thin, the holes are easily injected from
the control-gate by direct tunneling 11 11. These injected holes accumulate at the
bottom oxide/SisG interface and enhance the electron conduction in the bottom
oxide. Therefore, a thicker top oxide is needed to reduce direct tunneling of
holes and thereby to reduce charge leakage h m the floating-gate. Typicaüy, the
top oxide is selected to be greater than 30A to block the hole injection from
the control-gate.
Controt Gate
TOP Oxide
Figure 3-10 The energy band structure of the ON0 dieiectric
Silicon Nitride thickness:
The total amount of traps and charge in Si3N4 is dependent on the Si3N4
thickness and such factors also affect the charge retention capability. A thin Si3N4
Iayer leads to enhanced charge loss due to direct tunnelhg of electrons. It is
aiso known that Si3N4 scaling leads to degradation in TDDB (time dependent
dielectric breakdown) characteristics [ 121. Therefore, Si3N4 thickness s hould be carefully
scaled dom. Typically, a nitride layer larger than 70A is used.
B ottom oxide thickness:
Reducing the bottom oxide thickness down to 50A does not lead to a
marked degradation of the charge retention characteristics when the top oxide
thickness is ~ o ~ o A , which is thick enough to block hole injection from the
control-gate. However, the bottom oxide in the ON0 structure must be thicker
dian 50A to block direct eiectron tumehg and to preserve high reliability of
the memory ceU [Il]. Since the oxïde quaiity in poly oxide is Ser ior to the
oxide grown on a single crystaI silicon substrate, the actual limitation should be
thicker than 50k A high quality thin bottom oxide formation will be one of
the most important factors for ON0 scaling.
a Equivaient oxide âbickness of ON0
The equivaient oxide thickness of the ON0 dieleclric capacitor can be
found as follows
XOX = + (&oX/&~)Xsi,N, + XTO (3-1)
where Xox is the equivaient oxide thickness, XBO, XSi,N, and XTO are the
thicknesses of bottom oxide, nitride and top oxide respectively. kx and EN are
the permittivities of oxide and nitride. The ratio of is approximately 112.
This implies that the control-gate voltage coupling to the floating-gate is higher
for the O N 0 capacitor than for the oxide capacitor.
ON0 layer fabrication
The ON0 layer thicknesses were selected according to the limitations described
above. The 80A thin botîom oxide was fabricated in diluted oxygen at 9 5 0 ~ ~
for 8 minutes. The gas mixture used in this step was 86%N2, 12%4 and 2%HCl.
Then a nitride layer of -180A is deposited in the LPCVD at 750°C for 10
minutes. A wet oxidation of the süicon nitride layer [13] was done at 9 5 0 ~ ~
for 40 minutes to obtain a 4-a thin top oxide. Dunng the wet oxidation process,
some of the nitride is consumed and the final nitride thickness reduces to -MOA.
ON0 characterization
To v e w the advantages that ON0 has over oxide, two types of capacitor
structures were fabricated and characterized. The thickness of oxide and ON0
72
layers was selected to be 2û0A. The fabricated capacitor structures were characterized
to measure the leakage current and the breakdown voltage of the dielectrics.
O 2 4 6 8 10 12 14 16 control-gate Voltage (V)
Figure 3.1 1 Leakage current vs. control-gate voltage in ON0 and oxide test structure
Fig. 3.1 1 shows the leakage current of ON0 and of oxide as a function
of control-gate voltage. The measured data shows that at L2V applied to the
control-gate, the leakage current for ON0 is 1.3~10-~A/crn~, whde for an oxide
it is 5 . 5 ~ 1 0 ~ ~ / c r n ~ . n i e ON0 composite clearly has an improvement of approximately
two orders of magnitude compared to the single oxide capacitor structure.
To v e w the breakdown voltage, one hundred capacitors were tested, The
Fig. 3.12 shows the critical breakdown voltage distributions obtained for the ON0
and oxide Iayers. The breakdown fields obtained for ON0 is 10MV//cm whereas
for oxide, it is 8.6MV/cm. This experimental resuit suggests that ON0 has a
better distribution and a higher breakdown voltage compared to the samples with oxide.
Cntical Breakdown Voltage (V)
Figure 3.12 Critical breakdown voltage vs. the number of oxide and ON0 dielectric
capacitor samples
+ + 3.4.3 The p n Zener Junction
To obtain a Zener junction in the ZE'PROM cell, heavily doped n and
p regions are fabrîcated using boron and arsenic implants. After the fonnation of
the gate structure as shown in Figs. 3.2(j) and (k), a boron implant of 8 ~ 1 0 ' ~ c r n - ~
dose and 25KeV energy is used. A side wali spacer (SWS) is formed next by
depositing 3500A of LPCVD oxide, denseing the oxide O 950°C for 15 minutes,
and dry etching as show in Figs. 3.20) and (rn). The furnace cycle used to
densifi the oxide aIso drives-in the boron implant.
Then n+ region is formed by using arsenic at a dose of ~ x 1 0 ' ~ c m ' ~ and
an energy of 120Kew The wafers are then anneded in dry oxygen at 1000°C
for 20 minutes. This annealing step drives-in the implanted arsenic ions to form
the n+ region. This drive-in step is very important to form the Zener junction
undemeath the floaîhg-gate. This is necessary to increase the probability of coilecting
hot electrons by the fioating-gate during prognimming. The SWS is used to avoid
counter-doping of the entire p+ region.
Zener junction characterization
The experimentai 1-V characteristics of the reverse biased Zener junction
are shown in Fig. 3.13. Cornparison between simulations and experimentai resuits
led to the conclusion that the doping concentration in the pf region of the Zener
junction is -10'~crn'~. The 1-V characteristics of Zener breakdown also show that
the breakdown current h of the junction is -60pNpm of channel width at 3.3v
This is larger than the simulated drain current (40CLA/pm of channef width) obtained
for the ZE~PROM ceii ( c d A) in Chapter 2. The larger measured drain current
is a result of having a slightly deeper pt region than estimated by simulations.
Figure 3.13 Experimental breakdown characteristics of the p+n+ junction
75
3.5 Layout Ruies
The minimum photolithography resolution for the experimental fabrication
process is 0 . 8 ~ . nie layout design niles are based on the minimum feature
size and the mask alignment tolerance lmposed by the fabrication facility at the
University of Toronto. The process has 7 masks and is descrïbed in Table 3.2.
TABLE 3 2 Description of the masks in the ZE*PROM process
device well
2
3
FGPOLY (pos)
4
CGPOLY (pos)
5
6
7
floating-gate
PZENER (neg)
1
control-gate
NDEV (neg)
CON (neg)
MET1 (pos)
1
pf Zener 3
- --
source/draîn doping
contacts
metal lines
1
3
6
The Iayout design d e s for a ZE'PROM ceIi are iiiustrated in Fig. 3.14
and are summarized in Table 3-3.
LOCOS FGPOLY CGPOLY PZENER NDEV CON
Figure 3.14 Layout design rules for a 0.8pm ZE~PROM ce11
The p+ Zener region at the drain side is irnplanted using a mask (PZENER)
that covea ody part of the channel width and partiaily overlaps the LOCOS
area. This EXENER mask and the implantation process step for p+ Zener region
are the only additi0na.I steps introduced to the existing CMOS process.
TABLE 3.3 Layout design des for the ZE~PROM cell
The test mask layout used for investigating the Z~PROM cells as well as the arrays
is depicted in Fig. 3.15, The e-beam mask plates were fabncated at Northern Telecom. The
test masks layout consists of twenty seven single devices, four 8x8 arrays and two 4x4
arrays. Test structures are used to measure the sheet and contact resistance of the layers, for
spreading resistance profiling measurements and to characterize the device structure using
SEM.
Mask
LOCOS
FGPOLY
CGPOLY
PZENER
NDEV
CON
MET I
Layout nile #
1-1
1.2
2.1
2.2
3-1
3.2
3.3
3.4
4.1
4.2
5.1
6-1
6.2
6.3
7.1
7.2
7.3
Description
Minimum width of device active areas
Minirnurn length of device active areas
Minimum width
Minimum overlap to LOCOS
Minimum width
Minimum overlap to LOCOS
Minimum overlap to PZENER
Minimum overlap to CON
Minimum width
Minimum overiap to LOCOS
Minimum overlap to LOCOS
Minimum contact sue
Minimum spacing to CGPOLY
Minimum spacing to LOCOS
Minimum width
Minimum spacing
Minimum overlap to CON
Dimen- sions (pm)
6
12
0.8
2
0.8
2
0-4
2
4
2
2
2x2
2
2
4
2
L
Figure 3-15 Test masks layout used in the fabrication process
The foiiowing is a description of the stmctures included in the test chip:
(a) Twenty seven individuai 2 E 2 p ~ 0 ~ ceiis with gate lengths of 0 . 8 p , lp,
l.Spm, 2pm and 3 p with 2546, 50% and 75% of device width covered by
the Zener injector.
(b-e)Four 8x8 NOR type memory arrays with 0.8pm and 1Spm gate lengths and
30% to 50% of device width occupied by the Zener injector.
(f) Two 4x4 NOR type memory arrays with 0 . 8 ~ and Ipm gate Iengths and
50% of device width occupied by the Zener injector.
(g) Five structures to measure sheet and contact resistances using the transfer Iength
method.
(h) A MOS capacitor for C-V proliiing,
(i) Test structures to characterize the SWS and stacked gate using SEM.
By using the resolution and the alignment tolerance (k) ailowed by the
technology, a simple set of layout d e s can be generated for the design of ZE~PROM
cells and arrays. These h based layout rules are given in Appendix B.
The rnicrograph of the test mask implemented to investigate the E~PROM
ceils as well as the arrays is s h o w in Fig. 3.16. The micrographs of a ZE*PROM
ceiI and a NOR type array are shown in Figs. 3.17 and 3.18 respectively- The
word-iines of the array are accessible through polysficon lines that contact the
control-gates of the cells, and the drain and source regions are connected to
bit-lines and source-lines respectively.
Figure 3.16 Micrograph of the test mask (area doooprn x 6100pm)
Figure 3.17 Micrograph of a ZE*PROM c d
Figure 3.18 Micrograph of a ZE*PROM array
The SEM micrograph of the ceU cross section across the width of the
device is shown in Fig, 3.19- It shows the gate structure including the control
and floatîng-gates, the SWS, the p+ and n+ dinusions used for the Zener junction
at the drain, and the LPCVD oxide layer used to isolate the devices from the metal Iayer.
Figure 3.19 SEM micrograph of ceii cross section across the width of the device
The typical process and eleçtncal parameters obtained from the fabncated
test structures are Listed in Table 3.4. The layer thicknesses of the stacked gate
structure were measured using the NanoSpec 4M)O model and the Alpha Step
200 surface profiler. The sheet resistance of the polysilicon gates was measured
using the 4-point probe - model 1OlC. The HP4155A was used to measure the
electrïcal parameters such as the threshold voltage, leakage currents in the insulators
and the chaiinel current. In addition to these types of measurements, the quality
of the gate oxide and ON0 layers were verified through C-V measurements using
the HP4280A Capacitance Meter and the HP9816 controller.
83
TABLE 3.4 Summary of the ZE~PROM process and electrical parameters
Parameter
r
S tarting material p- type <100>
Gate oxide thickness
ON0 bottom oxide thîckness
1 ON0 nitride thickness
ON0 top oxide thickness
Polysilicon floating-gate thickness
Polysilicon controI-gate thickness
1 Substrate doping concentration after V, adjusûnent
1 N+ SourceDrain junction depth
Source/Drain region doping concentration
pf region junction depth
1 PC region doping concentration
1 Metal layer thickness
1 control-gate Line width - - -
[ Poly silicon gate sheet resistance
1 V, with respect to the control-gate
1 Gate oxide leakage current
1 ON0 leakage current
Value
3.7 Characterization of the Implemented ZE~PROM cell and array
The characterizaion of the cells and arrays included:
programming and erasing characteristics
program and erase unifonnity
1-V characteristics
drain, gate disturbs and soft-write characteristics, and
writekase endurance
The HP4155A serniconductor parameter analyzer was used to measure the
DC electrical characteristics of the fabricated test structures. The HP8180A data
generator and HP8182A data analyzer were used to generate the voltage pulses
used in programming, erasing and cycling of the memory cells and analyze the
performance of the cell.
3.7.1 Progrlimming
To program a cell in the memory array, the selected bit-line is comected to 3.3V,
the substrate is grounded, the metai source line is left floating and 12V is applied to the
selected word line. This yields a srnail drain current h of 60pAlpm of device width. The
results of the programming characteristics are shown in Fig. 3.20. In the fabricated test
devices, it was possible to program the cells within -850ns to achieve a V, of 4V. This pro-
gramming speed was slower than the 60011s expected from simulations described in Chap-
ter 2. This cm be attributed to possible discrepancies between the mode1 parameters used
in the simulator and the processing conditions encountered in the experimental work.
However, the trends codïrmed by simulations and experimental results show a significant
improvement in prograrnming time when compared to conventionaï flash ceus [14], which
require tens of microseconds for programming at a N supply.
8 1
Programming Time (psec)
Figure 3.20 Threshold voltage vs. prograrnming time of a ZE~PROM ce11
In a fabricated ZE~PROM cell, a bias condition ofVs=3.3V and Vcg=-12V is sufti-
cient to erase the ce11 within 50ms as shown in Fig. 3.21. The celi is erased with F-N tun-
neling of electrons from the floating-gate to the source [Hl. The drain of the cell is left
fioating during the erase operation. The erasing speed is higher in the beginning of the
erase operation, but starts to decrease as the floating-gate becornes less negative and the
electric field in the gate oxide is reduced. The experimentd results show that the Vt of the
cell reduces to 1.7V after 5ûms of erasing tirne. However, as al l cells in a sector are erased
86
at the same time, the per bit erase time becornes very short- The erase time can be M e r
decreased by using higher voltages at the source and at the control-gate, and by decreasing
the thickness of the gate oxide and the interpoly ONO. When selecting the source voltage,
care must be taken to avoid the source to substrate junction breakdown- Since the source
curent during erasure is very smaü, the source voltage cm be generated on chip without
the need for an additional power supply-
6
O ! 1 o - ~ 1 oi6 1 oL5 10" 1û3 1 O-2
Erase Tirne (Sec)
Figure 3.21 Threshold voltage vs. crase time of a ZE~PROM ceU
3.7.3 Program and erase uniforxnity
When orthogonaily programming a ZE~PROM array, it is very important
that al1 cells connected to a common bit-line have a uniform prograrnmed V,
distribution. Otherwise, the programming time of the cells will be dominated by
the slowest prografnrning ceii. Therefore, it is necessary to have a tight control
of the process parameters throughout the array- Another requirement is that the
characteristics of the cells be unifonn fiom wafer to wafer and lot to loti In
particular it is very important that the program and erase characteristics be uniform.
Therefore, an evaluation of the uniformity of the prografnmed and erased threshold
voltage across the 8 x8 Z~PROM arrays was carriid out.
Figure 3.22 Programrned and virm V, distribution for a 8 x 8 E~PROM array
Fig. 3.22 shows a typical V, distribution of programrned and virgin ceiis
(before programming for the first tirne) in a 8x8 array. The programrned V, was
obtained by applying Vd=3.3V and V@2V for a duration of lps. In general,
the programmed V, distribution was found to be spreading within a 1V range
while the virgin V, was u n i f o d y distributed. The programmed V, variation within
the array is due to variations of doping levels of the Zener junctions, Wp+, gate
oxide and ON0 layer thicknesses, and aügnment tolerances. Towards the centre
of the array, the distribution is more unifonn compared to the edges.
3.7.4 Reading
Since the p+ region adjacent to the drain exhibits a low breakdown voltage, which
contributes to soft prograrnmiog, the dedicated metal source-he can be used in the read
operation. Experimental I-V characteristics for a typicai ZE~PROM ceil are show in Fig.
3.23. The ceil has a device widrh of 6 p in which 50% is occupied by tbe p+ Zener region
attached to the drain. Similar to the simulated 1-V characteristics the source voltage
changes from O to 2 . N and the control-gate voltage is applied with OV, IV, 2V and 3.3V.
In the saturation region, the measured 1-V characteristics show a steeper slope [ l q due to
the capacitive coupling between the source region and the floating-gate. This slope is con-
sistent with the simulation ~su l t s and the analytical model developed in Chapter 2. The
measured read current for V,=lV and V,g3.3V is - 1 0 0 p N ~ of channel width. This is
slightly higher than the value obtained h m device simulations. The larger read current in
the fabncated ceils could be due to a variation of the Wp+, which might be occupying Iess
than the intended 50% of the channel width.
0.15 1 I
Figure 3.23 Read current vs. source voltage as a function of control-gate voltage
89
The read current dependence on the width of the p* dinusion is depicted
in Fig. 3.24. These were obtained from 3 cells that have 6pm channel width in
which 25%. 50% and 75% were occupied by the p+ Zener region. m e n the
width of the p+ region is increased, the channel width available for reading is
reduced and the read current is Iowered-
Figure 3.24 Read current vs. source voltage as a function of the p+ diffusion width
3.7.5 Disturb Characteristics
For a memory cell to be functional, it must be able to withstand dl
disturb conditions that arise when it is implemented in an array. These disturb
conditions acise primarily when another cell on the same bit-line or word-line is
being programmed and the celi is exposed to either high bit-line or word-luie
voltages as illustrated in Fig. 3.25. The ceii must remain immune ffom disturb
for the total time that it takes to program all cells along the cornmon bit-line
90
and word-luie I l l - Another important disturb condition is sol3 writùig of the celI
during reading of an erased ceil. In general, the ceIl is expected to be able to
read continuously for 10 years with only a srnail increase in threshold voltage.
sL1 S L ~ sL3 (Floating) (OV) (OV)
Figure 3.25 Drain and gate disturb conditions in the unselected ceiis (Q, S, T, U and V) of
a ZE*PROM array
Drain disturb
When a bit-line in the array is connected to 3.3V to program selected memory
cells, the unselected cells dong the bit-line (V@V and Vd=3.3V) will have hot holes
injected into their gate oxide (drain disturb) as iliustrated in Fig. 3.25, for device Q 11 81.
Drain dishirb characteristics, due to the ptnt junctions, in unselected programmed and
erased flash ZE~PROM ceils are show in Fig. 3.26.
r o - ~ i o - ~ i o - ~ IO-L io" r o+l i O+* Stress Time (Sec)
5 -
4 - z' V
$ 3 -
2 -
Figure 3.26 Threshold voltage as a hinction of stress time to illustrate drain disnirb
characteristics, due to the p+n+ junction, in unselected programmed and
erased ZE~PROM cells
vcg
1 vptioatir,g *v~=~.sv
Vsub
The programmed Bas6 Z*PROM cells exhibit a soft erase afkr a drain disturb
tirne of -5ûûms while the erased cell remains undisturbed after LOOS. This is due to the
- w -
fact that the Roating-gate potential of the programmed ce11 is lower than that of the erased
ceil leading to hot hole injection in the programmed cells. This undesired injection of hot
1 -
holes can be minimized by the orthogonal programming technique. For example, in this
Erased Ce11
8 x 8 test array, the maximum drain dishub time using orthogonal programming is 8 times
less than in a conventional word-line by word-line programming technique.
Gate disturb
When the word-line in the array is connected to 12V to program selected memory
cells, the unselected ceiIs dong the word-line (Vcg=12V and Vd=ûV) wiil be exposed to
the gate disturb condition as shown in Fig. 3.25. In this condition. unprogrammed ceils
can have electrons tunnel fiom the nç drain and source regions into the floating-gate
increasing the threshold voltage of the ceU. If the ceii is already programmeci, the stored
electrons can tunnel from the floating-gate to the control-gate through the ON0 interpoly
dielectric thus resulting in a reduced threshold voltage for the celi. Fig. 3.27 indicates t y p
ical gate disturb conditions for initidiy programmed and erased E~PROM cells. A minoc
gate disturb in the erased ceus can be observed after -10s with 12V appîied to the gate.
Since the equivalent oxide thickness of the O N 0 interpoly is -200A, a very smali gate dis-
turb was observed (after 1s) in the programmed ceus [18].
3*0i Erased Ce11
t
io-2 i il-1 160 io;' 1 i d 1o4 id Stress Time (mSec)
Figure 3.27 Threshold voltage as a function of stress time to demonstrate the gate disturb
(undesired programming and erasing) of the unselected erased and
programmed ZE*PROM cells that share a cornmon word line
These excellent drain and gate disturb characteristics c m be attributed to the use of
low Vd and h during programming, and the high quality of the gate oxide and ONO in the
fabricated Z~PROM ceils.
With the orthogonal programming technique, the cens must be able to endure the
word-üne stress for the total times that it takes to program al l the cells dong the word-line.
0 Soft-write
Although the read voltages applied to the source and to the control-gate are much
below the programming voltages, there is a probability for some programming to occur. In
general, a flash memory ceil must be immune from significant threshold voltage shifts for
10 years of continuous reading of the device [19]. Since it is impossible to perform tests of
this duration of time, a method that estimates and extrapolates the resdts in 10 years is
used for this test. This is doue by obsenring the speed at which the Vt increases for larger
source voltages and extrapolating to actual read voltage. When voltages above 2V are
applied to the source terminal, Vt shifts on the order of 0SV (soft-wnte endurance) can be
obtained in short time periods. M e n this time is plotted versus the inverse of the applied
source voltage, a straight line can be achieved.
Fig. 3.28 shows the t h e to cause a threshold V, shift of 0.5V for V, values of 3.3V,
4V and SV. To v e w the impact of temperature on the sof't-write endurance characteris-
tics, the measurements were carried out at rwm temperature and at 80°C. The maximum
allowed read voltage on the source was detennined by extrapolating the curves to a limit
of 10 years. Soft write endurance during the read cycles indicates a greater than 10 year
94
lifetime for both temperatures At higher temperatures, it takes longer to generate an
increase of 0 . N in V, This is due to enhanceci thermal scattering at higher temperatures
which in turn reduces the energy of the electrons that contribute to the ceU programming
P O 1 -
Figure 3 -28 Soft write time (time to cause a V, shift of 0.5V) vs. the inverse of source
voltage appiied during reading of a ZE~PROM ceU at two dinerent
temperatures
3.7.6 Endurance Characteristics
The endurance testing of flash memory celIs is extremely time consumuig and
requires sophisticatcd testers to be accomplished efficiently. However it was possible to
perform endurance testing that monitored the threshold voltage window of the ZE*PROM
cell as it was cycled. The Vt window closure is a common concem for d flash memories
and arises from electrons being trapped in the oxide as they move through the oxide. The
trapped negative charge increases the barrier to electron flow through the oxide and
reduces the V, shift for a given applied programming or erase pulse. The result is that the
difference between the programmed and erased Vt begins to decrease until there is insufti-
cient rnargin for the data to be reaci accurately.
The typical number of write/erase cycles for this memory cell is shown in Fig.
3.29. The ceil can be programmed to 50,000 cycles without catastrophic failure. The
50,000 cycle limit has been determined by the testing time constrains. No V, degradation
is o b s e ~ e d for the initial 10,000 cycles. However, after this, a Vt window closure is appar-
ent as both programmed and erased V, values deviate fiom the s W n g values. The
observed closure represents a signifiant improvement in endurance as compared to previ-
ously reported results [21]. The V, window closure of the p r o g r m e d and erased States is
due to electron trapping in the gate oxide at the drain edge as weU as at the source edge
during hot electron progrâII1IIUIIg and F-N tunneling erase.
io" 10' 102 103 104 id Write/Erase Cycles
Figure 3 -29 Threshold voltage vs. write/erase cycles to verify the endurance
characteristics of the ZE*PROM ceU
While endurance to 100,000 cycles remains to be verified, the results can be con-
sidered encouraging fiom the point of view that no gate oxide failures were observed for
all the cells that were tested. The endurance characteristics were very consistent in al1 the
cells that were tested exhibiting similar characteristics to those shown in Fig. 3.29.
3.8 Integrating the ZE~PROM array in a CMOS process module
To implement the ZE~PROM ceil in a 0.8p-m CMOS process, the folIowing
requirements must be taken into consideration. The low voltage and high
voltage (HV) transistors in a full process require two different gate oxides. The
inclusion of the pf region of the Zener injector requires an additional masking
step, an implantation and a re-oxidation to anneal the damage caused to the edge
of the gate oxide. Fig. 3.30 shows a modïfied CMOS process, in which the
additionai ZE~PROM steps are shaded. The different process steps are explained
after the figure.
97
- -
Well formation p-well n-weli
define active area LOCOS charnel stop implant
field oxide growth - I I
gate oxides for LV Gate oxide gr'* and HV transistors
maclcing step 4, ~ ~ P P R M cen removù of oxicie I
1 definition tunnel oxide growth)
Poly 1 (Gate) poly 1 deposition doping and etch
LDD implant n- implant for the NMOS transistors I
8) P+ Zener region I definition
9) P+ Zmer implant r boron irnplautation reoxidation
SWS formation oxide deposition and RIE
SourceDrain implantation
arsenic implantation reoxidation
etching of the contact contact holes and 1
Figure 3.30 Process flow of a modified CMOS process in which the additional
2 ' E 2 p ~ 0 ~ steps are identified (shaded)
1) Weii formation:
N-well and P-weiI formation are done at the beginning of the process in
which the ZE~PROM cells and peripherai transistors in the address decoders
and sense amplifiers are formed.
2) LOCOS:
The active area definition, a channel stop implantation to Uicrease the V, of
the parasitic field transistors for the safe operation of the HV transistors, and
the field oxide growth are performed at this step.
3) Gate Oxîde:
During this step, the gate oxides are grown for the LV and HV transistors.
The threshold voltage is also adjusted after this step.
4) E~PROM cell definition: (additional for ZE~PROM option)
A masking step is used to define the memory cell area and the oxide grown
on the active area is removed. The growth of a high quality, thin tunnel
oxide (85A) is carried out next.
5) Poly 1:
Polysilicon for the transistor gates, the lower plates of the poly-poly capacitors
and for the floating-gates of the Z J 3 2 ~ ~ ~ ~ cells is deposited, doped and subsequently
defined.
6) N- LDD implant:
The LDD implant for the NMOS transistors is camed out to minimize hot
electron effects.
7) Poly 2:
The ON0 inteply dielectric and poly 2 are forme& Poly 2 is used as the
control-gate of the memory cells and as the top plates of the poly-poly capacitors-
8) P+ Zener region definition: (additional for &PROM option)
An additional masking step is used to define the p+ region of the memory ce11 area.
9) The P+ ZENER implant: (additional for Z~PROM option)
Boron is implanted to define the p+ region in the Zener injecter. Since this
implantation is done prior to the SWS, the gate oxide at the edge of the
poly 1 gets heavily damaged. A damaged gate oxide with weak spots and
trapped charge can enhance trap assisted tunneling and increase the floating-gate
to drain leakage current. The gate leakage is very cntical for the ZE*PROM
ce11 in which the programmed cells might loose the charge stored in the
floating-gate. Therefore, a reoxidation step is needed to anneal the damaged
gate edge. The reoxidation step also improves the gate reliability by thickening
the gate oxide at the edge.
10) SWS formation:
An oxide layer is deposited, annealed and etched to form the SWS in the transistors.
1 1) Source/Drain implantation:
The source and drain of the devices are implanted after the formation of the SWS.
100
12) Metaliization:
The etching of the contact holes and the metallixation completes the entire
process flow.
3.9 Scaling of the CeII
To ver@ the impact of scaiïng down of the minimum line width on the
programrning speed of the ZE~PROM cel.1, the p r o g r d g t h e was measured
on devices with gate lengths varying from 3p.m to 0 .8p . The p+ doping concentration
on al l devices was 10~~crn-~ , the channe1 width of the devices was 6pm and the
ratio of the pf dinusion width to the channel width was 0.5. The devices were
subjected to 12V on the control-gate and 3.3V on the drain. The measured programming
characteristics are plotted together with the simdated results in Fig. 3.3 1, The
discrepancy between the measured and simulated values is due to variations in
ce11 dimensions in the fabricated test structures. When the gate length is reduced
from 3pm to 0.8pm, the programrning tirne drops fiom 4 p to 850ns. Although
the Z~PROM ceil does not depend on channel Length for hot electron generation,
this reduction in programming time can be attributed to the reduction in the
Roating-gate area. When scaling the ZE~PROM c d , both horizontal and vertical
dimensions are scded and the resulting reduction in area yields significant improvernents
in programming tirne. For example, for a 0.25p.m gate length, the expected programmiag
time is 240ns, making the cell viable in hard disk drive applications.
p' doping = 10'~crn-~
W,+lw = 0.5
/-O- .--- Simulation
.-• *O-*
*O*-
O
1 2 3 Gate Length (p)
Figure 3.3 1 Simulated and experimental programmllig t h e as a function of the gaie
length for different flash ZE~PROM cells
Since the pf region in the ZE*PROM ce11 is undemeath the gate structure,
the ce11 c m be scaled to the deep submicron region and still fit in the same
area occupied by a conventional flash memory cell. However, in a Z~PROM
cell, the reduced channel width associated with the presence of the p+ injector
yields a lower read current as compared to a conventional flash memory cell.
This problem can easily be alleviated by decreasing the width of the p+ injector.
In this chapter, issues related to the fabrication process ancl characterization
of the Z~PROM ceil and array were presented. The design of the fabrication
process include the verincation of the process flow ushg two-dimensionai process
simulations and the layout d e s . The process simulation shows that it is possible
102
to fabricate the flash ZE'PROM ceUs and arrays with a CMOS compatible process
with one additionai mask for the p+ region. The three criticai process steps were
developed and their suitability for the ZE~PROM cell was verified by experkental
characterizaîïon-
The experimentai results obtained on the flash ZE~PROM ceïl and array show
promising performance in progr-ng speeds at 33V supply. A programming time of
85ûns was achieved on fabricated test structures. The celi was shown to be immune to gate
and drain disturb whiIe achieving greater than 10 year soft write immunity for Vs=lw
Endurance characteristics showed a graduai window closure starting from 10,000
writelerase cycles. However, the ceils were able to be re-programmed to up to 50,000
cycles without catastrophic failure. The window closure was attnbuted to electron trap-
ping in the gate oxide and is not considered inherent to the ceil structure.
The experimental results demonstrated the feasibility of the Z~PROM ce11 and
array. The high programming speed and low operating voltages make this memory ceiI
suitable for embedded and portable applications. The orthogonal write architecture can be
used to speed up block writes and to reduce drain disturb.
References
T S U P R E M - ~ ~ ~ , "Two-dimensional Process Simulation Programy9, User's Manuai.
Version 6.5, Technology Modehg Associates, Inc., 1997.
E.A. Taft, "The Optical Constants of Siiicon and Dry Oxygen Oxides," J.
Electrochem. Soc., Vol. 125, pp.968-971, 1978.
BE. Deal and AS. Grove, "General Relationship for the Thermal Oxidation of
Silicon," J. Appl. Phys., Vol. 36, pp.3770-3774, 1965.
SM. Sze, '-1 TecITechnology", Chap.3, Second Edition, McGraw-RüI Pubiishiug
Company, New York, 1988.
B.Y. Liu and Y.C. Cheng, "Growth and Characterization of Thin Gate Oxides by
Diial TCE Process," J. Electrochem. Soc. Vol. 131, pp, 683-686, 1984.
D.W. Hess and BE. Deal, 'Effect of Nitrogen and OxygenMitrogen mixtures on
oxide charges in MOS structures,*' J. Electrochem. Soc., Vol. 122, pp.1123-1127,
1975.
K. Iniewski, "High Frequency CV measurements", MRL Data Sheets.
R.M. Anderson and D.R. Kerr, "Evidence for surface asperity mechanism of
conductivity in oxide grown on polycrystalline silicon," J. Appl. Phys., Vol. 48,
pp.4834-4836, 1977.
A. Dibu-Caiole, J. Ranaweera, W.T. Ng and C-A.T. Salama, "ON0 inter-poly
dielectrics for novel flash E~PROM celIs", Canadian Semiconductor Technology
Conference, p.42, 1997.
S. Mori, N-Yasuhisa, T-Yanase, M- Sato, K. Yoshikawa and H.Nozawa,
"Reliability aspects of l0OA inter-poly dielectncs for high density VLSI's", VLSI
Symposium, Digest of Technicd papers, p.7 1-72, 1986.
S. Mori, N. Matsukawa, Y. Kaneko, N. Ami, T. Shhagawa, Y. Suiza, N. Hosokawa
and K. Yoshikawa, "EDM Digest of Technical Papers", pp-556-559, 1987.
[12] S. Mori, Y. Kawko, N.Arai, Y-Ohshuna, H-Araki, IGNarita, E,Sakagami and
K.Yoshikawa, "Reliability study of thin inter-poly dielectncs for non volatile
memory application", International Reliability Physics Symposium, pp. 132-144,
1990-
[13] S-Mori, M-Sato, YMikata, T-Yanase and K. Yoshikawa, "Poly-oxide/nitride/oxide
structures for highiy reiiable EPROM ceils", VLSI Symposium, Digest of
Technicd papes, pAI-4 1, 1984-
[14] B. Dipert and M. Levy, 'Designhg with flash Memory", pp. 25-32, Annabook,
San Diego, 1994.
[15] M. Lenzlinger and E.H Snow, "Fowler-Nordheim tunneling in thermaliy grown
Si02," Journal of Applied Physics, Vo1.40, pp.278-283, 1969.
[l6] S.T. Wang, "On the 1-V characteristics of tloating-gate MOS transistor", IEEE
h s . Electron Devices, Vol. 26, pp. 1292-1294, 1979.
[17] G. Verma and N. Mielke, ''Reliability performance of ETOX based flash
mernories", International Reliability Physics Symposium, pp, 158- 166, 1988.
[18] J. Ranaweera, W.T. Ng and C.A.T. Salama, "Simulation, Fabrication and
Characterization of a 3.3V flash E~PROM array implernented in a 0 . 8 ~
process", Solid State Electronics, Accepted for publication.
Cl91 N. Ajika, M- Ohi, H- Arima, T. Matsukawa and N. Tsubouchi, "A 5V only 16Mbit
flash EEPROM cell with a simple stacked gare structure^', IEDM Digest of
Technical Papers, pp. 1 15- 1 1 8, 1990.
[20] S M Sze, "Physics of Semiconductor Devices", Second Edition, Wiley, New York,
1981.
[2 11 1. Kalastirsky, "Design and fabrication of fast programming flash EEPROM ceIls",
M.A.Sc. Thesis, University of Toronto, A p d 1996.
100
Conclusions
In this thesis, a flash E~PROM ceiI and array that incorporate Zener injector
to achieve a programming speed of the order of severai hundreds of nanoseconds
was presented. This Zener based cell (ZE~PROM), uses hot electrons injected
fiom the drain side to charge its floating-gate and program the cell in 85011s.
Zener induced hot electrons for progranunhg yields very low drain currents by
comparison to the channel hot electron programming method used in conventional
flash E~PROM cells. Therefore, it is possible to program many bits simultaneously.
A method of programming a i l the required celIs in a bit-line (orthogonal programming),
that reduces drain disturb and power dissipation was aiso introduced. The erasure
is performed within 5ûms. To avoid soft programming during reading, the source
region is used instead of the low breakdown Zener junction attached to the drain-
Program and erasure can be done with a 3-3V supply and a charge pump to
generate the I12V to the control-gate to implement all cell operations.
With high speed programming and simple driving circu3s, the 3.3V Bash
Z~PROM design presented in this thesis would be useful in many portable applications.
It also offers potential to replace RAMs and electronic hard drives. The cell
dimensions can be easily scaied to further enhance its performance.
the development of a Zener based ceU that cm be operated from a single
supply voltage (33V), the ceii exhibits an order of magnitude reduction in programming
tirne compared to conventional flash E*PROM cells.
the design and fabrication of a CMOS compatible, double polysilicoo, 3.3V
ZE~PROM array,
the development of an orthogonal programming technique to reduce drain disturbance
and power consumption in Z~PROM arrays, and
the demonstration of a method to prevent soft-write in ZE'PROM c d s by using
the source region for reading.
Further research is necessary to elucidate the following issues that have
not been considered in this thesis, These include:
developing flash Z*PROM ceil that operates at voltages below 3.3V, and
çtudying the possibility of using the ZE~PROM cell for multilevel storage
APPENDIX A
Flash ZE~PROM Fabrication Process Description
A detailed description of the ZE~PROM fabrication process is given below.
This description is intended to serve as a reference for future work on the ZE~PROM
ceils. The wafers used in the fabrication process are p-type with resistivity IR-cm,
<LOO> orientation and 4" diametet Steps such as cleaning, photolithography and
photoresist removal are standard proceuing steps. Ail the steps described are optimized
to achieve the appropriate specifications for the Z~PROM cells and arrays.
The wafer cleaning process uses the 3-step cleaning method described in
UTICL Data Sheets. The following solutions in which the ratio is given by volume
are used. To remove heavy organic contaminants - H2S04:H& = l:l, to rernove
light organic contaminants - DI water:Hfi:NHQOH = 5A:l and to remove inorganic
contaminants - DL water:H202:HCl = 6:l:l are used. The thin oxide grown after
each cleaning step is removed by dipping the wafers in 5%HF for 5 seconds.
The photolithography process step to form 0.8pm line width uses Shipley
positive photoresist 1813. The rest of the photolithography process steps described
in the process flow use photoresist type MICROPOSIT 13501. The developer is
of type MICROPOSIT MF-312. Spinning of the photoresist is done at 6000rpm
-7000rpm for 40 seconds. The pre-bake and pst-bake are done at 90°C for 30
108
minutes. Photoresist development is done in 45 seconds in a solution containing
equai parts of DI water and developer. Acetone is usually used to remove the
photoresist M e r a high dosehigh energy ion implantation, the photoresist asher
machine is used to remove the photoresist-
A.1 Fabrication Process How
Clean the wafers using the standard 3-step cleaning process-
Grow a ~ O O A rhick stress relief dry oxide in the furnace at 950°C for 62 minutes.
Deposit a 1200A thick nitride layer in the LPCVD at 800°C.
Patterning of the device active areas using mask #1 (LOCOS).
Dry etching (RIE) of nitride is done to define regions for LOCOS field oxidation.
The cross section after this process step is shown in Fig. A.1.
Photoresist -+,
p-substrate
Figure A.1 Cross-section after dry etchùig the nitride
Cleaning of the wafers.
The LOCOS field oxidation at llOo°C for 85 minutes in steam. Target oxide
thickness is 7500A. The oxidation of nitride in stearn also produces amnonia
which can d i s e through the oxide to the Si-SiO2 interface and form a nitride
layer. This is known as the White Ribbon or the Kooi effect Cl] and is s h o w
in Fig. A.2. During gate oxidation, these nitride layers significantly reduces the
thickness of the gate oxide preventing the formation of the highest quality gate
oxide. The technique used to eliminate the Kooi effect is to add a step to
grow a sacrificial steam oxide (-1000A) which wouid oxidize the nitride interfafe.
This oxide layer is stripped and the gate oxidation is performed on the nitride
fiee silicon d a c e .
white Ribbon regions
p-substrate
Figure A.2 Cross-section showing the Kooi effect after LOCOS formation.
Cleaning of the wafers.
The growth of -85A thin gate oxide by using a dry oxidation method with
diluted oxygen. A gas combination of go%&, 8%02 and 2%HC1 is used at
I 1 0 0 ~ ~ for 5 minutes. The addition of % during the oxidation contributes to
a slower growth rate of the oxide thus making it possible to increase the
oxidation temperature to llOO°C at 1 atm. HCI is intentionally introduced into
the oxîdation ambient to improve both the oxide and the underlying silîcon
properties. Oxide improvements included a reduction in ion contamination, an
increased dielectric breakdown strength and a reduced interface trap densityi
110
Immediately a€ter the gate oxide is grown, the gas flow is changed back to
N2 to anneal the wafers for 30 minutes at llOO°C to reduce the amount of
fixed oxide charge Q, [2]-
A blanket threshold voltage adjustment implant consisting of boron, dose of
4 ~ 1 0 ~ ~ c m ' ~ at an energy of 30KeV is done after the growth of the gaie oxide.
The cross section after this step is shown in Fig. A.3.
V, adjustment implant
Gate Oxide
p-su bstrate
Figure A.3 Cross-section after gate oxidation and V, adjustment implant
In order to retain the thin gate oxide, a 3-step deanhg without dipping the
wafers in 5% HF is done pnor to the deposition of amorphous silicon.
First poly layer consisting of a 3600A thick amorphous silicon layer is deposited
by pyrolyzing 40% Silane at a pressure of 03Torr h a LPCVD reactor at
560°C. The reason for initial deposition of amorphous silicon is that the surface
is smooth which is important for the interface with the interpoly dielectric.
Improved surface smoothness, ailows a thin oude to be grown on the heavily
doped polysilicon without sacriking the quality of the oxide.
The amorphous sîiicon layer is subsequently implant doped with a phosphorus
dose of 8xl0'~crn-~ at an energy level of 30KeV to d u c e the sheet resistivity.
CIeaning of the wafers.
A RTO (Rapid Thermal Oxidation) at 1 10°C for 30 seconds is done to redistribute
phosphorus in the polysilicon to achieve a constant etch rate, for crystalhation
of the amorphous silicon layer and to grow a thin oxide on the wafers. This
oxide layer is necessary for better adherence of photoresist into polysüicon.
Patterning of the fioating-gate using mask #2 (FGPOLY)
At this stage of the fabrication, a photolithography is done to pattern the polysiiïcon
layer to cover the entire active device area. The undesired areas of polysilicon
above the LOCOS are wet etched after removing the thin pad oxide. Next,
the photoresist and the pad oxide on top of the polysilicon layer are removed.
The cross section after the etching is shown in Fig. A.4.
nC Polysilicon
r LOCOS
p-substrate - Gate Oxide
- - - - - - -- -- - -
Figure AA Cross-section a.€ter patterning of the fioating-gate poly layer.
Cleanin~ of the wafers.
The interpoly dielectnc consisting of an oxide-nitride-oxide (ONO) sandwich
with 200A of equivaient electrïc thickness is then fabrïcated [3]. This optîmized
ON0 thicknss is used to obtain good retention characteristics compared to
polyoxide. The 80A thin bottom oxide is fabncated in diluted oxygen at 9 5 0 ~ ~
for 8 minutes. The gas combination used in this step is 86%N2, 1 2 1 4 and
296HCl. Then a nitride layer of -190A is deposited in the LPCVD at 750°C
for 10 minutes. A wet oxidation of the silicon nitride layer is done at 950°C
for 40 minutes to obtain a 40A thin top oxide.
A second layer of arnorphous silicon is then deposited, doped and annealeci
to form the control-gate. This layer is proçessed with similar conditions as the
first polysilicon layer.
Cleaning of the wafers,
A layer of 4000A LPCVD oxide is deposited to serve as the mask in Reactive
Ion Etching (RIE) of the polysilicon and ON0 Iayers. At this point, ail the
layers that were grown and deposited in the back of the wafers are wet etched.
This is necessary to have a better control of the temperature during the Rapid
Thermal Anneal (RIA) step-
Cleaning of the wafers.
RTA is done next at 1 l00OC for 30 seconds to provide a uniform distribution
of implanted phosphorus and to dense the LPCVD oxide.
Patterning of the gate structure using masW3 (CGPOLY). This photolithography
step patterns the LPCVD oxide. To achieve a minimum of 0 . 8 ~ line width
for the gate structure, Shipley positive photoresist type 1813 is coated and
spun at 6000 RPM for 40 seconds. Mer p s t bakiag the wafers for 30 minutes
at 90°C, the mask is aïigned and exposed for 13 seconds using the Karl Suss
MA4 mask aligner,
The gate structure is then defined by dry etching. First the LPCVD oxide
Iayer is etched using the photoresist as the mask. Then the resist is stripped
and the thick oxide is used as the mask to etch the gate structure. The polysilicoa
Iayers are etched with CI2 gas, and the oxide and nitride Iayers are etched
with Freon gases- Duruig the etching of the floating-gate poly layer, care must
be taken to avoid etching the silicon of the source and drain regions.
Cleaning of the wafers.
A layer of ~ O O A LPCVD oxide is then deposited to serve as the screen oxide
for the next ion implantation- The cross section after this process step is shown
in Fig. AS. , /-- ScreeOing Oxide
p-substrate - Gate Oxide
Figure A S Cross-section after etching of the gate structure
Patterning the p+ Zener region using mask #4 (PZENER). This photoiithography
step patterns the p' region of the Zener junction and of the substrate contacts.
The alignment of the Mask #4 is the most cnticai one in this process.
A boron implant of 8 x l 0 ' ~ m - ~ dose and 25KeV of energy is used next to
form the p+ regions. This boron implant replaces the conventional n-LDD implant
in the CMOS process,
Cleaning of the wafers,
A side waü spacer (SWS) is fonned next by depositing ~SOOA of LPCVD
oxide, denswing the oxide, and dry etching. Tbe funiace cycle used to deus@
the oxide also drives-in the boron implant* The cross section at this process
step is shown in Fig, A.6.
sws --\
I p-substrate
Figure A.6 Cross-section d e r SWS formation
Cleaning of the wafers,
A 500A thick LPCVD oxide is deposited to serve as the screen oxide for
the next ion implantation.
Patternhg of the source and drain regions using mask #5 (NDEV). This
photolithography step patterns windows through which n+ source and drain regions
are implanted Arsenic with a dose of 5~10'~crn-~ and an energy of 120KeV
is used for this implantation. The SWS is used to form the self aügned n+
source and drain regions and also to avoid counter-doping of the p+ pocket-
Since this is a high energy implantation, the photoresist after the implant must
be removed by the asher.
CIeaning of the wafers.
Another LPCVD oxide layer of 8OOA is deposited to use as the isolation
Iayer between the devices and the metal Iayer. The wafers are annealed in dry
oxygen at 1000°C for 12 minutes. This annealing step densifies the thick oxide
and dso drives-in the implanted phosphoms ions to form the source and drain
regions. This drive-in step is very important to detennine the exact location
of the Zener junction, and its junction depai. The cross section after this process
step is shown in Fig. A.7.
r LPCVD oxide -80OChk
p-subs trate
- --
Figure A.7 Cross-section after source/drain formation
116
Patterning of the contact windows using mask #6 (CON). Wet oxide etch is
used to open these contact windows for difision and polysiiicon regions. Then
tfie photoresist is removed and the wafers are cleaned for medlkation~
A 0 . 8 ~ thick A1+2%Si is sputtered on the wafers. The cross section after
this step is shown in Fig. A.8.
1 p-substrate 1
Figure A.8 Cross-section after aiuminum sputtering
Patteming of the metal Lines using mask #?. The Alurninurn layer is pattemed
with photolithography and the undesired areas of Aluminum is wet etched in
a solution heated to 4S°C. The photoresist is removed and sintering is carried
out at 4 5 0 ~ ~ for 20 minutes in fomiing gas to make the contacts. The final
cross sections (program and read) of the device are shown in Fig. A.9 and
Fig. A. 10 respectively.
Figure A 9 Cross-section fiom the program section
p-subs trate
Figure A. IO Cross-section of the read section
[Il 0s. Trapp, L.J. Lopp and R-A. Blanchard, bcSemiconductor Technology
Handbook", Chap- 3, Technology Associates, CA, 1993.
[2] D.W. Hess and BE. Deal, ''Effect of Nitrogen and OxygenINitrogen mixtures on
oxide charges in MOS structures," J. Electrochem. Soc. Vol-122, pp.1123-1127,
1975.
[3] A. Dibu-CaioIe, J. Ranaweera, W.T. Ng and C.A.T. Salama, "ON0 inter-poly
dielecûics for novel flash E*PROM tells", Eighth Canadian Semiconductor
Technology Conference, p.42, 1997.
The h Based Layout Design Rules
The layout d e s for the ZE'PROM array are based on a minimum alignment
tolerance and a minimum line width of 2k, where h~~ These d e s are
listed below.
B.l Active area: (Mask #1, LOCOS)
'i-
0 LLOCOS FGPOLY -----
1- - - - J CGPOLY
1-1 Minimum width=14Â,
1.2 Minimum spacing= 30h
1.3 Minimum overlap of n+ diffusion -
1 -4 Minimum overlap of floating-gate poly=SX T 1 -5 Minhum overlap of control-gate poty=6h 1.6 Minimum width of pt Zenedli 1.7 Minimum overlap of p+ a n e r difhision=5Â.
0 LOCOS FGPOLY
2.1 Minimum width=2k
2.2 Minimum spacing=i6h
B.3 control-gate poly: (Mask#3, CGPLOY)
3.1 Minimum width=2h
3 -2 Minimum spacingr16h
3 -3 Minimum control-gate extension =6x
3 -4 Minimum active area extension of 15k
3.5 Minimum field poly to activm9k
B.4 P+ Zener region and mbstrate contacts: (Mask #4, PZENER)
4.1 Minimum width=8h
4.2 Minimum contact size=6hxdh
4.3 Minimum contact spacing=6h
4.4 Minimum overlap of pC ciBûsiont4h
4.5 Minimum overlap of metal=3X
B.5 Source and drain dithsion: (Mask #5, NDEV) LOCOS FGPOLY CGPOLY NDEV FZENEiR
5.1 Minimum overlap of n+ diffusion= 51c
B.6 Contacts: (Mask #6, CON)
6.1 Exact contact size=6hx6X
6.2 Minimum contact spac ingd
6.3 Minimum control-gate overlapdx
6.4 Minimum active overIap=4h
Minimum spacing to control-gate=%
Metal layer: (Mask W7, MET1) 7.1 7.4
7.1 Minimum width=lOh
7.2 Minimum spacing=8h
7.3 Minimum overlap of poly contacta
7.4 Minimum overlap of active contact=3A
i- LOCOS CON ----- '----J CGrnLY
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