Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications

8/6/2019 Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications

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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010

Device and Circuit Design Challenges for Low

Leakage SRAM for Ultra Low Power

Applications

Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh

Abstract - Ultra low-power applications havegained a lot of attention in recent years. This is dueto the increase in battery operated devices and alsodue to the scaling of CMOS devices. Various CMOS

circuits of low-leakageare in demand one of them isthe SRAM. So, at the present scenario varioustechnologies are used to design the low leakageSRAM. The low leakage SRAM are of primeconcerned as 30% of the total chip consumption isdue to memory circuits. This paper deals with thevarious device & circuit design challenges tooptimize the low leakage SRAM with various designmethodologies and circuit topologies for optimal low power operations. This paper identifies the suitablecandidates for low leakage SRAM for ultra low power applications at device and circuit levels andprovides an effective road-map for SRAM designersto work with its ultra-low power applications.

Key Words Ultra-Low Power, CMOS Scaling,Leakage Power, Static Noise Margin.

I. INTRODUCTION

In recent years the demand for low power deviceshas been increases tremendously. This demand maybe due to fast growth of battery operated portableapplications such as PDAs, cell phones, laptops &other handheld devices. But also at the same timeproblems arising from continuous technology scalinghave recently made power reduction an important

design issue for the digital circuits and applications.The increased importance of power is even morenoticeable for a new class of energy constrainedsystems. Recent interest is in operating the CMOScircuits with power supply voltage below thetransistor threshold operation [33]. As sub-thresholdcircuits can allow ultra low power designs to befabricated on modern process technology. Sub-

threshold operation is applicable to wide range ofapplications ranging from wireless devices,biomedical applications, spacecraft applications etc.Lowering supply voltage to reduce power

consumption is one of the choice of the designers fordesigning low leakage SRAM circuits. However ultralow power design of high density SRAMs in whichthe operating voltage is below the transistor sub-threshold is extremely challenging. In modern SoCswhere total power and total area is dominated bymemory circuits reductions in Vdds for them(memory circuits) can have low leakage power [26].Also by the system integration point of view, SRAMmust be compatible with sub-threshold combinationallogic, operating at ultra low voltages. Ultra-DynamicVoltage Scaling (U-DVS) is another approach toreduce energy consumption by adjusting the systemsupply voltage over a large range, depending on the

performance requirement. U-DVS is suitable forsystems with time-varying throughput constraint.

This paper is organized as follows; the scope ofthe low leakage SRAM for ultra low powerapplication is presented in section II. Variouschallenging issues of the current and the futureSRAM cell is reviewed in section III. Section IVpresent various device level optimizationmethodologies for low leakage SRAM. Section Vshows the various circuit topologies for low leakageSRAM cell for ultra low power applications. Finallyconclusion is drawn in section VI.

II. SCOPE OF LOW LEAKAGE SRAM FOR ULTRALOW POWER APPLICATIONS

Besides the quadratic dynamic power savings,very low supply voltages promise greatly reducedleakage power. For example, a 1-V reduction in thesupply voltage can reduce Ioff the transistor leakagecurrent, by over one decade due to the drain-inducedbarrier-lowering (DIBL) effect. The gate oxide


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leakage can also be reduced more than 100x with thesame 1-V drop in supply voltage.

Various low leakage applications for ultra-low power

operations are,

A. Energy-constrained applications such as wireless

sensor nodes, RFID tags, medical equipments such ashearing aids and pace-maker, wearable computing or

implants, Personal digital assistants, energy

scavenging applications, and Laptops, which are

dominated primarily by the need to minimize energy

consumption and increase battery life time, speed is a

secondary consideration for this class of applications,

so sub-threshold circuits offer a good solution [13].

B. Battery-powered handheld systems have been

faster than other integrated circuit applications such

as cell phones, MP3 players, and portable games. All

benefits from increased battery life, with lowering

integrated circuit (IC) power dissipation are provided.

In modern system-on-chip (SoC) devices, some

components, such as digital signal processors and

microprocessors, must operate at high frequencies, at

least intermittently. Many components do not need to

run as fast, but must be integrated on the same high-

performance silicon die. Additionally, some

applications require a small subset of the circuits to

operate continuously, e.g., real-time clocks and

wakeup circuitry.

III. CHALLENGING ISSUES FROM THE CURRENT

AND THE FUTURE LOW LEAKGE SRAM CELL

We have identified various device and circuitdesign challenges which need to be addressed foradvancing the in sub-threshold circuit design,emphasizing the need for co-design at all levels ofabstraction like device, circuit and architecture, andso forth. This section provides an interesting insightand challenges for designers interested to work withenergy-constrained applications.

A. Sensitive to Process and Temperature Variation:

Integrated circuits with ultra low-voltage powersupplies are highly sensitive to process andtemperature variations. The absolute value of theMOSFET threshold voltage degrades and the thermalvoltage is enhanced as the temperature increases. Asmall increase in the die temperature exponentiallyenhances the sub-threshold leakage current. Contraryto the standard higher-voltage circuits designed forhigh-speed, low-voltage circuits optimized forminimum energy operate faster when the dietemperature increases [13].

The on-chip temperature gradients induced byimbalanced switching activity are therefore typicallysmall across the die of a low-voltage integratedcircuit. Die temperature fluctuations due to thevariations in the ambient temperature however cancause significant fluctuations in the speed and thepower characteristics of ultra low-voltage circuits.

B. Power Overhead associated with Change in

Supply Voltage:

Power overhead associated with changing thesupply voltage level should at least be compensatedby the energy savings in the low-voltage mode. So,understanding the energy required to change thesupply voltage level is necessary as energy overheadis a fundamental issue and cannot be avoided.

C. Effect of Transistor Mismatch:

The main challenge for low-voltage operation isthat relative sizing of transistors is a weak knob due

to the exponential dependence of drive current onthreshold voltage in sub-threshold region. The basicand most important building block of a traditionalSRAM, 6T bit-cell is a ratioed structure and itscorrect operation depends on relative strength of itstransistors. Fig.1 shows the effect of access transistordrive strength on Write Margin (WM) distribution fora 6T SRAM cell at different supply voltages.

Fig.1Effect on Write Margin

However, at low voltages, the effect of sizing isnegated by transistor mismatches. Hence, a solutionrelying on only transistor sizing can be suitable forhigh-voltage operation but is insufficient for low-voltage functionality.

D. Degradation of Ion/Ioff


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The degradation in Ion/Ioff from 107

approximately to 104

implies that, in sub-Vt , there isa strong interaction between the on and the offdevices when it comes to setting the voltage level ofcritical signals. This introduces a relevant failuremechanism where SRAM density requirements callfor the integration of many devices on shared nodes

[13].

E. SER (Soft Error Rate)

An issue for deeply voltage scaled SRAM is softerror rate (SER). Soft errors occur when an alphaparticle or cosmic ray strikes a memory node andcauses data loss. Since, bitcell storage capacitancedecreases with scaling and voltage scaling furtherreduces the stored charge, SER is a concern for sub-threshold memory [33].

F. Cell Stability

Static Noise Margin (SNM) is the maximum

amount of noise that is tolerated at the data storagenodes of an SRAM cell. The voltage transfercharacteristics (VTC) of two cross-coupled invertersare shown in Fig.2. The resulting curve is called thebutterfly curve. The SNM is the length of thelargest square that can be embedded inside the lobesof a butterfly curve, as illustrated in Fig.2.

Fig.2 Butterfly Curve [20]

As described in [15, 16, 19, 20], for the memorycircuits operating in the super threshold (strong

inversion) region, the read static noise marginincreases with an increase in the memory cell ratio.The memory cell ratio is the ratio of the pull-downNMOS transistor width to the access transistor width(WN1/WA1 or WN2/WA2 where W is the width ofthe corresponding device in the 6T-SRAM bit-cell).As the supply voltage is scaled to the sub-thresholdregion, the dependence of the data stability on theSRAM cell ratio becomes negligible.

The reason for the diminishing sensitivity of theread static noise margin to the transistor sizes atscaled supply voltages is identified. The switchingcurrent at ultra-low voltage is the sub-thresholdleakage current. The sub-threshold leakage currentproduced by a MOSFET is [7].

Where, Ileak, , Weff, COX, Leff, Vt, VT, VGS, VDS, and

n are the sub-threshold leakage current, carrier

mobility, effective transistor width, oxide capacitance

per unit area, effective channel length, threshold

voltage, thermal voltage, gate-to-source voltage,

drain-to-source voltage, and sub-threshold swing

coefficient, respectively. For devices operating in the

weak inversion region, the switching current is

exponentially dependent on the voltage levels [15,

16]. Alternatively, increasing the device width

produces only a linear increase in the switching

current. A linear change in the sub-threshold

switching current has a relatively small impact on the

voltage transfer characteristics. The sensitivity of the

read noise margin to the memory cell ratio is

therefore negligible in an ultra-low supply voltage,

i.e., sub-threshold memory circuit.

7. Device Scaling:

Device scaling offers a reduction in gatecapacitance and at super sub-threshold voltages, itoffers a reduction in switching energy and gate delay.

Scaling leads to increase in density but at the sametime device scaling brought many problems likeincreased sub-threshold and gate leakage. Due toexponential sensitivities to Vth and Vdd in subthreshold regime, circuit may work properly underdevice scaling.

IV. VARIOUS CIRCUIT OPTIMIZATION

METHODLOGIES FOR LOW LEAKAGE SRAM CELL

There are various methods by which we canreduce the leakage current in order to optimize thepower reduction. One of them is the biasing schemes

which help in reducing the leakage currents inSRAM.

1. Various Biasing Schemes

(a). Source Biasing Scheme

This leakage reduction technique increases theline voltage in sleep mode operation to generate a


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negative Vgs in the access transistor and reduce thebit line leakage, as shown in Fig.3. The reducedsignal rail, bit line leakage and the body effect in thetransistor lowers the sub-threshold leakage in theSRAM cell. Gate leakage is also reduced as thesource voltage is reduced. But it imposes delaypenalty as an extra NMOS is required and also causes

the SER (soft error rate) to rise which directly has animpact on stability [1-4].

Fig.3 Source Biasing Scheme [10]

(b). Reverse Body Biasing Scheme

In this technique NMOS or PMOS reduces thesub-threshold leakage in sleep mode via body effectFig.4. Due to zero body bias in active mode theaccess time remains the same. This scheme is lesseffective in deep sub-micrometer and it also increasesthe junction band to band tunneling leakage current[3, 5, 6].

Fig.4 Reverse Body Biasing Scheme [10]

(c). Dynamic Voltage Supply

In this scheme, the supply voltage is lowered toreduce the leakage; however, the bit line leakagecannot be reduced in this, as the bias condition in theaccess transistor does not change Fig.5. This has alarger transistor overhead and has substantialincrement in SER [3, 7].

Fig.5 Dynamic Voltage Supply [1]

(d). Floating Bit Line.

This technique has the bit lines, floating during

the standby mode and reduces the bit line leakage viaDIBL. This scheme (Fig.6) cannot be applied toindividual cache lines, since the bit line is sharedacross different cache lines. Normally, bit lines haveto be precharged and ready for the word line access.Since the bit lines are floating for this technique, anextra precharge cycle is required whenever a newsub-array is accessed. No delay rise and no impact onSER is observed [8].

Fig.6 Floating Bit Lines [1]

(e). Negative world line scheme

In this technique it has been propped to cut off thesub-threshold leakage through access transistors byusing a lower voltage in cells and bit lines (Fig.7).Although this technique has no impact on theperformance or on SER but there is dynamic poweroverhead for creating the negative voltage [9].


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Fig.7 Negative Word-line Scheme Lines [2]

(f). Forward Body Biasing

In this technique, the NMOS or PMOS transistors in

the selected sub array are dynamically switched from

zero body bias to forward body bias. Forward body-biasing (FBB) has proven to effectively improve

performance, suppress short channel effects, and

reduce variations, roll-off. The drain-induced barrier

lowering (DIBL) which limits scalability of channel

length can also be relieved by FBB during the normal

operation of the device. As alone this technique does

not reduce the gate current but along with super high

Vt it is able to do so [10].

(i). Forward Body Biasing with Super High Vt

Here, the device optimization is achieved usingsuper halo 2-D doping profile. This profile uses a non

uniform P+ doping profile in the source body anddrain body boundaries to reduce the source draindepletion width and effectively suppresses the bodypunch through. The Vth roll and DIBL are alsocontrolled by 2D halo doping profile. The high Vtdoping profile is generated by raising the halo dopingconcentration of the nominal Vt device.FBB isdynamically applied to only the active portion of thecache for fast read and write operation. The two-dimensional (2-D) halo doping profile of a super highdevice to achieve total leakage reduction, whilesuppressing the gate leakage and junction band-to-band tunneling (JBTBT) leakage. In this schemeusing a super high device and FBB is used to

dynamically reduce the active leakage in cachememories.

The only limitation is that the technology wherehigher halo doping is unacceptable, a super high Vtdevice can be built using a gate material with ahigher flatband voltage. The simulation results showsthat a 32X 32 sub-array of SRAM is designed andsimulated at 70nm technology in which total 64%

reduction is shown as compared to source biasing and16% as compared to conventional SRAM [10,21,28].

Fig.8.Forward Body Biasing [10]

(g). Active/Passive Clamped Transistor Scheme

(i). Passive clamped transistor scheme:

A passive clamped bias design uses digitallyprogrammable transistors which are used to set thevirtual ground voltage during standby. Thisprogramming has to set for worst case, ie, maximumSRAM leakage under process variation conditions.As aging can change the device on and offcharacteristics so this makes a passive clamptransistor scheme less effective in reducing cacheleakage power [11].

(ii). Active Clamped Transistor Scheme

There are various actively clamped bias schemes

which minimize the standby power of the memory.One of them is using replica cell bias generator toderive the gate voltage of the bias device. Thisscheme tracks the process variations in Vss value.The other proposed scheme is a linear voltageregulator which is used to derive the Vss to a givenprogrammable Vmin value. This results in excellentPVT and aging tracking but if see the other side itresults in larger penalties of area and dynamic poweroverhead to switch between active and standbyvoltage levels [32].

A new scheme is proposed in which a combineddistributed sleep and active clamp scheme is usedwhich incurred less than 3 % are overhead and activeclamping has 14% less leakage than for passive biasand sleep transistors. It helps in reducing the leakagepower of idle sub-arrays by 30-60% at 0.8-1.0 Vstandby. A 256kb dual Vcc SRAM has beensimulated which operated between 2.3-4.2GHz with16-29mw total power consumption at 85

oC. It has

fixed 1.2 fixed Vlccand 0.7-1.2 Vcore [15].


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Another approach is using the combination ofFBB with Vt using 2D super halo technique andActive clamped transistor. This approach is used sothat FBB technique is used for fast operation andclamped transistors with high Vt is used to reduce theleakage [10].

(2). High-K Metal Gate Technology

In this proposed technology the high-k" (Hi-k)material is used to replace the transistor's silicondioxide gate dielectric, and new metals to replace thepolysilicon gate electrode of NMOS and PMOStransistors. These new materials, along with the rightprocess recipe, reduce gate leakage more than 100-fold, while delivering record transistor performance.Along with this PMOS FBB technique is used forlower voltages. The stronger PMOS under the FBBcan improve the minimum operating voltage up to 75mV. This improvement is achieved without

increasing the overall SRAM leakage power, sincethe Nwell is restored back to Vcc after the WL(wordline) is turned off. The active powerconsumption per access due to dynamicallydischarging and charging the Nwell is less than 1% ofthe total access power, where significant portion ofthe active power during cache access is from signaland clock distributions. The leakage current isreduced by 10x. The operating frequency of 153 MbSRAM using this technology at 45nm is 2.7 GHz at0.9V and 3.8 GHz at 1.1V.The limitation is that itdegraded the write margin [17].

(3). Dual Rail Mechanism

Several design solutions for Vdd minimum issueswere proposed for the single rail at 65 nm and 45 nmSRAM. The suppressed word-line (WL) scheme wasreported to address the bit cell SNM issue caused bythe ever increasing device variations in the shrinkingdevices. This scheme can improve the SNM, but itcauses an unacceptable cell current degradation in thelower Vdd regime. The cell current degradation, inturn, becomes the limiter of Vddmin. The area isincreased to maintain an acceptable cell current. Toavoid this area penalty, dual-rail SRAM designs in 65nm were proposed. The dual-rail design with adedicated SRAM power source, Cell-Vdd (CVdd),

can achieve a lower Vddmin, but the challenge lies inthe large current consumption of the CVdd powersource. The large CVdd current implies large areaswhich are needed to implement numerous CVddvoltage regulators, and wider power lines to mitigatethe CVdd IR-drop issue. IR drop constraints as wellas the area penalty results from the power routing.However, fixing the CVdd voltage level would limitthe Vddmin reduction because scaling down the Vdd

would cause a large voltage difference between theCVdd and the Vdd [18].

In order to further improve the Vddmin, anadaptive CVdd voltage regulator, which generates adesired offset with respect to Vdd, is proposed. Inthis mechanism a dual rail Vdd is used to generate

logic Vdd and cell Vdd, so that logic Vdd is reducedto 0.6V. The Vddmin is lowered and also the arearequired has been reduced. This technique is alsoextendable to new process technologies upto 32nm.But it degraded the SNM as when the Vdd is scaleddown ,the offset voltage is increased due to which theSNM degrades [18].

Fig.9 Maximum Offset Voltage Limitation versus Different

Process Generations [18]

Fig.9 shows the maximum offset voltagelimitation versus different process generations. Itshows that the maximum offset voltage is gettinglower as the device shrinks from 65 nm to 32 nmtechnology nodes. That is because the SNM is alsogetting lower as the device scales down. This trendwill also make the proposed Vdd-tracking CVddconcept more attractive in the future technologynodes. 1 Mb SRAM is tested and the area has beenreduced to 5%. Vdd is 0.74V-0.9V and Vddmin of0.6 V is achieved.

(4). Low Vdd Operation and Increase in the Vth

Scheme

For high speed applications and low Vddoperation, a new scheme is used in which the Vth ofthe has been increased. The supply voltage, ie, Vdd

has been reduced to 0.5V and the access time is alsoreduced to 20ns when a 64 kb SRAM is simulated at90nnm technology. But at lower voltages of Vddwrite operation cannot be performed and also leakagecurrent of PMOS transistors results in storagedestructions [20].

(5). Dual Boosting Scheme


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In this scheme internally boosting of the voltagelevel of the word line and cell power node is donewhich increases the driving capability of the NMOSaccess transistor during read operation and reducesthe bit line delay because of Icell increases duringthis operation. It increases the Read SNM and writeSNM at low voltages. The operating frequency is 50

MHz but it has been observed that it results inoverhead of area and power. It has been observed thatduring the simulation of 256kb SRAM the areaoverhead is 4.5% due to cell boosting and reductionin chip cycle by 26% at the expense of 14.6%additional power. The cell ratio is also of primeconcern which is kept one. [23, 26].

(6). Novel Write Mechanism

In this scheme a write mechanism is proposedwhich depends only on one of the 2 bit lines toperform the write operation. Transistor sizing is alsoof prime concerned in this mechanism for cell

stability. It also uses the sleep transistors but theoverall leakage power is slightly higher thanconventional SRAM and the cache are is alsoincreased by 12.25 % from the conventional SRAM.A trade off is maintained between the SNM and theleakage power. As high Vt PMOS are used whichhelps in reducing the leakage but reduces the SNM[21, 28, 32].

(7). Sense Amplifier Redundancy Mechanism

Here, a charge pump is used to resolve the zeroleakage read buffer footer. A high density 8T SRAMis simulated with minimum operating voltage of350mV. But speed is of concern in this technique

which decreases. Also the cell stability is decreased[29].

(8). Dual Vth & Dual Tox Scheme

In this scheme different combinations oftransistors with dual Vth and dual Tox have beenused to design the various 6T SRAM cells. It reducesboth sub-threshold and gate tunneling leakagecurrent. This technique is useful in increasing theSNM also. Various combinations have been observedto have the best results [35].

(9). Self Write Back Sense Amplifier Scheme

Self write back sense amplifier is used withcapacitance separator. In it a cascaded bit line schemeis used as the access time of the proposed scheme isproportional to the number of sense amplifiers. It ispreferred for low SRAM macros. The proposedscheme is advantageous for smaller macro, for bitcapacity is less than 256 kb the timing margin forsense amplifier enable signal is unnecessary for

shorter BL arrays. The cascaded bit line schememinimizes the area penalty. It also realizes read andwrite operation without global lines. It is useful forlow voltage operation [23].

(10). Uni-axial Si Strained Technology

In this technique, the uni-axial Si strainedtechnology, the nitride films are deposited on Si toact as the contact etch stop layer (CESL). In this 65nm process, strong uniaxial tensile strain is createdby the nitride layer in order to increase NMOSmobility. The amount of strain increases with thethickness of the nitride layer that can fill between thegates and the amount of contact of the nitride filmwith the source/drain region. The 65 nm strainedsilicon technology improves transistorperformance/leakage tradeoff, which is essential toachieve fast SRAM access speed at substantially lowoperating voltage and standby leakage. The 1 MbSRAM macro features a 0.667 m

2low-leakage

memory cell and can operate over a wide range ofsupply voltages from 1.2 V to 0.5 V. It achievesoperating frequency of 1.1 GHz and 250 MHz at 1.2V and 0.7 V, respectively. This technology has beensuccessful for future process technologies also [14].

The above techniques are used to reduce theleakage and increase the stability of the cell. Butthere are other technique which depends on thenumber of transistors in a SRAM cell to increase thestability and reduce the leakage.

(11). Gate Feedback Memory Cell

In this scheme a gate feedback memory cell is

used for SRAM in which the decoder circuits isseparated from read circuits. The power consumptionwas low, 0.83w dynamic power consumption and0.197 w static power consumption while simulatinga 512x13 bit SRAM memory cell at 130nm. Thelimitation was that it has almost vanishing readstability at low voltages and also speed was thelimitation [13].

(12). Stacking Effect

In this scheme half stacking and full stackingeffects is used to design a conventional 6T SRAMcell for low leakage reduction. There is drasticchange in power consumption in full stack effect but

the main limitations are area overhead and SNMdegraded. At 130 nm the results are fine but as thegate length is reduced power consumption alsoincreases. It has been shown that the stacking of twooff transistors can significantly reduce leakage powerthan a single off transistor [37]. Increasing the sourcevoltage of NMOS transistor reduces sub-thresholdleakage current, exponentially due to negative Vgs,


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lowered signal rail, reduced DIBL and body effect.This effect is also called self-reverse biasing oftransistor the self-reverse bias effect can be achievedby turning off a stack of transistors. Turning off morethan one transistor in a stack raises the internalvoltage (source voltage) of the stack, which acts asreverse biasing the source. The voltages at the

internal nodes depend on the input applied to thestack [16].

Fig.10.6T SRAM using Stacking Effect [16]

V. VARIOUS SRAM CELL TOPOLOGIES FOR LOW

LEAKAGE SRAM CELL

Although the 6T SRAM cell with abovementioned technologies have been implemented for abetter performance but it has some of the limitations.

The conventional SRAM fails at many aspects so,various other topologies of SRAM are beingdiscussed here for low leakage SRAM.

(1) 7T SRAM Cell

Here a 7T SRAM cell (90nm technology) a dataprotection NMOS transistor N5 has been addedbetween Node V2 and NMOS transistor N2. Whilethe SRAM cell is being accessed, /WL is in theactivated state, 0, and N5 is OFF. Since N5prevents the voltage at Node V2 from decreasing, thedata bit is not reversed even if Node V1 voltagegreatly exceeds Fig.11.

During data retention period, when the SRAM cell isnot being accessed, word line signal /WL is 1, and

NMOS transistor N5 is ON. The use of two CMOS

inverters results in high cell stability. During Read

operations, the logical threshold voltage of the

CMOS inverter driving Node V2 increases greatly

when the data protection NMOS transistor N5 is

turned off. For this reason, the Read SNM value at

V2 remains large even when access MOS transistor

N3 is turned on and Node V1 voltage increases.

Fig.11 7T SRAM Cell [20]

The worst normalized Read SNM and normalizedIcell values improve, respectively, to 1.24 and 0.54.A minimum supply voltage (Vdd-min) of 440 mVand a 20 ns access time are achieved with a 0.5 Vsupply voltage. In this SRAM, Vdd-min is limited bythe following two factors: 1) Write operations at low-Vdd levels cannot be performed, since write margindecreases with decreasing Vdd. 2) Read operations atlow-Vdd levels result in storage data destruction inSRAM cells due to the leakage current of PMOStransistor P2.[20]

Fig.12 Vdd-min Temperature Dependence [20]

Fig. 12 shows Vdd-min dependence ontemperature. Below 85oC, Vdd-min decreases withincreasing temperature. This occurs because Vdd-minis determined by factor: (a). Write margin, unlikeRead SNM, improves with decreasing Vth levels inNMOS transistors, and Vth decreases with increasingtemperature. VDD-min, which will not improve evenif the temperature exceeds 85

oC, will be determined

by factor (b).The leakage current of PMOS transistor


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P2 increases with increasing temperature. Thisreverses the relationship between BL delay time andretention time. Since, both Write margin and SRAMcell current improve with decreasing Vth levels inNMOS transistors; it will be possible to achieve evenhigher speeds and lower-VDD operations byreducing Vth levels below 0.32 V, the value currently

achieved.

(2). 7T dual Vt SRAM Cell

The circuit schematic of the 7T dual-Vt SRAMcell with transistors sized for a 65nm CMOStechnology is shown in Fig.13. The cross-coupledinverters formed by the transistors N1, P1, N2, andP2 store a single bit of information. The write bitlineWBL and the pass transistor N3 are used fortransferring new data into the cell [36].

Alternatively, the read bitline RBL and thetransistor stack formed by N4 and N5 are used forreading data from the cell. Two separate control

signals R and W are used for controlling the read andthe write operations, respectively, with the 7T SRAMcircuit as shown in Fig. 13.

Fig.13 7T Dual Vt SRAM [36]

(3). 8T SRAM Cell

The schematic of the 8T SRAM cell sized for a65nm CMOS technology is shown in Fig. 14. The leftsub-circuit of the 8T memory cell is a conventional6T SRAM cell with minimum sized devices(composed of N1, N2, N3, N4, P1, and P2). Two dataaccess transistors (N3 and N4) and two bitlines(WBL and WBLB) are used for writing to the SRAMcell. An alternative communication channel

(composed of a separate read bitline RBL and thetransistor stack formed by N5 and N6) is used forreading the data from the cell. Two separate controlsignals R and W are used for controlling the read andthe write operations, respectively, with the 8T SRAMcircuit as shown in Fig. 14. During a read operation,the read signal R transitions to Vdd while the writesignal W is maintained at Vgnd [36].


The read bitline (RBL) is conditionallydischarged based on the data stored in the SRAMcell. The storage nodes (Node1 and Node2) arecompletely isolated from the bitlines during a readoperation. Data stability is thereby significantlyenhanced as compared to the standard 6T SRAMcells [29].

(4). 9T SRAM Cell

The schematic of the 9T SRAM cell, withtransistors sized for a 65-nm CMOS technology, isshown in Fig. 15. The upper sub-circuit of the 9Tmemory circuit is essentially a conventional 6TSRAM cell with minimum sized devices (composedof N1, N2, N3, N4, P1, and P2).

Fig.15 9T SRAM cell [36]

The two write access transistors (N3 and N4) arecontrolled by a write signal (WR). The data is storedwithin this upper memory sub-circuit. The lower sub-circuit of the new cell is composed of the bit-lineaccess transistors (N5 and N6) and the read accesstransistor (N7). The operations of N5 and N6 arecontrolled by the data stored in the cell. N7 is

controlled by a separate read signal (RD). During awrite operation, WR signal transitions high while RDis maintained low. N7 is cutoff. The two write accesstransistors N3 and N4 are turned on. In order to writea 0 to Node1, BL and BLB are discharged andcharged, respectively. A 0 is forced into the SRAMcell through N3. Alternatively, for writing a 0 to


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Node2, BL and BLB are charged and discharged,respectively. A 0 is forced onto Node2 through N4.

During a read operation, RD signal transitions high

while WR is maintained low. The read access

transistor N7 is activated. Provided that Node1 stores

1, BL is discharged through N5 and N7.

Alternatively, provided that Node2 stores 1, thecomplementary bitline (BLB) is discharged through

N6 and N7. Since N3 and N4 are cutoff, the storage

nodes Node1 and Node2 are completely isolated from

the bitlines during a read operation [36].

Leakage Power Comparison of the three Topologies

(7T, 8T, and 9T)

The leakage power consumption of the SRAMcircuits is shown in Fig. 16. The leakage power of anSRAM cell is determined by the total effectivetransistor width and the threshold voltages of thetransistors that produce the leakage current.

Transistor sizing for enhanced data stability comes ata cost of significant additional leakage power withthe standard full-voltage-swing 6T SRAM circuits.The leakage power is doubled when is increasedfrom 1 to 3 with the standard 6T SRAM circuit, asillustrated in Fig. 16.

The dual-Vt 7T SRAM cell consumes the lowestleakage power by utilizing minimum sized high-Vttransistors in the cross-coupled inverters. The leakagepower of the dynamic wordline voltage swingtechnique, the 9T SRAM cell, the 8T SRAM cell, andthe dual-Vt 7T SRAM cell is reduced by 51%, 23%,21%, and 57%, respectively, as compared to a

standard 6T SRAM cell sized for read stability(=3)[34].

Fig.16 Leakage Power Consumption [34]

(5). 10T SRAM cell

Fig. 17 shows the schematic of the 10T sub-threshold bitcell. Transistors are identical to a 6Tbitcell except that the source of M3 and M6 tie to a

virtual supply voltage rail Vdd. Write access to thebitcell occurs through the write access transistors, M2and M5, Transistors from the write bitlines, BL andBLB. Transistors M7 through M10 implement abuffer used for reading. Read access is single-endedand occurs on a separate bitline, RBL, which isprecharged to prior to read access. The wordline for

read also is distinct from the write wordline. One keyadvantage to separating the read and write wordlinesand bitlines is that a memory using this bitcell canhave distinct read and write ports.


At 27oC, the 10T memory saves 2.5X and 3.8X

in leakage power by scaling from 0.6 V to 0.4 V and0.3 V, respectively and over 60X when scales from1.2 V to 0.3 V, scaling also gives the expectedsavings in active energy per read access.

(6). 11T SRAM Cell

The schematic diagram of the proposed 11T-SRAM bitcell. Transistors M2, M4, M5, and M6 areidentical to 6T-SRAM, but two transistors M1 andM3 are downsized to the same size as the PMOStransistors.

The bitline and word line are distinct from thewrite word line. In this case, memory can havedistinct read and write ports. During the hold time,RDWL and WL are not selected. In the 6T-SRAMpart, suppose that node Y stores 0 and node Xstores 1 as was described for the 6T-SRAM part inthe previous section. For the added circuitry thefollowing behavior is observed when transistor M12is turned off. Also, the M11 state is dependant of the

voltage in node Y. If node Y stores 1, then M8connects the gate of M11 to ground, so M11 is turnedoff. However, if node Y stores 0, M9 is turned offand it starts to charge the gate of transistor M11.

Therefore there is a leakage path through M11that connects the node YN to zero. Minimum sizetransistors were used for the added 5T-circuitry,except the access transistor that has a larger size. The


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most important part of the 11T-SRAM is a boostcapacitor (CB) that connects source of M9 to RDWL.


VI. CONCLUSION

As low leakage SRAM will continue be indemand due to rise in battery operated portableapplications and also due to continuous scaling ofCMOS. So, new approach should be involved toreduce the leakage application. Device optimizationis a must for low leakage SRAM to further reducepower and enhance performance. Also area and cellstability should be taken care while optimizing thepower reduction. Various optimization techniqueshas been proposed which can be effective in recenttechnologies .These techniques can be implementedin various SRAM transistor cells which overallincrease the performance. As higher order transistorsare able to solve the problems of conventional 6T so

we can go forward and also the area overhead will beat the same time is minimized as the scaling ofCMOS is continued. The leakage reduction can bedone by the various optimization techniquessuggested in the papers and for stability enhancementwe can choose the SRAM cell topology. The Dualrail mechanism techniques discussed in this paperwill also work for lower technology till 32nm.Therecent technologies like High K metal gatetechnology is efficient for the lower CMOStechnologies till 22nm.So we can implement thethese techniques in context of present and futuretechnologies and can enhance the stability and reducethe leakage current.

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BIOGRAPHIES

Shilpi Birla, a Ph.D. Scholar at the UK Technical University,Dehradun (Uttarakhand) India. She is an Asst. Professor in the

Department of Electronics & Communication Engineering, Sir

Padampat Singhania University, Udaipur (Rajasthan) India. Shehas received her M.Tech. (VLSI Design) and B.E. (Electronics &

Communication Engineering) Degrees from the University of

Rajasthan, Jaipur (Rajasthan) India and MITS University,

Laxmangarh, (Rajasthan) India, respectively. Her main research

interests are in Low-Power VLSI Design and its Multimedia

Applications, RF-SiP, and Low-Power CMOS Circuit Design.

Neeraj Kr. Shukla (IEEE, IACSIT,IAENG, IETE, IE, CSI,ISTE), a Ph.D. Scholar at the UK Technical University, Dehradun

(Uttarakhand) India.He is an Asst. Professor in the Department of

Electrical, Electronics & Communication Engineering, ITMUniversity, Gurgaon, (Haryana) India. He has received his

M.Tech. (Electronics Engineering) and B.Tech. (Electronics &

Telecommunication Engineering) Degrees from the J.K. Instituteof Applied Physics & Technology, University of Allahabad,

Allahabad (Uttar Pradesh) India in the year of 1998 and 2000,respectively. His main research interests are in Low-Power Digital

VLSI Design and its Multimedia Applications, Open Source EDA,

and RTL Design.

R.K. Singh (IAENG, ACEEE, IE, ISTE), Professor in theDepartment of Electronics & Communication Engineering, VCT-

Kumaon Engineering College, Dwarahat, Almora (UK) India. He

is being honored with the Ph.D. in Electronics Engineering in theYear 2003 from the University of Allahabad, Allahabad (Uttar

Pradesh), India. He has received his M.E. (Electronics & Control

Engineering) in 1992 from BITS, Pilani and B.E. (Electronics &Communication Engineering) in 1990 from Marathawada

University, India. He has authored several text-books in the field of

VLSI Design, Basic Electronics, and Opto-Electronics. He has

worked at various capacities as, the Principle, Kumaon

Engineering College, Dwarahat in the year 2003-04, Director (O),

Directorate of Technical Education, Uttaranchal in the year 2005,and Joint Director, State Project Facilitation Unit, Dehradun for the

World Bank TEQIP Project. He is also the recipient of couple of

prestigious awards, e.g., Rastriya Samman Puruskar, Jewel of IndiaAward, Rastriya Ekta Award, Life Time Achievement Award, and

Arch of Excellence Award. His current areas of interest are VLSI

Design, Opto-Electronics and its applications.

Manisha Pattanaik (WSEAS, IE, ISTE) has been honored the

Ph.D. from Indian Institute of Technology (IIT) Kharagpur, (West

Bengal) India in the field of VLSI Design from the Department of

Electronics and Electrical Communication Engineering in the year

2004. Currently she is an Assistant Professor (VLSI Group) atABV-India Institute of Information Technology & Management

(ABV-IIITM), Gwalior, (Madhya Pradesh), India. She has been

awarded various scholarships, e.g., National Scholarships, Merit

Scholarships and MHRD Fellowships. She shared theresponsibility in the capacity of referee for IEEE International

Conferences on VLSI Design for two consecutive years, 2003-04.

Her areas of interest are Leakage Power Reduction of Nano-Scale

CMOS Circuits, Characterization of Logic Circuit Techniques for

Low-Power/Low-Voltage and High performance analog & digitalVLSI applications and CAD of VLSI Design.

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Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications

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