DEVKIT-MPC5748G - Schematics · Catalin Neacsu Rev Date Comments Power - MCU Power Reset and JTAG...

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Comms 1 - CAN and LIN

Revision Information

X1DesignerCatalin Neacsu

CommentsRev Date

Power - MCU Power

Reset and JTAG

Sheet 8Sheet 9Sheet 10Sheet 11Sheet 12Sheet 13Sheet 14Sheet 15

These schematics are provided for reference purposes only. As such,NXP does not make any warranty, implied or otherwise, as to thesuitability of circuit design or component selection (type or value) used inthese schematics for hardware design using the NXP Calypso family ofMicroprocessors. Customers using any part of these schematics as abasis for hardware design, do so at their own risk and Freescale does notassume any liability for such a hardware design.

Sheet 2Sheet 3Sheet 4Sheet 5Sheet 6Sheet 7MCU GPIO 1

Comms 4 - Ethernet (RMII Mode)Comms 3 - USB Host Interface (device footprints only)Comms 2 - OpenSDA

User notes are given throughtout the schematics.

Specific PCB LAYOUT notes are detailed in ITALICS

Caution:

MCU GPIO 2

Comms 5 - FlexRayUser - Switches, LED's ,Potentiometer and SD CARDUser - GPIO Connectors

Table Of Contents:

Notes:

DEVKIT-MPC5748G

- All components and board processes are to be ROHS compliant- All small capacitors are 0402 unless otherwise st ated- All resistors are 0603 5% 0.1w unless otherwise s tated. All zero ohm links are 0603- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated- All jumpers are denoted Jx. Jumpers are 2mm pitch- Jumper default positions are shown in the schemat ics. For 3 way jumpers, default is always posn 1-2. 2 Pin jumpers generally have the "source" on pin 1.- All switches are denoted SWx- All test points (SMT wire loop style) are denoted TPx- Test point Vias (just through hole pads) are deno ted TPVx

Power - Main input, 5V and 3.3V regulator

Clocks

Initial release23 Sep 2015

Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes. 3 Different test points used in design:

TPVx - Through Hole Pad small

TPHx - Through Hile Pad Large (for standard 0.1" he ader).Also used on IO Matrix (IOMx)

TPX - Surface Mount Wire Loop

Power - MCU Decoupling

X2 Catalin Neacsu Further changes. Decreased component size where possible.24 Sep 2015

Catalin NeacsuX3 29 Sep 2015Changed ethernet page. Changed caps around Q50Rearranged GPIOs on page 15. Added more LEDs on page 14

X4 Catalin Neacsu02 Oct 2015 Changed U50, USB connectors, ETH Connector, BOM optimizationX5 05 Oct 2015 Catalin Neacsu Changed PN of U11 and C23X6 07 Oct 2015 Catalin Neacsu Small visual updatesX7 08 Oct 2015 Catalin Neacsu Add separation resistors for USB interface, U50X8 12 Oct 2015 Catalin Neacsu Changed 3V3 converter, minor BOM optimizationX9 14 Oct 2015 Catalin Neacsu Changed 3V3 converter, minor BOM optimization, better cost

X10 21 Oct 2015 Catalin NeacsuUpdated IO connections per Jesus Sanchez's requestAdded TP on page 3 per Ruiz Ricardo's request

X11 27 Oct 2015 Catalin NeacsuChanged Power Supply pageAdded one user led

X12 28 Oct 2015 Catalin Neacsu Changed PN for P2 and P7X13 30 Oct 2015 Catalin Neacsu Changed Power Supply page to allow supply selectionX14 02 Nov 2015 Catalin Neacsu BOM OptimizationX15 03 Nov 2015 Catalin Neacsu PN change for L1X16 23 Dec 2015 Catalin Neacsu Added Open SDA block

Implemented other feedback

X17 06 Jan 2016 Catalin Neacsu Implemented OpenSDA feedbackX18 08 Jan 2016 Catalin Neacsu Changed some ICs to their NXP equivalentX19 15 Jan 2016 Catalin Neacsu P12, Y50 add GND connections. JTAG connector 14 pinsA 26 Jan 2016 Catalin Neacsu Protoype ReleaseA1 13 Jun 2016 Jun Qiao Update with Flexray, OpenSDA, Ethernet, LED, Buttons, GPIO. A2 20 Jun 2016 Jun Qiao Update with OpenSDA, GPIO connectors. B 24 Jun 2016 Jun Qiao Pilot Release

BX1 03 Nov 2017 Sendhil kumar Update Ethernt & USB connection...etc

C 29 Nov 2017 Sendhil kumar Pilot Release

D 03 Apr 2018 Sendhil kumar Ethernet Section - replaced from Rev B KSZ8081RNACA schematicsJ2,J3,J4, J9,J12,J13&J14 are changed.

D1 17 May 2018 Sendhil kumar C15 Capacitor properties updated

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Automotive Product Group6501 William Cannon Drive WestAustin, TX 78735-8598

This document contains information proprietary to NXP and shall not be used for engineering design,procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: IUO: PUBI:

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Thursday, May 17, 2018

Index and Title Page

C Neacsu

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X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GND Test Points, Top Side

Power Input and Voltage Regulators

Test and reference points

Power Control

Jumpers can be fitted tofacilitate power measurements

LAYOUT NOTE:ADD Graphical silk:

+ -

12V Power Supply Input

3.3V Switching RegulatorInput Voltage 5V, Output 3.3V at 1600mA

Layout note: follow IC datasheet recommandations fo rPCB layout and thermal dissipation

Input Voltage 12V, Output 5V at 1800mA

Layout note: follow IC datasheet recommandations fo rPCB layout and thermal dissipation

5V Switching Regulator Board supply selectionSelect between USB and external 12V

1-2 -> external 12V2-3 -> USB/UART connector

GND

PER_HVA3V3_SR5V0_SR

5V0_SR

3V3_SR

GND

GND

GND

GND

GND

3V3_SR

GND5V0_SR

GND

3V3_SR

GND

GND

GND

GND

5V0_SW

GND

GND

5V0_SR

5V0_SR5V0_SW

12V_IN

5V_TGT_OUT

GND

MCU_5V0 (3)

MCU_3V3 (3)

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Power Input, 5V, 3.3V Reg

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R135 0

L8

47uH

1 2

C8422uF10V

R124 0

R134 0DNP

AP1509-SG-13

U18

VIN1

OUT2

FB3

SD4

GN

D1

5

GN

D2

6

GN

D3

7

GN

D4

8

R1381.0K1%

C6622uF10V

R1271.0K1%

J11HDR_1X3

1 2 3

L74.7uH

1 2

R1223.09K1%

C7122uF

25V

D6SBR3U30P1

AC

D8

PMEG4030ER

A C

TP9SILK = GND

1

D5SBR3U30P1

AC C63

22uF10V

R125 0

R143560

AP1509-SG-13

U19

VIN1

OUT2

FB3

SD4

GN

D1

5

GN

D2

6

GN

D3

7

GN

D4

8

TP7SILK = 3V3_SR

1

DS12GREENSILK = 5V_OK

AC

R1401.69K

1%

P6CON PWR 3

1

23

SH

1S

H2

DS13GREENSILK = 3V3_OK

AC

R144270

D4

PMEG4030ER

A C

TP8SILK = 5V0_SR

1

TP6SILK = GND

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Individual MCUsupply control

Default Configuration:

- ALL MCU supply voltages are set to 3.3V(ADC0, ADC1, VDD_HV_A, VDD_HV_B, VDD_HV_C,VBallast)- VDD_HV_FLA = External 3.3V supplied (jumperfitted)

The analogue pins can only be driven to thesame voltage as the VDD_HV_x domain they aresituated in (ie max 3.3V) so makes sense forthe analogue supply and reference to be 3.3V

3v3

5v0

Calypso MCU Power ConnectionsPower Supply Contraints:

- If VDD_HV_A is driven from 3.3V, VDD_HV_FLA mustalso be supplied from 3.3V- If VDD_HV_A is driven from 5V, the VDD_HV_FLA pin must be disconnected from 3.3V

- Don't attempt to over drive an analogue pad to 5Vwhen the digital VDD_HV_x supply is set to 3.3V. Th iswill trigger the ESD protection on that pad. Forexample if VDD_HV_A is set to 3.3V and the analogu esupplies are set to 5V, you cannot drive 5V into apad in the VDD_HV_A domain

Notes on signal Grounds:

- The scheme shown has the analogue and digital grounds connected to the same plane - This results in better ADC performance than using an analogue grond plane with single entrypoint (or ferrite) to digital ground plane.

GNDGND GNDGNDGNDGND

GND

HV

B_C

AP

HV

FLA

_CA

P

LV_CAP

AD

C0_

CA

P

AD

C1_

CA

P

AD

C1R

EF

_CA

P

HV

A_C

AP

B_CAP

LVDEC_CAP

C_CAP

MCU_3V3(2)

MCU_5V0(2)

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Calypso MCU Power

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R16 0DNP

SILK = 5V

R64 0DNP

SILK = 5V

C604700pF

Q1MJD31CT4

34

1

R111 0

SILK = 3V3

R1130TPV16

SILK = ADC0

R117 0

SILK = 3V3

C542.2uF

TPV4

R116 0DNP

SILK = 5V

R15 0

SILK = 3V3

R91 0

TPH2

DNP

SILK = VSS_HV_VPP

1

R126 0

SILK = 3V3

1.25v Core & External BallastAnalogue Calypso 6M 176QFPPACKAGE 2OF3 POWER PINS

Flash

U16B

SPC5748GHK0AMKU6

VR

C_C

TR

L32

VS

S_L

V_1

0910

9

VD

D_L

V_3

131

VD

D_L

V_5

454

VD

D_L

V_1

1011

0

VD

D_L

V_1

5215

2

VD

D_H

V_A

_66

VD

D_H

V_A

_59

59

VD

D_H

V_A

_85

85

VD

D_H

V_A

_151

151

VD

D_H

V_B

_124

124

VS

S_H

V_A

DC

089

VD

D_H

V_A

DC

090

VD

D_H

V_A

DC

199

VS

S_H

V_A

DC

197

VD

D_H

V_F

LA27

VD

D_H

V_A

DC

1_R

EF

98

VS

S_H

V_7

7

VS

S_H

V_2

828

VS

S_H

V_5

555

VS

S_H

V_5

757

VS

S_H

V_8

686

VS

S_H

V_1

2312

3

VS

S_H

V_1

5015

0

VD

D_L

P_D

EC

30

VS

S_H

V/V

PP

26

EX

_PA

D17

7

TPV13

SILK = ADC1

TPV12

SILK = HVFLA

TPH3

DNPSILK = ADC1REF

1

R60 0

SILK = 3V3

TPV10

SILK = HVB

R98 0

SILK = 3V3

R105 0DNP

SILK = 5V

R112 0

TPV14SILK = C_CAPR121 0

DNP

SILK = 5V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place small Caps as close as possible to MCU pins

ADC

VDD_HVA VDD_HVB

VDD_LV

VDD_LV (1.25V) Decoupling. Place one of the 0.1uF caps close to each VDD_LVpin. Place the 0.68uF caps on each side of the package such that there isno cap on the side with the ballast transistor

Flash

Calypso MCU Decoupling and bulk storage

LP Internal Reg Cap

One 0.1uF cap per VDD_HV_x pin. Place as close as possible to pin

(For regulator stability the total capacitance should be around 2.2uF).

GND GND

GND

GND

GND

GND GND GND

ADC0_CAP ADC1REF_CAPADC1_CAP

HVA_CAP HVB_CAP

LV_CAP

HVFLA_CAP

LVDEC_CAP

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Calypso MCU Decoupling

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C482.2uF

C100.1UF

C610.1UF

C740.1UF

C620.68UF

C570.1UF

C150.1UF

C760.1UF

C440.68UF

C671.0UF

C750.1UF

C130.1UF

C551.0UF

C581.0UF

C651.0UF

C28

0.1UF

C780.68UF

C262.2uF

C450.1UF

C680.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TARGETRESETLED

Reset Switch

(1.65 to 5.5v operation) Tri-State BufferedRESET signal toreset the MCU

Reset and External Clock In

Buffered RESET-out

Note:

The Reset pad on Calypso is in the VDD_HV_A domain which can be run from either 3.3V or 5V(selected by the VDD_HV_A and PER_HVA jumpers)

To maintian brightness on the LED's irrespective of the voltage setting, the LED's arepowered from constant 3.3V, grounded via the reset line.

Bi Directional resetline to/from MCU

Active reset drive (high / low)for any periperhals that need tobe reset when MCU is in reset

Reset fromDebugger

Reset Input / OutputPORST

Connect an external LVI to padwhen supplying external 1.25V sothat PORST is asserted untilexterbal 1.25V supply is atthreshold and stable

Reset is in theVDD_HVA domain.

TDITDOTCLK

(bufferedreset TO MCU)

(bidirectionalMCU reset)

OptionalConfig

TMS

(RDY)

Place One CAPnext to eachconnector

ONCE Connector

(N/C)(TMS)

(GND)(GND)(GND)

(GND)

(TDI)(TDO)(TCLK)(EVTI)(RESET)(VREF)

JTAG Standard 14-pin Connector

Layout Note:Clearly mark pin numbers1, 2, 13 and 14

GND

GND

GND

3V3_SR

GND

GND

PER_HVA

3V3_SR

PER_HVA

GND

GND

PER_HVA

JTAG-RSTx(5)

MCU-RSTx (5,7,10,15)

RST-OUTx (12)

PORSTx (7)

MCU-RSTx(5,7,10,15)

TMS_HEADER(10)

TCLK_HEADER(10)

TDI_HEADER(10)PC1(7,10)

JTAG-RSTx(5)

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Reset Circuitry & External Clock In, JTAG

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VCC

GND

U11A

74LVC2G08

1

27

84

DS3

REDSILK = MCU_RST

A C

C10.1UF

TPH1

DNPSILK = PORSTx

1

U7

STM6315

VCC4

RST2

VSS1

MR3

TPV1

R3510K

C240.1UF

SW1SKRPABE010

SILK = RESET

1 4

2 3

U11B

74LVC2G08

5

63

R65 270

P4

HDR_2X7SILK = JTAG

1 23 45 67 89 10

11 1213 14

R5410K

R29 10K

R5310K

C210.1UF

R21 0

R50 0

DNP

R51 0

DS2LED_YELLOW

AC

R8710K

R4010K

R1910K

R44270

RST-SWITCHxSYSTEM-RSTx

RST-INx

DBUG-RSTx

JCOMP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Oscillators

CX3225GA40000D0PTVCC(Optimised for Automotive,8pF Load capacitance)

ABS07-32.768KHZ-T(Load Capacitance 12.5pF)

Clocks

GND

GND

MCU-XTAL(7)

XTAL32(7)

EXTAL32(7)

MCU-EXTAL(7)

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Clocks

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Clocks

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Clocks

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R1301MDNP

C79 12PF

Y432.768KHZ

12

C82 12PF

Y5

40MHZ

12

R1331MDNP

C80 12PF

C81

12PF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Calypso GPIO 1 of 2

(LIN0_RX)(LIN0_TX)

(FR_A_TX)

(USB1_CLK)(USB1_DIR)

(RMII_RXD0)(RMII_RXD1)

(RMII_RXER)

(MII_TXCLK)

(FR_DBG0)(FR_DBG1)(FR_DBG2)(FR_DBG3)

(TDI)(TDO)

(ADC_POT)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(CAN0_TX)(CAN0_RX)

(RS232_RX)(RS232_TX)

(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)_

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(USB1_D0)(USB1_D1)

(USB1_D2)(USB1_D3)

(USB1_D4)(USB1_D5)

(USB1_D6)(USB1_D7)

(MII_CRS)

(RMII_TXD0)(RMII_TXD1)

(RMII_TXEN)

(RMII_MDC)

(RMII_MDIO)

(TCK)(TMS)

(FR_A_TX_EN)(FR_A_RX)

Green - I/O Matrix (dedicated)

Key to text colours:Purple - Comms Physical Interfaces

Blue - Debug (JTAG & Nexus)

RED - I/O Matrix and other functions (eg LED)

Orange - Other Peripherals and I/O

Black - Clock, Reset and Control

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(GPIO)(GPIO)

(GPIO)

(GPIO)(GPIO)


(GPIO)(GPIO)

(GPIO)(GPIO)


(GPIO)(GPIO)

(GPIO_SW)(GPIO)(GPIO)(LED8)(GPIO)(GPIO)

(GPIO)(GPIO)

(RMII_CRS)

(GPIO)(GPIO)

(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)(GPIO)

(LED2)

(LED3)

(LED4)

(LED6)

(LED7)

(LED5)

(SW1)

PORSTx(5)MCU-RSTx(5,10,15)

MCU-EXTAL(6)MCU-XTAL(6)

PB0(9)PB1(9)PB2(9)PB3(9)

XTAL32(6)EXTAL32(6)

PA11(12)PA12(15)PA13(15)PA14(15)PA15(15)

PA7(14)PA8(12)PA9(12)

PA10(14)

PA1(14,15)PA2(15)PA3(14)PA4(14)

PB4(14,15)

PC11(15)PC12(13)PC13(13)PC14(13)PC15(13)

PC6(15)PC7(15)PC8(10)PC9(10)

PC10(15)

PC5(13)PC4(14)

PC0(10)PC1(5,10)PC2(11)PC3(11)

PD12(15)PD13(15)

PD6(15)PD7(15)PD8(15)PD9(15)

PD10(15)

PD5(15)PD4(15)

PD0(15)PD1(15)PD2(15)PD3(15)

PD14(15)PD15(15)

PA0(14)

PA5(15)PA6(15)

PB5(15)PB6(15)PB7(15)

PB10(15)PB11(15)PB12(15)PB13(15)PB14(15)PB15(15)

PH0 (12)PH1 (12)PH2 (12)

PH9 (10)PH10 (10)PH11 (11)PH12 (11)

PG0 (12)PG1 (12)PG2 (15)PG3 (15)PG4 (15)PG5 (15)

PG10 (11)PG11 (11)PG12 (15)PG13 (15)PG14 (11)PG15 (11)

PF14 (12)PF15 (12,15)

PE2 (13)PE3 (13)PE4 (15)PE5 (15)

PE12 (14)PE13 (15)PE14 (11)PE15 (11)

PF0 (15)PF1 (15)PF2 (15)PF3 (15)PF4 (15)PF5 (15)PF6 (15)PF7 (15)PF8 (15)PF9 (15)PF10 (15)PF11 (15)PF12 (15)PF13 (15)

PG6 (15)PG7 (15)

PH5 (14)

PE6 (14,15)

PE0 (15)PE1 (15)

PE7 (14,15)PE8 (15)PE9 (15)PE10 (15)PE11 (15)

PG8 (15)PG9 (15)

PH3 (15)PH4 (15)

PH6 (15)PH7 (15)PH8 (15)

PH13 (14)

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Calypso GPIO 1of2

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Calypso GPIO 1of2

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Calypso 176QFP

PACKAGE 1OF3 GPIO PINS1

U16A

SPC5748GHK0AMKU6

RESET29

PORST153

XTAL56

EXTAL58

PA0/GPIO0/E0UC_0_X/CLKOUT0/E0UC_13_H/WKPU19/CAN1RX24

PA1/GPIO1/E0UC_1_G/WKPU2/NMI0/CAN3RX19

PA2/GPIO2/E0UC_2_G/E2UC_0_X/ADC0_MA2/WKPU317

PA3/GPIO3/E0UC_3_G/LIN5TX/dCS4_1/ADC1_S0/EIRQ0/MII_0_RX_CLK114

PA4/GPIO4/E0UC_4_G/dCS0_1/E2UC_24_X/WKPU9/CMP1_13/LIN5RX/dSS_151

PA5/GPIO5/E0UC_5_G/LIN4TX/ULPI0_STP146

PA6/GPIO6/E0UC_6_G/dCS1_1/EIRQ1/LIN4RX/ULPI0_DIR147

PA7/GPIO7/E0UC_7_G/LIN3TX/ADC1_S8/EIRQ2/MII_0_RXD2128

PA8/GPIO8/E0UC_8_X/E0UC_14_H/ADC1_S9/EIRQ3/LIN3RX/MII_RMII_0_RXD1129

PA9/GPIO9/E0UC_9_H/dCS2_1/ADC1_S10/MII_RMII_0_RXD0130

PA10/GPIO10/E0UC_10_H/SDA0/LIN2TX/MII_1_TXD1/ADC1_S11/dSIN_1/MII_0_COL131

PA11/GPIO11/E0UC_11_H/SCL0/MII_1_TXD0/ADC1_S12/EIRQ16/LIN2RX/ULPI0_FAULT/MII_RMII_0_RX_ER132

PA12/GPIO12/E0UC_28_Y/dCS3_1/E2UC_26_Y/CMP1_15/EIRQ17/dSIN_053

PA13/GPIO13/dSOUT_0/E0UC_29_Y/E2UC_25_Y/CAN0TX/CMP1_1452

PA14/GPIO14/dSCLK_0/dCS0_0/E0UC_0_X/E2UC_23_X/CMP1_12/EIRQ4/dSS_050

PA15/GPIO15/dCS0_0/dSCLK_0/E0UC_1_G/E2UC_21_Y/WKPU10/CMP1_10/CAN0RX/dSS_048

PB0/GPIO16/CAN0TX/E0UC_30_Y/LIN0TX/E2UC_4_Y/CMP0_239

PB1/GPIO17/E0UC_31_Y/E2UC_5_Y/WKPU4/CMP0_3/CAN0RX/LIN0RX40

PB2/GPIO18/LIN0TX/SDA0/E0UC_30_Y/SD_DAT7176

PB3/GPIO19/E0UC_31_Y/SCL0/E2UC_8_X/WKPU11/LIN0RX/ULPI0_FAULT1

PB4/GPI20/ADC1_P088

PB5/GPI21/ADC1_P1/MII_1_RX_DV91

PB6/GPI22/ADC1_P2/MII_1_RXD392

PB7/GPI23/ADC1_P3/MII_1_RXD293

PB8/GPI24/ADC0_S0/WKPU25/OSC32K_XTAL61

PB9/GPI25/ADC0_S1/WKPU26/OSC32K_EXTAL60

PB10/GPIO26/dSOUT_1/CAN3TX/CMP2_O/SAI0_SYNC/E2UC_29_Y/ADC0_S2/WKPU8/CAN6RX62

PB11/GPIO27/E0UC_3_G/dCS0_0/ADC0_S3/dSS_0/MII_1_RX_CLK96

PB12/GPIO28/E0UC_4_G/dCS1_0/DO1/ENET1_TMR0/ADC0_X0101

PB13/GPIO29/E0UC_5_G/dCS2_0/ADC0_X1/MII_1_RX_DV103

PB14/GPIO30/E0UC_6_G/dCS3_0/FR_DBG1/ADC0_X2/MII_1_RXD2105

PB15/GPIO31/E0UC_7_G/dCS4_0/MLBSIG/ADC0_X3/MII_1_RXD0107

PC0/GPIO32/TDI154

PC1/GPIO33/TDO149

PC2/GPIO34/dSCLK_1/CAN4TX/E2UC_22_X/SSCM_DBG0/EIRQ5/ULPI1_CLK145

PC3/GPIO35/dCS0_1/ADC0_MA0/E2UC_23_X/SSCM_DBG1/EIRQ6/CAN1RX/CAN4RX/ULPI1_DIR/dSS_1144

PC4/GPIO36/E1UC_31_Y/FR_B_TX_EN/SD_DAT0/ULPI0_D1/SSCM_DBG2/EIRQ18/CAN3RX/dSIN_1159

PC5/GPIO37/dSOUT_1/CAN3TX/E2UC_24_X/FR_A_TX/SD_CLK/ULPI0_D0/SSCM_DBG3/EIRQ7158

PC6/LIN1TX/E1UC_28_Y/E2UC_17_Y/SSCM_DBG4/CMP0_744

PC7/GPIO39/E1UC_29_Y/CMP1_O/E2UC_18_Y/SSCM_DBG5/WKPU12/LIN1RX45

PC8/GPIO40/LIN2TX/E0UC_3_G/SD_DAT6/SSCM_DBG6175

PC9/GPIO41/E0UC_7_G/E2UC_7_Y/SSCM_DBG7/WKPU13/LIN2RX/ULPI1_FAULT2

PC10/GPIO42/CAN1TX/CAN4TX/ADC0_MA1/CMP0_O/LIN6TX36

PC11/GPIO43/ADC0_MA2/E2UC_1_Y/WKPU5/CAN1RX/CAN4RX35

PC12/GPIO44/E0UC_12_H/FR_DBG0/SD_DAT4/EIRQ19/dSIN_2173

PC13/GPIO45/E0UC_13_H/dSOUT_2/FR_DBG1/SD_DAT5174

PC14GPIO46/E0UC_14_H/dSCLK_2/E2UC_6_Y/FR_DBG2/CAN4TX/EIRQ83

PC15/GPIO47/E0UC_15_H/dCS0_2/E2UC_5_Y/FR_DBG3/EIRQ20/dSS_2/CAN4RX4

PD0/GPI48/ADC1_P4/WKPU2777

PD1/GPI49/ADC1_P5/WKPU2878

PD2/GPI50/ADC1_P679

PD3/GPI51/ADC1_P780

PD4/GPI52/ADC1_P881

PD5/GPI53/ADC1_P982

PD6/GPI54/ADC1_P1083



PD9/GPI57/ADC1_P13/MII_1_RXD194

PD10/GPI58/ADC1_P14/MII_1_RXD095

PD12/GPIO60/dCS5_0/E0UC_24_X/DO0/ENET1_TMR1/ADC0_S4100

PD13/GPIO61/dCS0_1/E0UC_25_Y/ENET0_TMR0/ADC0_S5/dSS_1102

PD14/GPIO62/dCS1_1/E0UC_26_Y/FR_DBG0/ADC0_S6/MII_1_RXD3104

PD15/GPIO63/dCS2_1/E0UC_27_Y/FR_DBG1/MLBDAT/ADC0_S7/MII_1_RXD1106

PE0/GPIO64/E0UC_16_X/SCL1/WKPU6/CAN5RX/LIN11RX18

PE1/GPIO65/E0UC_17_Y/CAN5TX/SDA120

PE2/GPIO66/E0UC_18_Y/FR_A_TX_EN/SD_DAT3/EIRQ21/ULPI0_CLK/dSIN_1156

PE3/GPIO67/E0UC_19_Y/dSOUT_1/SD_CMD/WKPU29/FR_A_RX/ULPI0_NXT157

PE4/GPIO68/E0UC_20_Y/dSCLK_1/FR_B_TX/SD_DAT1/ULPI0_D2/EIRQ9160

PE5/GPIO69/E0UC_21_Y/dCS0_1/ADC0_MA2/SD_DAT2/ULPI0_D3/WKPU30/FR_B_RX/dSS_1161

PE6/GPIO70/E0UC_22_X/dCS3_0/ADC0_MA1/ADC1_MA1/SD_CMD/EIRQ22167

PE7/GPIO71/E0UC_23_X/dCS2_0/ADC0_MA0/ADC1_MA0/SD_CLK/EIRQ23168

PE8/GPIO72/CAN2TX/E0UC_22_X/CAN3TX/SDA2/LIN6TX21

PE9/GPIO73/E0UC_23_X/SCL2/WKPU7/CAN2RX/CAN3RX22

PE10/GPIO74/LIN3TX/dCS3_1/E1UC_30_Y/SDA3/EIRQ1023

PE11/GPIO75/E0UC_24_X/dCS4_1/CLKOUT1/SCL3/WKPU14/LIN3RX25

PE12/GPIO76/E1UC_19_Y/ADC1_S13/EIRQ11/ULPI1_FAULT/dSIN_2/MII_0_CRS/MII_1_TX_CLK133

PE13/GPIO77/dSOUT_2/E1UC_20_Y/ADC1_X3/MII_0_RXD3127

PE14/GPIO78/dSCLK_2/E1UC_21_Y/ULPI1_D2/EIRQ12136

PE15/GPIO79/dCS0_2/E1UC_22_X/SCLK_2/ULPI1_D3/dSS_2137

PF0/GPIO80/E0UC_10_H/dCS3_1/SOUT_4/CAN6TX/ADC0_S8/CMP2_16/SAI0_MCLK63

PF1/GPIO81/E0UC_11_H/dCS4_1/CS3_0/SAI0_BCLK/ADC0_S9/CMP2_17/SIN_464

PF2/GPIO82/E0UC_12_H/dCS0_2/SCLK_4/SAI0_D3/ADC0_S10/CMP2_18/dSS_265

PF3/GPIO83/E0UC_13_H/dCS1_2/CS0_4/SAI0_D2/ADC0_S11/CMP2_19/SS_466

PF4/GPIO84/E0UC_14_H/dCS2_2/SOUT_5/SAI0_D1/ADC0_S12/CMP2_2067

PF5/GPIO85/E0UC_22_X/dCS3_2/CS2_0/SAI0_D0/ADC0_S13/CMP2_21/SIN_568

PF6/GPIO86/E0UC_23_X/dCS1_1/SCLK_5/SAI1_SYNC/E2UC_30_Y/ADC0_S14/CMP2_2269

PF7/GPIO87/SCLK_0/dCS2_1/CS0_5/ADC0_S15/CMP2_23/SAI1_MCLK/SS_570

PF8/GPIO88/CAN3TX/dCS4_0/CAN2TX/E2UC_15_Y/CMP0_542

PF9/GPIO89/E1UC_1_H/dCS5_0/E2UC_14_Y/WKPU22/CMP0_4/CAN2RX/CAN3RX41

PF10/GPIO90/dCS1_0/LIN4TX/E1UC_2_H/E2UC_19_Y/EOUT0/CMP1_846

PF11/GPIO91/dCS2_0/E1UC_3_H/E2UC_20_Y/WKPU15/CMP1_9/LIN4RX47

PF12/GPIO92/E1UC_25_Y/LIN5TX/E2UC_16_X/EOUT1/CMP0_643

PF13/GPIO93/E1UC_26_Y/E2UC_22_X/WKPU16/CMP1_11/LIN5RX49

PF14/GPIO94/CAN4TX/E1UC_27_Y/CAN1TX/MII_RMII_0_MDIO/ADC1_X2126

PF15/GPIO95/E1UC_4_H/ADC1_X1/EIRQ13/CAN1RX/CAN4RX/MII_RMII_0_RX_DV125

PG0/GPIO96/CAN5TX/E1UC_23_X/MII_RMII_0_MDC/ADC1_X0122

PG1/GPIO97/E1UC_24_X/MII_RMII_0_TX_CLK/ADC1_S7/EIRQ14/CAN5RX121

PG2/GPIO98/E1UC_11_H/dSOUT_3/CAN7TX/LIN11TX16

PG3/GPIO99/E1UC_12_H/dCS0_3/E2UC_1_Y/WKPU17/CAN7RX/dSS_315

PG4/GPIO100/E1UC_13_H/dSCLK_3/LIN10TX14

PG5/GPIO101/E1UC_14_H/E2UC_2_Y/WKPU18/LIN10RX/dSIN_313

PG6/GPIO102/E1UC_15_H/LIN6TX/CLKOUT1/E2UC_3_Y/CMP0_1/EXTREGC38

PG7/GPIO103/E1UC_16_X/E1UC_30_Y/CLKOUT0/E2UC_2_Y/WKPU20/CMP0_0/LIN6RX37

PG8/GPIO104/E1UC_17_Y/LIN7TX/dCS0_2/CAN7TX/EIRQ15/dSS_234

PG9/GPIO105/E1UC_18_Y/dSCLK_2/E2UC_0_X/WKPU21/CAN7RX/LIN7RX33

PG10/GPIO106/E0UC_24_X/E1UC_31_Y/ULPI1_D4/SIN_0138

PG11/GPIO107/E0UC_25_Y/CS0_0/CS0_2/ULPI1_D5/SS_0/SS_2139

PG12/GPIO108/E0UC_26_Y/SOUT_0/E2UC_12_Y/MII_0_TXD2/ADC1_S2116

PG13/GPIO109/E0UC_27_Y/SCLK_0/E2UC_13_Y/MII_0_TXD3/ADC1_S1115

PG14/GPIO110/E1UC_0_X/LIN8TX/ULPI1_D0/SIN_2134

PG15/GPIO111/E1UC_1_H/SOUT_2/ULPI1_D1/LIN8RX135

PH0/GPIO112/E1UC_2_H/E2UC_11_Y/MII_RMII_0_TXD1/ADC1_S3/dSIN_1117

PH1/GPIO113/E1UC_3_H/dSOUT_1/E2UC_10_Y/MII_RMII_0_TXD0/ADC1_S4118

PH2/GPIO114/E1UC_4_H/dSCLK_1/E2UC_9_Y/MII_RMII_0_TX_EN/ADC1_S5119

PH3/GPIO115/E1UC_5_H/dCS0_1/MII_0_TX_ER/MII_1_TXD2/ADC1_S6/dSS_1120

PH4/GPIO116/E1UC_6_H/SOUT_3/SCL3/ULPI0_D4162

PH5/GPIO117/E1UC_7_H/SDA3/ULPI0_D5/SIN_3163

PH6/GPIO118/E1UC_8_X/SCLK_3/ADC0_MA2/ADC1_MA2/ULPI0_D6164

PH7/GPIO119/E1UC_9_H/dCS3_2/ADC0_MA1/CS0_3/ADC1_MA1/ULPI0_D7/SS_3165

PH8/GPIO120/E1UC_10_H/dCS2_2/ADC0_MA0/ADC1_MA0/SD_RST/SD_WP166

PH10/GPIO122/TMS148

PH11/GPIO123/dSOUT_3/CS0_0/E1UC_5_H/ULPI1_D6/SS_0140

PH12/GPIO124/dSCLK_3/CS1_0/E1UC_25_Y/141

PH13/GPIO125/SOUT_0/dCS0_3/E1UC_26_Y/EOUT1/dSS_39

PH14/GPIO126/SCLK_0/dCS1_3/E1UC_27_Y/EIN_ERR10

PH15/GPIO127/SOUT_1/E2UC_3_Y/E1UC_17_Y/EOUT08

PH9/GPIO121/TCK155

TP16 SILK = PH14TP17 SILK = PH15

PH14PH15

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Calypso GPIO 2 of 2

(USB1_NXT)(USB1_STP)

(USB1_RST)

(ENET_RST)

Green - I/O Matrix (dedicated)

Key to text colours:Purple - Comms Physical Interfaces

Blue - Debug (JTAG & Nexus)

RED - I/O Matrix and other functions (eg LED)

Orange - Other Peripherals and I/O

Black - Clock, Reset and Control


(GPIO)


(GPIO)(GPIO)

(GPIO)

(GPIO)(GPIO)(LED1)

PI11(12,15)

PI7(11,15)

PI5(11)PI4(11)

PI0(14,15)PI1(14,15)PI2(14,15)PI3(14,15)

PI6(15)

PI8(15)

PI12(15)PI13(15)PI14(15)PI15(15)

PJ0(15)PJ1(15)PJ2(15)PJ3(15)PJ4(14)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


Calypso GPIO 2of2

8 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


Calypso GPIO 2of2

8 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


Calypso GPIO 2of2

8 15

___ ___X

Calypso 176QFP

PACKAGE 3OF3 GPIO PINS2

U16C

SPC5748GHK0AMKU6

PI0/GPIO128/E0UC_28_Y/LIN8TX/SDA1/SD_DAT3172

PI1/GPIO129/E0UC_29_Y/SCL1/SD_DAT2/WKPU24/LIN8RX171

PI2/GPIO130/E0UC_30_Y/LIN9TX/SDA2/SD_DAT1170

PI3/GPIO131/E0UC_31_Y/SCL2/SD_DAT0/WKPU23/LIN9RX169

PI4/GPIO132/E1UC_28_Y/SOUT_0/ULPI1_STP143

PI5/GPIO133/E1UC_29_Y/SCLK_0/CS2_1/CS2_2/ULPI1_NXT142

PI6/GPIO134/E1UC_30_Y/CS0_0/CS0_1/CS0_2/DO0/SS_0/SS_1/SS_211

PI7/GPIO135/E1UC_31_Y/CS1_0/CS1_1/CS1_2/DO112

PI8/GPIO136/E2UC_15_Y/ADC0_S16/MLBCLK/MII_1_RX_CLK108

PI11/GPIO139/E2UC_14_Y/ENET0_TMR1/ADC0_S19/dSIN_3111

PI12/GPIO140/dCS0_3/dCS0_2/MII_1_TX_EN/ADC0_S20/dSS_2/dSS_3112

PI13/GPIO141/dCS1_3/dCS1_2/MII_1_TXD3/ADC0_S21113

PI14/GPIO142/SAI2_D0/ADC0_S22/SIN_076

PI15/GPIO143/CS0_0/dCS2_2/SAI2_MCLK/ADC0_S23/SS_075

PJ0/GPIO144/CS1_0/dCS3_2/SAI2_SYNC/E2UC_19_Y/ADC0_S2474

PJ1/GPIO145/SOUT_0/SAI2_BCLK/ADC0_S25/SIN_173

PJ2/GPIO146/CS0_1/CS0_2/CS0_3/SAI1_D0/ADC0_S26/SS_1/SS_2/SS_372

PJ3/GPIO147/CS1_1/CS1_2/CS1_3/SAI1_BCLK/ADC0_S2771

PJ4/GPIO148/SCLK_1/E1UC_18_Y/E2UC_4_Y/EIN_ERR5

PI4PI5

PI7

PI11

PI0

PI6

PI8

PI12PI13PI14PI15

PI1PI2PI3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(Enable)

CAN & LIN Physical

EN = PER_HVA enables Transceiver and sets I/O for V DD_HV_A

(LIN0_TX)

(LIN0_RX)

(CAN0_RX)

(CAN0_TX)

CAN0 Physical Interface

Master Mode Pullup EnableLIN0 Physical Interface

(LEF = 20K Baud)

Total currentthrough resistors(LIN Bus at GND)= 12mA (0.144W)

Each resistor spec = 0.1W (0.2W total)

(Wake)

WAKE = GND ensures no spurious wakeups

MC33662LEF LIN transceiver is newer version of 3366 1 offering:

- Full LIN compliance (33661 no longer compliant)- Improved ESD protection on LIN pin up to 15KV- Improved ESD on Wake and VSUP Pins- Other EMC and performance improvements

See freescale.com for more details

BatteryReversepolarity &PulseProtection

All CAN and LIN signals arein power domain VDD_HV_A.

All interfaces will work at3.3V or 5.0V (PER_HVA)

CAN termination resistorfootprint. Place onunderside of PCB

VDD - 5.0V input supply for CAN transceiver (4.5 t o 5.5V)

VI/O - determines the signal level on MCU TX and RX pinsand can range from 2.8 to 5.5V

STB - High for Standby mode, pulled low for normal mode.

312-80788- MC33901WEF -> SO8_1P27_4X5IC INTERFACE CAN HS 60KB/S-1MB/S 4.5-5.5V SOIC8Replaced with TJA1044GT/3

PER_HVA

GND

GND

GNDGND

GND

GND

GNDGND

GND

PER_HVA5V0_SR

PB3(7)

PB2(7)

PB1(7)

PB0(7)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


CAN and LIN

9 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


CAN and LIN

9 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


CAN and LIN

9 15

___ ___X

C60.1UF

TPV15

SILK = CAN0-S

D1SBR3U30P1

A C

C52.2uF

R4 0

P3

HDR 1X4 RA

1234

R128120.0

R1 2.0K

P5

HDR 1X4 RA

SILK = CAN

1234

TJA1044GT/3

U20

TXD1

GN

D2

VC

C3

RXD4

VIO

5

CANL6

CANH7

STB8

VSUP1DNP

1

C732.2uF

R17 0

C770.1UF

D2 SBR3U30P1AC

R3 0

R119 4.7K

R141 0

R2 2.0K

C692.2uF

R142 0

U1

MC33662BLEF

RXD1

EN2

WAKE3

TXD4

GND5LIN6VSUP7INH8

J16 HDR 1X2DEFAULT(CLOSED)

12

C700.1UF

J5

DNP

1 2

CAN0-S

CAN0_RX

LIN0-RX

LIN0-TXLIN0-LIN

CAN0_TX

LIN0-VSUP

CAN0-CANH

CAN0-CANL

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OpenSDA interface

OpenSDA INTERFACEJTAG CONNECTOR

OpenSDA INTERFACE

RXD_USB_UART

TXD_USB_UARTTDO

TMS

Note:For PowerPC deviceswith JCOMP pin available,extra circuitry isneeded to support it

JCOMP(Layout Note:Route USB_N and USB_P with90 Ohm Differential Pair.Keep tracksas short as possible)

TCLK

TDI

Default AA -> K20 internal regulator 3V3 outputB -> external power supply through J11 as 1-2

USB Power Switch

(Layout Note: Place 100uF & 1.0uF close to the OUTpin)

P3V3_SDA

P5V_SDA

P3V3_SDA

P5V_SDA

P3V3_SDA

P3V3_SDA

GND

GND

GND

GND

GND

GND GND

GND

GNDGND

GND

GND

GND

P3V3_SDA PER_HVA

GND

GND

P3V3_SDA PER_HVA

GND

GND

P3V3_SDA PER_HVA

GND

GND

GND

PER_HVA

PER_HVA

P3V3_SDA

GND

PER_HVA

GND

P3V3_SDA PER_HVA

GND

GND

PER_HVA

GND

PER_HVA

PER_HVA

K20_VOUT33

K20_VOUT33

P3V3_SDA

3V3_SR

GND GND

GND

GND

5V_TGT_OUT

GND

P5V_SDA

P5V_SDA

MCU-RSTx (5,7,15)

PC9 (7)

PC8 (7)PC1 (5,7)

PH10 (7)TMS_HEADER(5)

TCLK_HEADER(5)

TDI_HEADER(5)

PH9 (7)

PC0 (7)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

D


OpenSDA

10 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

D


OpenSDA

10 15



Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

D


OpenSDA

10 15

___ ___X

SW3SKRPABE010SILK = BOOT

1 4

2 3

L1

330 OHM

1 2

TP12

SILK = PH10

TP15SILK = PC8

U6

74LVC2T45GM,125

1A6 VCCA7

VCCB8

2A5

DIR3

GND4

1B1

2B2

C102

1.0UF

TP3SILK = VBAT

C23100uF

C1912PF

C24.7UF

MK20DX128VFM5

U8

VDD11

VSS12

VDDA7

VSSA8

VBAT11

JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH512

JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH613

JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH714

JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH015

NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P316

EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN017

XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT118

ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P520

ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB21

ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS23

CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/I2S0_TX_BCLK/LLWU_P724

PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P825

PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P926

CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P1027

CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS28

PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P1429

ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT30

ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P1531

PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT132

VREGIN6

VOUT335

USB0_DM4

USB0_DP3

EXTAL3210

XTAL329

RESET19

ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P622

EPAD33

U2

74LVCH1T45

VCCA1

GND2

A3

B4

DIR5 VCCB

6

C1810uF

R13 10K

R1810K

R24 270

R3810K

C1112PF

L2

330 OHM

1 2

A

B

R145

0

R3144.2K

DS1GREEN

AC

U3

74LVCH1T45

VCCA1

GND2

A3

B4

DIR5 VCCB

6

R43

10K

TP10

SILK = PH9

TP13

SILK = PC9

U12B

74LVC2G08

5

63

U14

74LVC1G08

NC5

Y4

GND3

B1

A2

VCC6

C160.1UF

DS14GREEN

AC

R251.0K

R39

10K

R56

10K

C1710uF

R2010K

R14 10K

R22

1.0K

1%

J1

USB_MICRO_AB

SILK = SDA

VBUS1

D-2

D+3

ID4

GND5

SH

ELL1

6

SH

ELL2

7S

HE

LL3

8

SH

ELL4

9

SHELL510

U9

NCP380

OUT1

ILIM2

IN6

GN

D5

EN4

FLAG3

EP

7

R146 270

TP2

TP4

SILK = SDA_JTAG_RST

R33

10K

VCC

GND

U12A

74LVC2G08

1

27

84

U5

74LVC2T45GM,125

1A6 VCCA7

VCCB8

2A5

DIR3

GND4

1B1

2B2

C72.2uF

TP14

SILK = PC1

TP11

SILK = PC0

R27

10K

R10 33

J6

HDR 2X5

1234

6 578910

U4

74LVC2T45GM,125

1A6 VCCA7

VCCB8

2A5

DIR3

GND4

1B1

2B2Y1

8MHZ

1 2

R9 33

R32

10K

TP1

TC_VBAT_TP

SDA_JTAG_RST

SDA_JTAG_TCLK

SDA_JTAG_TDISDA_JTAG_TDO

SDA_JTAG_TMS

SDA_EXTALSDA_XTAL

SDA_USB_DNSDA_USB_DP

SDA_LED

RST_K20

OUT_EN_PASSBOOT_ENTRY

JCOMP_K20TXD_K20RXD_K20TCLK_K20TDI_K20TDO_K20

RXD_TXD_ENTMS_K20VTGT_ENU9_FAULT#

TCLK_K20TDI_K20

TCLKTDIOUT_EN_PASS

TDO_K20TXD_K20

TMS_K20JCOMP_K20

TMS

OUT_EN_PASS

RST_K20

RXD_K20

RXD_TXD_EN

TMS

TDI

TCLK

SD

A_U

SB

SH

IELD

TC_SDA_USB_ID_TPSDA_USB_CONN_DPSDA_USB_CONN_DN

SDA_JTAG_RST

U9_FAULT#

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB (Type A Host and Type AB OTG)

USB Power Switch

(USB1_D7)(USB1_D6)(USB1_D5)(USB1_D4)(USB1_D3)(USB1_D2)(USB1_D1)(USB1_D0)

(USB1_DIR)

(USB1_STP)(USB1_NXT)

(USB1_RST Active Low)

(Select 60MHz CLKOUTwith 24MHz XTAL)

(ID=GND forHOST mode)

(20K for HOST)

(Layout Note: Place Series Termination resistor (30 Ohm) close to USB IC)

(Layout Note: Route USB_N and USB_P with90 Ohm Differential Pair. Keep tracksas short as possible)

General Layout Note. Recommendation is to keep alltracks between MCU and USB PHI less than 3"

USB Signalsare inpowerdomainVDD_HV_A

The USBinterfaceonlysupports3.3Voperation.All I/Osignals mustbe 3.3V. IfVDD_HVA isset to 5V,USB MCUpads must beleft astri-state with nopullups orseriesresistors tobe removed

Layout Note:Place caps &resistor asclose todevice aspossible

211-78945 -CON 5 USB_MICRO_AB_RECEPTACLE RA SKT SMT 0.65MM SP 122H AUChanged to211-75297-USB_TYPE_ACON 4 SKT RA SMT -- AU USB A

(Layout Note: Place 100uF & 1.0uF close to the OUTpin)

3V3_SR

GNDGND

GND

GND GND

GND GND

GND

GND

GND

3V3_SR

3V3_SR

GND

5V0_SR

GND

GND 5V0_SR

GND

GND

GND

GND GND

GND

5V0_SR

PI4(8)PI5(8)

PC2(7)PC3(7)

PG15(7)PE14(7)PE15(7)PG10(7)PG11(7)PH11(7)PH12(7)

PG14(7)

PI7(8,15)

Drawing Title:


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DEVKIT-MPC5748G

B


USB Type A / Type AB

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B



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B



11 15

___ ___X

R108 0

R688.06K1%

C380.1UF

TPV6SILK = FAULT

R81 30

R90 0

R107 0

R72 1M

C3012PF

R70 0

C470.1UF

R86 0

R106 0

C4910uF

U15

USB3340

CLKOUT1

NXT2

DATA03 DATA14 DATA25 DATA36 DATA47

REFSEL08

DATA59 DATA6

10

REFSEL111

DATA713

REFSEL214

SPK_L15

SPK_R16

VDD3P320

VBAT21

RBIAS24

XO25

REFCLK26

RESET27

VDD1P8_2828

STP29

VDD1P8_3030

DIR31

VDDIO32

GN

D33

CPEN17

VBUS22

ID23

DP18

DM19

NC_1212

C2912PF

Y2

24MHZ CRYSTAL

1 4

32

R6910K

C421.0UF

L6330OHM

12

R74 0

C34

1000pF

R99 0

C5310uF

R371.0K

L4 26OHM1 2

V D- D+ G

USB_TYPE_A_FEMALE

J9

S1

A1A2A3A4

S2

U13

NCP380

OUT1

ILIM2

IN6

GN

D5

EN4

FLAG3

EP

7

R1000

R84 20K

C3710uFR83 0

R95 0

C321.0UF

C2010uF

C25100uF

C411000pF

R4510K

C331.0UF

R80 0

R6644.2K

R92 0

US

B_A

_VD

D3.

3

A_XO

USB_A_EN

USB_A_VBUS

USB_NUSB_P

USB_A_5V

A_XI

USB_IDUSB1_CLK

US

B_A

_VD

D1.

8

USB_A_PWR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MCU can drive the Pulluprequired by this signal

RMII0_TXD_0RMII0_TXD_1

RMII0_TXEN

RMII0_MDC

RMII0_MDIO

PHY_INT_1

PHY_RESET_B must be a GPIOtoggeld after CLKIN is active.

Reset Control:- Reset from MCU Reset Out (will reset with MCU)- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in resetwhile reset config data can be driven onto pins to change mode etc.

Layout Note:PLEASE ROUT TX/RX N/P SIGNALSSTRAIGHTFORWARD AND AVOIDT-STUBS ON RESISTOR PADINTERCONNECTION

(Layout Note:100 Ohm Differential Pair.Keep tracks as short as possibleMatch pair within 5 mils

RMII0_RXD_1RMII0_RXD_0

RMII0_CRS_DV

RMII0_RXER

Ethernet Physical Interface

VDDIO_ENET

3V3_SR

VDDIO_ENET

VDDA_ENET

VDDA_ENET

VDDIO_ENET

VDDIO_ENET3V3_SR

3V3_SR

GND

GND

GND GND

GND GND

GND GND

GND

GND

GND

VDDIO_ENET

GND

VDDIO_ENET

GNDGND

GND

GND

GND

PH2 (7)

PH1 (7)PH0 (7)

PG0(7)

PF14(7)

PA9 (7)PA8 (7)

PF15 (7,15)

PA11 (7)

PG1(7)

PI11(8,15)

RST-OUTx(5)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

C


Ethernet

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C


Ethernet

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Ethernet

12 15

___ ___X

C3624PF

R7610.0KDNP

R7310.0K

R716.49K R85

10.0KDNP

C2710UF

R48 50

C52

4.7UF

C640.1UFDNP

J10

RB1-125BAG1A

TD+1

TD-2

TCT3

NC14

NC15

RCT6

RD+7

RD-8

L111

L212

L313

L414

SH

19

SH

210

R670

R9610.0KDNP

R49 0DNP

R118100

C35100PF

J8HDR 1X2

DNP

12

R10449.9DNP

C59

1.0 UF

R4610K

R59 0DNP

R109100

R93 0

D3

BAT54AWT1G

2

3

1

C310.1UFDNP

R791.5KDNP

R11049.9DNP

R7549.9DNP

R58

0

C51

0.1UF

R88 33

R8249.9DNP

R781.5KDNP

R101 33 R77 33

KSZ8081RNACA

U17

VD

D_1

V2

1

VD

DA

_3V

32

RXM3RXP4

TXM5TXP6

XO7

XI8

REXT9

MDIO10

MDC11

RXD112RXD013

VD

DIO

14

CRS_RV/PHYAD1/PHYAD015

REF_CLK16

RXER17

INTRP18

TXEN19

TXD020

TXD121

GN

D1

22

LED0/ANEN_SPEED23RST

24

GN

D2

25

R1030

C56

0.1UF

L5120OHM

DNP

21

C460.1UF

R102 33

J7HDR 1X2DNP

12

R890DNP

R94 33

C50

0.1UF

C400.1UF

C430.1UF

Y3

25MHZ

1

4

3

2 C3924PF

R970DNP

ENET1_TCT

ENET1_TX_PENET1_TX_N

ENET1_RX_PENET1_RX_N

ENET_1_RX_RDIV

RMII_XTALO

RMII_XTALI

RXD1RXD0

RMII0_INT_B

LED1/SPEED

CRS_DV

RXCLK

ENET1_RCT

ENET_1_TX_RDIV

VDDPLL_1.2V

PHY_RST_B

CPU_PER_1_RST_B

REXT

LED2_LINK

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FlexRAY Physical Interface

FlexRAYdebugconnector

Decoupling.Place next to power pins.

NormalEN STBN1

SleepGo to SleepRec Only 0

111

MODE

0 00

VBAT VBUF VCC VIO

(FR_A_TX)

(FR_A_RX)(FR_A_TX_EN)

(FR_DBG0) (FR_DBG1)(FR_DBG2) (FR_DBG3)

Crimped lead - 279-9522Receptacle housing - 279-9156

Bus voltage +/- 12V (VBAT = 12v)Components spec'd for 12V operation

All Signals are inpower domain VDD_HV_A.

FlexRAY interface willwork at 3.3V or 5.0V(PER_HVA)

BGE: Bus Guardian Enable. Pullhigh to enable transmitter

STBN: Standby Input. Pull Highfor non standby mode

EN: Enable Input. PUll high toenable

Note on VBAT:- Operational range is 4.45V to 60V- Undervoltage detection is max 4.715V

On EVB this is supplied from 5v, In theory thisshould be to battery with 60uS delay betweenapplying Vbat and I/O voltages. If necessary,12V can be externally supplied by removing theresistor and connecting pad to 12v

GND

GND

PER_HVA 5V0_SR

GND

PER_HVA

FRBATA 5V0_SR PER_HVA

GND

FRBATA

GNDGND

PC12(7)PC14(7)

PC15(7)PC13(7)

PC5(7)PE2(7)PE3(7)

Drawing Title:


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DEVKIT-MPC5748G

B



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B



13 15



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B



13 15

___ ___X

R34 10K

C2210uF

TPV5SILK = BATA

R4110KDNP

TPV2 C94700pF

C310uF

P1

DNP

SILK = FR_DBG1 23 4

R2610KDNP

L3

DLW43SH

21

4 3

R23471%

R63 0

TPV8

R30471%

C40.1UF

TPV7

C810PF

R62 0

C1210PF

R42 0

R47 10K

R61 0

TJA1081B

U10

INH1

EN2

VIO

3

TXD4

TXEN5

RXD6

BGE7

STBN8

RXEN9

ERRN10

VB

AT

11

WAKE12

GN

D13

BM14

BP15

VC

C16

P2

SILK = FLEXRAY

12

C140.1UF

R28 10K

R36 10K

FRA-JRXD

FRA-BGE

FRA-JTXDFRA-JTXEN

FRA-BM FRA-DATA-B

FRA-BP

FRA-INH2

FRA-RXEN

FRA-DATA-A

FRA-ERRNFRA-WAKE

FRA-EN

FRA-STBN

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Switches are hard wired to 3.3V rather than 5V so i t's not possible to drive 5V into a 3.3V pad (which would cause damage)Similarly, the LED's are active low with 3.3v suppl y so can be safely coupled to pads on either 3.3V o r 5V domainsThe ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage

User Pushbutton Switches (Active High)

User Peripherals (Led's, Switches and ADC Pot)

User LED's (Active Low)

ADC Input Pot and Test Point

(ADC1_P[0])(USR_LED1)

(USR_LED2)

(USR_LED3)

(USR_LED4)

(PB_SW1)

(PB_SW2)

(USR_LED5)

(USR_LED6)

(USR_LED7)

(USR_LED8)

Micro SD CARD HOLDER

(SDHC_DATA0)(SDHC_DATA1)(SDHC_DATA2)(SDHC_DATA3)

(SDHC_WP) PH8 -Not used for Micro SD Card

(SDHC_CD) WKPU2

(SDHC_CLK)

(SDHC_CMD)

3V3_SR

PER_HVA

GND

PER_HVA

GND

GND

GND

GND

GND

GND

3V3_SR

3V3_SR

3V3_SR

GND

PJ4(8)

PA0(7)

PA10(7)

PA4(7)

PA7(7)

PC4(7)

PH13(7)

PH5(7)

PA1(7,15)

PE7(7,15)

PE6(7,15)

PI3(8,15)PI2(8,15)PI1(8,15)PI0(8,15)

PE12 (7)

PA3 (7)

PB4 (7,15)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


User Peripherals

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User Peripherals

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User Peripherals

14 15

___ ___X

R136 270

R15410KDNP

R15710K

DS6SILK = PH13 AC

DS10SILK = PA0 AC

R15510KDNP

R114 270

R120 270

R14810KDNP

C720.1UF

R139 270

DS9SILK = PJ4 AC

TP5SILK = ADC_PB4

1

SD/MMC SKT

J15

CD-A10

SH111

SH212

SH313

SH414

DAT21

CD/DAT32

CMD3

VDD4

CLK5

VS

S6

DAT07

DAT18

CD-B9

C850.1UF

DS5

GREENSILK = PA7 AC

R131 0

R132 270

R14710KDNP

C8610uF

R156 0

R15210KDNP

SW2SKRPABE010

SILK = SW2_PE12

1 4

2 3

SW4SKRPABE010

SILK = SW1_PA3

1 4

2 3

DS7SILK = PC4 AC

R1110K

DS8SILK = PH5 AC

R123 270

R115 220

DS4

RED

SILK = PA10 AC

DS11SILK = PA4 AC

R151 22

R129 270

RV15K

13

2

R15310KDNP

R13710K

PI3PI2

PI1PI0

CD_SWPA1

PE7

PE6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NOTE: J1,J2,J3 and J4: Arduino UNOcompatible headers.J5 and J6: Arduino Mega compatible headers.

GPIO Connectors

PER_HVA

PER_HVA

PER_HVA

GND

GND

GND

GND

GND

5V0_SR3V3_SR

PER_HVA

PER_HVA

12V_IN

PC10 (7)

PG9(7)

PA12(7)PA13(7)

PI7(8,11)PG6(7)PG7(7)PG8(7)

PI1(8,14)

PF1(7)PF0(7)

PA2(7)

PI0(8,14)

MCU-RSTx(5,7,10)

PF9(7)PF8(7)

PF4(7)PF6(7)

PB4(7,14)PB5(7)

PD0(7)

PD2(7)

PD9 (7)PD8 (7)

PD7 (7)PD6 (7)PD5 (7)

PC11 (7)

PF12 (7)PF13 (7)PC6 (7)PC7 (7)PI2 (8,14)

PD4 (7)

PD10 (7)PD12 (7)

PA15(7)

PF5(7)PF7(7)

PB6(7)

PF2(7)

PA1(7,14)

PE5 (7)PE4 (7)PE0 (7)PE1 (7)

PG4 (7)

PJ0 (8)PJ1 (8)

PG12(7)PG13(7)

PI8(8)PI11(8,12)PI12(8)PI13(8)

PH7 (7)PH6 (7)PJ3 (8)

PI14(8)PI15(8)

PD15 (7)PD14 (7)PD13 (7)PH8 (7)

PH4 (7)

PI3 (8,14)

PG2 (7)PG3 (7)

PF11(7)

PD3(7)

PA6(7)

PF3(7)

PA5(7)

PA14(7)

PB10(7)

PB15(7)

PB11(7)

PB14(7)

PB12(7)PB13(7)

PE6(7,14)

PJ2 (8)

PE7(7,14)

PD1(7)

PE8(7)

PF10(7)

PE9(7)

PB7(7)

PE10(7)

PH3 (7)

PE11(7)

PG5 (7)

PE13(7)

PI6(8)

PF15(7,12)

Drawing Title:


Date: Sheet of

Page Title:


SCH-29030 PDF: SPF-29030 D1

DEVKIT-MPC5748G

B


GPIO Connectors

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DEVKIT-MPC5748G

B


GPIO Connectors

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GPIO Connectors

15 15

___ ___X

R6

4.7K

DN

P

J12

CON_2X10

12

34 6

5 78

910

1112

1314

1516

1718

1920

R5

4.7K

DN

P

J2

SKT_2X8

12

346

578

910

1112

1314

1516

C83

2.2uF

D7SBR3U30P1

AC

J14SKT_2X8

12

34 6

5 78

910

1112

1314

1516

J13

SKT_2X8

12

34 6

5 78

910

1112

1314

1516

R7

4.7K

DN

P

J3CON_2X10

12

346

578

910

1112

1314

1516

1718

1920

J4

CON_2X10

12

346

578

910

1112

1314

1516

1718

1920

R8

4.7K

DN

P

Date post:	21-Feb-2020
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