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DfR Advanced Packaging

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description of several advanced packaging technologies along with issues and resolutions.
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  • 1. Advanced PackagingDfR Solutions Open HouseDecember 14, 2011Presented by: Greg Caswell 2004 -2200011070

2. Agendao Package on Package -3D(PoP)o System in Package 3D (SiP)o Through Silicon Via (TSV)o Bottom Terminated Components 2004 - 200107o QFNo LFCSPo .3 mm pitch CSPo Copper Wire Bonding 3. Roadmap vs Market Application 2004 - 200107 4. Benefits of PoPo The benefits of PoP are well known. They includeo Less board real estateo Better performance (shorter communication paths 2004 - 200107between the micro and memory)o Lower junction temperatures (at least compared tostacked die)o Greater control over the supply chain (opportunity toupgrade memory and multiple vendors)o Easier to debug and perform F/A (again, compared tostacked die or multi-chip module or system in package)o Ownership is clearly defined: Bottom package is thelogic manufacturer, the top package is the memorymanufacturer, and the two connections (at least for one-pass)are the OEM 5. Benefits of PoPo The benefits of PoP are well known. They includeo Less board real estateo Better performance (shorter communication paths 2004 - 200107between the micro and memory)o Lower junction temperatures (at least compared tostacked die)o Greater control over the supply chain (opportunity toupgrade memory and multiple vendors)o Easier to debug and perform F/A (again, compared tostacked die or multi-chip module or system in package)o Ownership is clearly defined: Bottom package is thelogic manufacturer, the top package is the memorymanufacturer, and the two connections (at least for one-pass)are the OEM 6. Smartphone advancements aided by PoP technologyand cost of ownership benefits.PoP addresses integration challenges to enablesemiconductor advancements . . . 2004 - 200107. . . to cost affectively deliver physicalworld benefits. 7. Stacked Packages = PoP 3D 101PoP 2004 - 200107Double stackTriple stackDouble stackCourtesy: ASE 8. 2004 - 2001078Thermal Comparison 9. PoP Assembly Processo Assembly of PoP can be throughone or two reflowso Most commonly singlereflow (aka, one-pass)o Top package is typicallydipped before placemento Flux (sticky) or solder paste 2004 - 2001079 10. 1st Generation PoP Infrastructure DevelopmentOEMsArchitecturestacking 2004 - 20010712 major OEMs in Handset and DSC market adopting PoPIndustryStandardsJEDEC JC.11.2 Design guide, JC11.11 POD, JC-63 pin outsEquipment Panasonic, Siemens, Fuji, Unovis, Assemblon, HitachiEMS / ODM 5 major EMS providers in production or developmentLogic IDM 15 major IDMs adopted PoPMemory IDM 8 major Memory suppliers adopted PoPAmkorFull service Develop, Design, Model, Standards, bottom,top PoP, Modules, pre-stacked engineering samples, BLRPractical Components stocks Amkor 12, 14 & 15mm bottom / top DC sampleswww.amkor.com Design, stacking, test and Brd level reliability (joint study papers) 11. Design Factors Impacting Warpage Die Die size Die Thickness 2004 - 200107o Moldo Material propertyo Shrinkageo Thickness Laminate Substrate Properties Thickness Cu ratio Routing Die attach Material property Thickness 12. Package Warpageo Due to mismatch in CTE betweenthe substrate, mold compoundand dieo Die attach can also play a roleo High Tg mold compounds areused to balance CTE mismatchbetween die and substrateo Effect of mold compoundbecomes negligible at reflowtemperatures 2004 - 20010712 13. Warpage and Yields 2004 - 20010713 14. Warpage and Reflow Profile 2004 - 20010714Ramkumar, 2008 European Electronic Assembly Reliability Summit 15. 1st Gen PoP Technologies limit PoP I/O and Bottom StackedDie Density Requiring New Technologyo Die stacking in bottom package requires thicker mold capo New memory architectures require higher I/O interfaceso Higher Semiconductor density requires package size reductiono Thin form factors and increased battery size require thinner PoP stackso Improved warpage control required when go thinner with higher densityo A new bottom PoP technology is needed to continue growth 2004 - 2001070.50mm pitch Multiple die in bottom package 16. Thru Mold Via Technology (TMV)o Enabling technology for next generation PoP reqmtso Improves warpage control and PoP thickness reductiono TMV removes bottlenecks for fine pitch memory interfaceso Increases die to package size ratio (30%)o Improves fine pitch board level reliabilityo Supports Wirebond, FC, stacked die and passive 2004 - 200107integration 17. Construction and package stack-up for the TMV PoPTest VehicleReference : "Surface Mount Assembly and Board Level Reliability for HighDensity PoP (Package on Package) Utilizing Through Mold ViaInterconnect Technology - Joint Amkor and Sony Ericsson", Paper 2004 - 200107 18. CCaatteeggoorriieess ooff SSiiPP eexxaammpplleess ooff 33DDHorizontal PlacementStackedStructure 2004 - 200107Interposer TypeInterposer-lessTypeWire Bonding Type Flip Chip TypeWire BondingTypeWire Bonding +Flip Chip Type Flip Chip TypeTerminal Through Via TypeEmbedded StructureChip(WLP) Embedded+ Chip on Surface Type3D Chip EmbeddedTypeWLP Embedded + Chip on Surface Type 19. 2004 - 200107SiP: from Die to Package to Hybrid StackingThe Road to 3D Packaging~2010 2011 2012 2013die stacking8 dies4 diesTRD PoPPIP FCCSPaMAP PoPaWLP PoPaMAP PoP(Cu pillar)Bare-die FC PoP3D IC PoPExposed-die aMAPPoP2.5D IC SiPCoC FBGAHybrid FCCSPASICEDS PoPaEDSi PoPCourtesy: ASE 20. TSV DevelopmentCourtesy:ASE 2004 - 200107 21. Silicon Interposer 2004 - 200107Chip 1 Chip 2Si Interposer65 nm ASICSi Interposer w/ TSVSubstrateCourtesy ASE 22. 2004 - 200107XBit: Aug 17, 2011:Samsung announcementof 32 Gbit Memory withTSVSamsung TSV Implementation 23. Through-Silicon-Viaso Through Silicon Vias (TSV) are the next generation 2004 - 200107technology for system in package deviceso Similar to plated through holes in a PCBo Promised advantages includeo Thinner packageso Greater level of integration between active die.o Process still being optimized and cost must be reducedfor widespread adoption. 24. TSV (cont.) TSV is rarely justified by just miniaturization alone More cost-effective to thin, stack and wire bond Cost can be 2X-4X price of flip chip ($200/wafer is the goal)and 5X-10X the price of wire bonding TSV will be justified byperformance Increase in inter-die I/O Increase in bandwidth Decrease ininterconnect length 2004 - 20010724http://www.intel.com/technology/itj/2007/v11i3/3-bandwidth/6-architectures.htm (August 22, 2007) 25. TSV Processeso Via First, before Front End of Line (FEOL) 2004 - 200107o Vias etched in bare wafer prior to fabo Not likelyo Back End of Line (BEOL)o Via First, before BEOLo Via Last, after BEOLo Vias can be created at various stages of the processo By the wafer provider, IC manufacturer, or packaging house 26. TSV Process BEOL 2004 - 200107 27. How Can Through Silicon Vias (TSV) Fail?o Three primary failure mechanisms 2004 - 200107o Cracking of the Copper Platingo Cracking of the Silicon /Change in Resistance of Silicono Interfacial Delamination of Via Wall from Silicono Challengeso The exact process and architecture (materials, design) for TSVhas yet to be finalizedo Can lead to large changes in stress state 28. TSV Designo Via walls can be straight (etch) or tapered (laser)o Vias can be filled (likely) or not filled (aka, annular) 2004 - 200107 29. TSV Designo Depending on Via First or Via Last design layout, TSV 2004 - 200107can have a floor of coppero Also known as Carpeted or NailheadingS. Barnat et. al., EuroSIME 2010 30. TSV Materialso Will the via be filled?o If yes, with what material? 2004 - 200107o Coppero Tungsteno ConductivepolymerWhy Tungsten?Low CTE mismatch withSilicon 31. Via Fill (Tradeoffs)o Solid Fill (copper, nickel, tungsten, aluminum, etc.) 2004 - 200107o Most robust (fatigue)o High stress in silicono Longest processo Enhanced thermal performanceo Greater density (think filled microvias)o Polymer Fillo Still robusto Reduced stress in silicono Shorter process, more expensive materialo No Fill (annular)o Least robusto Lowest stress in silicono Fastest process, lowest cost 32. Cracking of Copper TSVo Will copper in TSV experience fatigue cracking? 2004 - 200107o Classic circumferential fatigue cracking of copper plating iscurrently unlikely for two reasonso Reason #1: Hole Fillo Most TSV concepts seem to be moving to a solid plug design(fully filled)o A partial fill or plated barrellikely a process defect(pinch off due to non-optimizedleveler) 33. Example: Filled PCB Viaso Filled PCB vias (copper, solder,or conductive fill) do not failwhen subjected to temperaturecyclingo KEY EXCEPTIONo Partially filled PCB vias fail fasterdue to the presence of a stressconcentration 2004 - 200107 34. Cracking of Copper TSV (cont.)o Reason #2: Unfilled Via and Compressive Stresso Unlike in PCB, the matrix (i.e., silicon) has a lower coefficient ofthermal expansion (CTE) than the barrelo There is also a lower CTE mismatcho PCB: 50ppm vs. 17ppm (33) / TSV: 2ppm vs. 17ppm (-15)o If electroplated, stress free state should be at roomtemperatureo Any increase in temperature, due to hot spots or change in ambientconditions, will place the copperplating under an axial compressive stresso The tensile stress then arises circumferentiallyo Could induce cracking along the length ofthe via, but will not cause electrical failure 2004 - 200107 35. Cracking of Copper TSV Possible Exceptionso Lu claimed very large stresses in the copper plating for 2004 - 200107annular TSVLu, Dissertation, UTexas, 2010 36. Cracking of Copper TSV Possible Exceptionso Liu measured (XRD) similar stress levels in filled TSVLiu, ECTC, 2009 2004 - 200107Note zero stress state 37. Cracking of Copper TSV Possible Exceptions (cont.)o One publication seems to show stress-driven cracking 2004 - 200107of TSV, but little additional information is providedJ. McDonald, Thermal andStress Analysis Modeling for 3DMemory over Processor Stacks,SEMATECH Workshop onManufacturing and ReliabilityChallenges for 3D ICs us

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