DIGI REPORT

8/8/2019 DIGI REPORT

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To Whom It May Concern

This is to certify thatDeepak Bhagat and Krishna Agarwal from BIT Mesra,Ranchi havesuccessfully completed their

project on:

IMPLEMENTATION OF Digital Alarm clock

With all its functionalities during the summertraining course fromSemiconductor Technologies, Vedanttheirwork was authenticand conduct was diligent & sincere. The

project satisfies the norms of the company and was developedunder the guidance ofMs. Anupam Maurya & Mr. Amit

Chandra.

Certificate is awaited

CERTIFIED BY:

Ms. Anupam Maurya Mr.Sachin Kr. Kanodia

(Project Guide) (Center Manager)

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ACKNOWLEDGEMENT

No academic endeavor can be single handedly

accomplished. This work is no exception.

At the outset, we would like to record our gratitude to Mr.

Sachin Kr.Kanodia for initiating us into this training.

We sincerely acknowledge our thanks to our project guide

Ms. Anupam Maurya & Mr. Amit Chandra for their valuable

suggestions and time to time consultation.

Last, but not the least, we would like to thank all the staff of

VLSI Design Department, Semiconductor Laboratory (SCL),

Vedant, Lucknow especially Ms. Charu Agarwal for their kind

cooperation and assistance during our training period.

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PREFACE

The evolution of Very large scale integration (VLSI) technology hasdeveloped to the point where millions of transistors can be integrated on a

single die or chip where integrated circuits once filled the role of

subsystem component partitioned at analog-digital boundaries. They now

integrate complete systems on a chip by combining both analog-digital

functions. Complementary metal oxide semiconductors technology has

been the mainstay in mixed signal implementations because it provides

density and power savings on the digital side, and a good mix of

components for analog design.

Due in part to the regularity and granularity of digital circuit computer aided

design (CAD) methodologies have been very successful in automating the

design of digital systems given a behavioral description of the function

desired. Such is not the case for analog circuit design. Analog design still

requires a hands on design approach in general. Moreover many of the

design techniques used for discrete circuits are not applicable to the design

of analog /mixed signal VLSI circuits. It is necessary to examine closely

the design process of analog circuit and to identify those principles that will

increase design productivity and the designers chances for success.

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CONTENT Page no.

SEMICONDUCTOR TECHNOLOGIES 06

VEDANT 08

INTRODUCTION TO VLSI 10

INTRODUCTION TO VHDL 13

IEEE LIBRARIES 15

INTRODUCTION OF PROJECT 16

VHDL CODE AND RTL SCHEMATIC 18

WAVEFORM 50

BIBLIOGRAPHY 51

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SEMICONDUCTOR TECHNOLOGIES-VEDANTAN ISO 9001:2000 CERTIFIED INSTITUTION

Semiconductor Technologies has always been in sync with thefuture. It has understood and appreciated the needs of India, its

people and its ever-growing industry. Over the last six 20 yearstell the saga of VEDANT contribution in leading the national effortin the vital areas of microelectronics.

M/s Semiconductor Technologies-VEDANT is Indias premierVLSI Design & Embedded System Design organization since

2002. While VEDANTis Indias pioneer in the field of VLSI Design& Embedded System Design and Testing. VEDANT is providingEducation & Training on VLSI Design & Embedded SystemDesign through state-of-the-art lab facilities, equipped with theIndustry Standard tools. VLSI Design / Embedded SystemsDesign Engineer design such Silicon chipsmaking a career inVLSI Design / ESD is highly respected & rewarding one.Furthermore we would like to bring in your notice that VEDANT is

a member of Indian Semiconductor Association as well.Semiconductor Technologies-VEDANT (Now an ISO 9001: 2000Certified Institution) is center for the training crafted inVLSI/ESD education module followed with VLSI Design softwarealong with the FPGA programming & 8051 Microcontroller kit.

VEDANT

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VEDANT (VLSI design and training) is one of the prestigious projects

of SCL, a pioneer with vertically integrated facility in the country.

SCL VEDANT program covers the complete spectrum of VLSI design

inclusive of front end, back end and provides of exposure to the IC

fabrication process. Industry standard CAD tools are used for the

purpose of training backed up by project work under the guidance of

experts.

VEDANT (LUCKNOW CENTER) is the institute, which provides

training in VLSI design to students. The working environment is

concentrated on front-end design process. It runs two programs PG

diploma in VLSI designing of four months and certificate course of

two months. It also provides Summer & Winter Training in VLSI

Design orEmbedded System.

It has an advanced lab which is equipped with latest industry standard

Electronic Design Automation (EDA) and FPGA tools and 8051

Development Kits inclusive of

Model Sim 6.0a

Xilinx tools

FPGA Kit

8051 Development Kit

Keil SoftwareFlash Magic (Rom burning)

INTRODUCTION TO VLSI

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For any given design, if the architecture of the fixed LSI andVLSI blocks suit the application then the design time isconsiderably shortened. When a one-chip microprocessor is notquite suitable, micro programmable architectures can oftenprovide sufficient customization.

Micro programmable architectures, such as bit-slice, allow acloser control over the architecture but not total control. The basicbuilding blocks are still designed by the chip manufacturer forgeneric applications. Bit-slice architectures include interruptiblesequencers and 32-bit ALUs.

The customization of the bit-slice modules to an applicationis done through customer-designed module interconnection, theimplemented commands and their sequences. The commands orinstruction set is called the micro-program for the design.ASIC (VLSI, VHLSI)

The 1980s saw the acceptance of ASICs ( ApplicationSpecific Integrated Circuits), VLSI devices large enough to allowdesigners to implement architectures that were suited to solvingthe design problem rather than forcing one architecture to solveeverything. It was the natural extension to the bit-slicearchitectures, where some control of architecture was possiblethrough microprogramming but where the basic building blocks

were fixed designs.Not far behind the ASIC and ASIC developments,

multimedia and design integration saw a need to incorporateanalog functions into digital systems. For years the trend hadbeen away from analog design as a chosen career and now therewas a shortage of design engineers. First came massive re-training of internal staff as companies struggled to cope. Thencame the creation of Electrically Programmable Analog Circuit

(EPAC) and related devices.Application- specific solutions also includes the standard

product mix where the market for a device is so large thatproduct are developed specific to a mass application. PCIcontrollers is an example where one interface controller istargeted to handle the interface for many devices and devicetypes, the control problem tailored to the device via programming.

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The application-specific customization of the design solutionallows the designer to have the creative power of a gate-levelbreadboard design while keeping the production advantages ofVLSI.

Over the years, there has been an evolution of the universal

building blocks used by logic circuit designers. In the mid-1960s,there were SSI gates; NAND, NOR, EXOR, and NOT or INVERT.In the early 1970s, MSI blocks, registers, decoders, multiplexers,and other blocks made their appearances. In the late 1970s,ALUs (arithmetic logic units) with on-board scratchpad registers,interrupt controllers, micro program sequencers, ROMs/PROMs,and other LSI devices up to and including a complete one-chipmicroprocessor (control, ALU and registers) became readilyavailable. (And from this the PC was born.)

SSI (small scale integration) is defined here to include chipscontaining approximately 2-10 gates. MSI (medium scaleintegration) is used for chips containing 20-100 gates. LSI (largescale integration) ships contain 200-1000 gates, with the upperlimit continually extending as VLSI (very large scale integration)became a reality. In the mid-1980s, ASIC (application-specificintegrated circuits) ranged from 1000 gates to 20,000 gates(bipolar technology) or 200,000 (CMOS technology).

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INTRODUCTION TO VHDL

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Excel VHDL is a user friendly windows based package whichencapsulates the powerful Simily VHDL engine.

A typical VHDL source file contains zero or more designunits. Examples of design units are entity, architecture, package,etc. When a VHDL source file is compiled, the results ofsuccessful compilation are stored in a library .So, in effect; thedesign units contained within the VHDL source file are placed in alibrary.

A design unit that has been compiled into one library canreference other designs units in any other library through the useof clauses and library statements.

In VHDL, the current working library is always called work.When using a VHDL compiler or simulator, there is always aconcept of a current working library. If no particular library isspecified as a current working library, the current working libraryis assumed to be work. You can associate the work library withany other library.

There are two kinds of design units: Primary and Secondarydesign units. The design units of type entity, package andconfiguration are primary design units. Design units or typearchitecture and package body are secondary design units.Secondary design units are always associated with a primarydesign unit. Secondary units typically contain the implementationof their primary units.

SIMPLE RULES TO REMEMBER

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All primary units in a given library must have unique names. Note:VHDL language actually allows the entity to have the same name,as one of its configurations but VHDL Similar requires that allprimary units have unique names in a given library. All secondaryunits for a given primary unit must also be named uniquely. A

primary design and its associated design unit must both reside inthe same library.

IEEE LIBRARIES

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There is a VHDL standard library with a special name std. This library andits contents (the packages standard and textio) are built into the tools andcant be controlled. This also means that you cant have user defined librarycalled std.

The other IEEE libraries are stored I lib folder of the installation directory.

The source code is present in IEEE folder and the compiled code is presentin the IEEE.SYM folder. You may view the source code folder to see thedefinitions for use in your code.

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Introduction to DIGITAL ALARM

CLOCK

Digital Clock is a real time device used to display time in visual form .Itconsists of 6 seven segment displays. Each pair is used for second, minuteand hour respectively. There is one MOD 60 synchronous counter forseconds, one MOD 60 synchronous counter for minutes and one MOD 24synchronous counter for hour. MOD 60 counters consist of one MOD 10counter and one MOD 6 counter. MOD 24 counter consists of one MOD 10counter and one MOD 3 counter. Output of each counter is fed to sevensegment display and the outputs of all seven segment display areconverted to integers by using seven segment code to decimal converter.

When second counter completes 60 stages it sends an enable signal to theminute counter and similarly when minute counter completes its 60 stages(ie.00 to 59) it enables the hour counter. When hour counter completes 24stages (ie.00 to 23), it resets all counters to 00.

23:59:59

ALARM

The alarm is operated by comparing the output of the seven segment codeto decimal converter to the given input by the user.

If both match, the alarm blows on.

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CODE for Digital Alarm Clock

----------------------------------------------------------------------------------

-- Company: S.T.Vedant

-- Engineer: Anupam Maurya-- Create Date: 11:40:07 09/15/2009-- Module Name: port_map - Behavioral-- Project Name: Digital Alarm Clock-- Target Devices: XC2S50-- Revision 0.01 - File Created

--------------------------------------------------PORT MAP--------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity port_map isPort ( clk,rst : in STD_LOGIC;

alrm_min1,alrm_hr1 : in STD_LOGIC_VECTOR (3 downto 0);alrm_min2 : in STD_LOGIC_VECTOR (2 downto 0);

alrm_hr2 : in std_logic;alarm : out std_logic;

sec1,sec2 : out STD_LOGIC_VECTOR (6 downto 0);min1,min2 : out STD_LOGIC_VECTOR (6 downto 0);hr1,hr2 : out STD_LOGIC_VECTOR (6 downto 0));

end port_map;

architecture Behavioral of port_map is

signal a,c,e,bo,do,fo :std_logic_vector(3 downto 0);signal b,d :std_logic_vector(2 downto 0);signal f,clr,bclr,p,q,r:std_logic;

component decoder isPort ( a : in STD_LOGIC_VECTOR (3 downto 0);

q : out STD_LOGIC_VECTOR (6 downto 0));end component;

component mod_10 is

Port ( clk,rst : in STD_LOGIC;q : inout STD_LOGIC_VECTOR (3 downto 0));end component;

component mod_2 isPort ( clk,rst : in STD_LOGIC;

q : inout STD_LOGIC);end component;

component mod_6 isPort ( clk,rst : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (2 downto 0));

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end component;

component nand_5 isPort ( a1,a2,a3,a4,a5 : in STD_LOGIC;

q : out STD_LOGIC);end component;

begin

bclr


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entity decoder isPort ( a : in STD_LOGIC_VECTOR (3 downto 0);

q : out STD_LOGIC_VECTOR (6 downto 0));end decoder;

architecture Behavioral of decoder is

beginq


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-------------------------------------------------MOD-2 COUNTER---------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod_2 isPort ( clk,rst : in STD_LOGIC;

q : inout STD_LOGIC);end mod_2;

architecture Behavioral of mod_2 is

beginprocess(clk,rst)

beginif rst='1' then

q


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if rst='1' thenq


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TOP MODULE OF DIGITAL ALARM CLOCK

Internal Schematic diagram of Digital Alarm Clock

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RTL for decoder

Internal RTL of decoder

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RTL for MOD-10 COUNTER

Internal RTL of MOD-10 COUNTER

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Internal RTL ofMOD-2 COUNTER

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Internal RTL ofMOD-6 COUNTER

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RTL for NAND GATE

Internal RTL ofNAND GATE

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WAVEFORM OF DIGITAL ALARM CLOCK

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BIBLIOGRAPHY

Following is the list of books from which help has been taken for the

completion of this project.

1 VHDL-PRIMER J.Bhasker

2 VHDL PROGRAMMING Douglas L. Perry

2 MODERN DIGITAL ELECTRONICS R.P.Jain

3 DIGITAL DESIGN MorisMano

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