Digital Array Radar: MPAR Applications

IDEAS Microwave LaboratoryElectrical and Computer Engineering

Digital Array Radar: MPAR Applications

Dr. William Chappell, Caleb Fulton

Purdue UniversitySponsored by:

Collaboration with CREE Semiconductor, Lockheed Martin, and Sierra Monolithics


Overview of Presentation

• Introduction– Trends in Electrical Engineering

– What is a Digital Array Radar

• Current DAR Effort– Approach

• GaN/ SiGE two chip channels

– Results

• Weather-Specific Related Issues– Dual Polarization

• Low Cost Perspectives

Cost is a risk for the MPAR program


Trends in Electrical Engineering

To create a low cost radar it seems imperative to leverage the trends occurring at the component level.

A.) Massively Integrated RF Components, System on Chip.-SiGe and CMOS RFIC’s

B.) Widebandgap Semiconductors-GaN and SiC – III-V semiconductors

C.) Severe Impact from Digital Portion of Systems-Calibration, adaptability, and correction by feedback from the digital domain


What is a Digital Array Radar?

Analog

Digital

Ethernet Output

PA/ LNADownconverter

~D/A

A/DDigital

Backend

01011

11001

01011

10101

01011

11101

Digitization of the signal at each element. The combining of signals is done in the digital domain.

PA/ LNADownconverter

~D/A

A/D

Digital Backend


Initial Concept

DAR Program Concept V0

Traditional Multilayer Board

Antenna

GaN and SiGe


CAD Representations of Final Prototype Subarray

DAR Program Concept V1

AnalogAntenna,GaN and SiGe

DigitalADC/DAC’s, FPGA’s, Memory


DAR Program Demonstrator

Measured DAR Version I Prototype Subarray

On display outside for dual polarization.A thorough overview and demo is planned at 1 PM in 1350 NWC (Next door)


Low-Cost DAR Radar“2 Chip Radar” SolutionTraditional Hybrid

Radar ModuleAdvanced Integration

GaNSiGe

~D/A

A/D

~

~Image from Eurofighter’s radar http://www.airpower.at/news06/0922_captor-e/index.html

Remove Component Cost By Leveraging Commercial Integration Practices, remove T/R module

The 400 Watt Radiating “Laptop” Panel

High Power GaN MMIC

Massively integrated SiGe chip transceivers

Planar “laptop-like” Integration – Simple 4 Layer Board for Analog Components

Digital Backend

TraditionalElectronics


Digital Beamforming Architectures

Antenna array (N elements)

T/R modules (N elements)

M down-converters

M digitizers

M RF OSA beamformers

Can form on the order of M simultaneous beams with purely analog beamformers

Radar Signal Processor and final beamformer

RF

Baseband

Digital

Antenna array (N elements)

T/R modules (N elements)

Radar Signal Processor and final beamformer

N digitizer modules

IntermediateProcessor

IntermediateProcessor

Digitizer modules, intermediate processors, and final signal processor work together intelligently and flexibly

Overlapped Subarray (OSA) Digitization

Digital at Every Element with Hierarchical Digital Backend

Beamformingthrough digital

processing

Element Level

Calibration

Analog Beamforming


High Power Plastic Antenna Array

Composite multilayer polymer antenna

Large Area Integration 8x8 antenna only array constructed

•>35 Watts per element has been demonstrated with limited cooling on RF GaN antenna panel

•Air cooling upto 50 % duty cycle with 25 watts radiated

•Simulations show 80% efficiency at 7 Watts for GaN Amplifiers for 2.7 to 2.9 GHz

•Plastic QFN packages are therefore possible

16 element panel


GaN Results

Cost is Reduced Through Simplified Packaging• Comparison of Air Cooling Techniques

• At least 10°C cooler than without a fan

• All tested points above 22dB of Gain

• Base Plate (Solid), Input Stage (Dash) and Output Stage (Dash-Dot)

Up to 50 Watts Demonstrated in a Plastic Package

Plastic Packaging and Simple Cooling Enabled through the Efficient Modes of Operation

0

20

40

60

80

100

120

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55

Tem

pera

ture

(°C

)

PAE

(%)

Duty Cycle

Temperature and Efficiency verses Duty Cycle

56.8CFM Fan (PAE)No Fan (PAE)

No Fan, Still > 50% Efficient


¾ 2-Stage GaN MMIC¾ 2 mm output stage¾ 2.7-3.1GHz operation¾ 50 Ohm In/Out¾ Est. Chip Size = <4 mm2

¾ RF POUT = 10 Watts¾ PAE = 75%¾ Large Signal Gain = 28dB¾ Drain voltage = 28 volts¾ Est. Production Cost: ~$12/chip

10W Ultra-High Efficiency MMIC PA

Simulated MPAR MMIC Performance

Cree GaN Process capable of supporting ultra-high efficiency MPAR power amps


13

Important Solid State Trends:• Continuous increase of the frequency limits, i.e. fT and fmax (III-V’s)• Increase of output power (wide bandgap transistors)• Low-cost RF transistors for consumer mass markets (Si-based)

Solid State Trends

1960 1970 1980 1990 20001

10

100

1000

InP HBT

*

*

Transferred substratefT

fmax

AlGaAs/GaAs HEMTInP HEMT

Si BJT

AlGaAs/GaAs HEMTGaAs pHEMT

InP HEMTInP HBT

GaAs MESFET

Ge BJT

f max ,

f T , G

Hz

YearCourtesy: www.eas.asu.edu/~vasilesk/EEE532/Talk_ASU_short.ppt

CMOS

SiGe Microwave

RF Domain

Millimeter Wave

ftfmax

MPAR is easily within the range of silicon IC’s


14

mm-wave Silicon

Courtesy of Harish Krishnaswamy at USC


15

Promise of the Technology

• Recent Demonstrations – 8 element receive only array that is 2 by 3 mm in Jazz .18 micron SiGe – Works from 6 to 18 GHz (UCSD)

Multichip Module Replaced by Multireceiver Silicon IC

“motherboard-like RF array integration”

Example of 16 elements on a chip

http://www.arrowne.com/innov/in82/pics/c8i15_freescale_figure_2.jpg�


Two-Channel SiGe Transceiver

TxI

RxI

TxQ

RxQ

Σ

Σ

TR Switch

LO

ab eGaab e

GaGa

C O set ab e

· Frequency

a d dt

VariableAttenuator

VariableAttenuator

TxI

RxI

TxQ

RxQ

Σ

Σ

TR Switch

LO

· Enable· Gain· Enable

· Gain· Gain· DC Offset · Enable

· Frequency

· Bandwidth

VariableAttenuator

VariableAttenuator

DAC

DAC

DAC

DAC

• SMI boards have:– Two independent direct-conversion I/Q Tx/Rx channels per board

– 54 programmable registers

– Flexibility in gain, filtering, DC offset compensation, etc.

– Programmable RF LOs on each board

Sierra Monolithics (SMI) 2x2 WiMAX Transceiver(Eight Per Panel)

SiGe integration allows for more than 1 radar channel per chip. Beyond (SOC) System on Chip


Tracking Demonstration

Tracking demonstrated using digital beamformer


Dual Polarization Variation of DAR

The integrated SiGe transceiver is very useful for dual polarization

There are two channels on one integrated circuit, so one IC handles both inputs from the antennas.

V H

TxI

RxI

TxQ

RxQ

Σ

Σ

TR Switch

LO

· Enable· Gain· Enable

· Gain· Gain· DC Offset · Enable

· Frequency

· Bandwidth

VariableAttenuator

VariableAttenuator

DAC

DAC

DAC

DAC

TxI

RxI

TxQ

RxQ

Σ

Σ

TR Switch

LO

ab eGaab e

GaGa

C O set ab e

· Frequency

a d dt

VariableAttenuator

VariableAttenuator

DAC

DAC

DAC

DAC

V

H

Direct Data Output


DAR Dual Polarization Work

Andrew W.’s slide

VH VH

-40 dB isolation between polarizations

Measured simultaneous transmit on each polarization

Independent waveform synthesis at each antenna will allow for compensation of polarization mismatches to improve polarization metrics

0 0.5 1 1.5 2 2.5 3

x 10-5

-2

-1

0

1

2

Time, seconds

r(t)

Received LFM Pulse

Measured V and H data of LFM pulse


Conclusion

•Cost is a risk for the MPAR program

•Leveraging the advances at the component level will be useful for pushing the cost curve down

•Massive Integration - SiGe•High Power Plastic Operation – GaN•Digital Utilization – Digital at Every Element

-Let the broader electronics world do the heavy lifting

Digital at every element has been demonstrated for a 16 element panel.

A low cost phased array can be built if commercial trends and practices are leveraged.

•Cost is a risk for the MPAR program


A detailed overview of the array and a demonstration of the performance will be shown at 1 PM in room

Next door, 1 PM


DAR Version I Subarray Architecture

2) Plastic High Power PackagingMulti-layer panel and plastic packaging designed to house efficient GaN T/R modules

5) SynchronizationDigital backend Control board designed, laid out, and populated in-house

Wrote firmware for FPGAs and software for host PC interface

3) Silicon Integration Utilized integrated Sierra Monolithics 2x2 WiMAX SiGe transceiver

1) Antenna Panelization Antenna was designed, analyzed for mutual coupling, fabricated, and tested

4) Digital Processing Quadrant boards perform data conversion and element-level processing

Quadrant RFControl

Spartan3AN

FPGA

32 Mb SRAM

JTAGRS-232

PC

Clock Dist.

Transceiver

Sw. GaN

Sw. GaN

Sw. GaN

Sw. GaN

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

Spartan3A FPGA

32 Mb SRAM

Hea

der 2x2 MIMO Xcvr.

Hea

der 2x2

MIMO Xcvr.

Sw. GaN

Sw. GaN

Sw. GaN

Sw. GaN

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

Spartan3A FPGA

32 Mb SRAM

Hea

der 2x2

MIMO Xcvr.

Hea

der 2x2

MIMO Xcvr.4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

Spartan3A FPGA

32 Mb SRAM

Hea

der 2x2

MIMO Xcvr.

Hea

der 2x2

MIMO Xcvr.

Sw. GaN

Sw. GaN

Sw. GaN

Sw. GaN

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

derSpartan

3A FPGA

32 Mb SRAM

4x ADC

2x DAC

2x DAC

Xcvr

. Hea

der

Hea

der 2x2

MIMO Xcvr.

Hea

der 2x2

MIMO Xcvr.

Sw. GaN

Sw. GaN

Sw. GaN

Sw. GaN

GaNSiGeDigital CMOS

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Digital Array Radar: MPAR Applications

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