DIGITAL INTEGRATED CIRCUITS FOR COMMUNICATIONاحسان احمد عرساڻِي
Every Wednesday:15:00 hrs to 18:00 hrs
هر اربع: وڳي 6 وڳي کان 3شام تائين
My Introductionمنهنجو تعارف
Ahsan Ahmad Ursani Associate Professor Dept. of
Telecommunication Engineering
Office No: TL-117 Institute of
Communication Technologies
Email: Web page:
احسان احمد عرساڻيايسوسيئيٽ پروفيسرشعبو ڏور ربطيات :دفتر نمبرTL-117 انسٽيٽيوٽ آف
ڪميونيڪيشن ٽيڪناالجيز :برق ٽپال:ويب صفحو
[email protected]://sites.google.com/
a/faculty.muet.edu.pk/aau/home
The Teaching Planتدريسي رٿا
S. No. Chapter Hours
1 Dynamc Combinational CMOS Logic 10
2 Designing Sequential Logic 17
3 Designing Memory and Array Structures 21
Total 48
Pre-Requisite: IC Design
The Textbookنصابي ڪتاب
Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey
Chapter 6, 7, & 12
Chapter 2باب پهريون
S. No. Topic Hours1 Introduction 12 Static Latches and Registers 13 Dynamic Latches and Registers 14 Alternative Register Styles 15 Pipelining: An approach to optimize sequential 16 Speed and Power Dissipation 17 Non-Bistable Sequential Circuits 18 Perspective: Choosing a Clocking Strategy 19 110 1
Total 10
Introduction
Timing Metrics for Sequential Circuits
Set-Up time tsu Time before clock transition
Hold time thold Time After clock transition
worst-case propagation delay tc-q minimum delay (contamination delay) tcd Propagation Delay of combinational logic
tplogic Time period of the Clock signal T
Timing Metrics for Sequential Circuits
Classification of Memory Elements
Foreground Memory embedded into
logic organized as
individual registers of register banks
Background Memory Large amounts of
centralized memory core
Not the subject of this chapter
Two types of memory
Not refreshed frequently
Circuits with Positive feedback
Multivibrators
Refreshed frequently
In order of miliseconds
Store state of parasitic capacitances of MOS
Higher performance
Lower Power Dissipation
Static Dynamic
Latch Level-sensitive circuit Passes input D to the Output Q Output does not change in the HOLD
MODE Input just before the going into HOLD
phase is held stable during the following HOLD phase
An essential component of Edge-triggered Register
The +ve and the –ve Latches
A Bistable Circuit Basic Part of a memory Having two stable states Use +ve feedback
The Bistability Principle
Metastabilityloop gain is greater
than unityloop gain is much smaller than unity
Transition from one state to the other
This is generally done by applying a trigger pulse at Vi1 or Vi2
The width of the trigger pulse need be only a little larger than the total propagation delay around the circuit loop, which is twice the average propagation delay of the inverters
SR Flip Flop
SR Flip-Flop Using NAND Gates Using NOR Gates
CMOS clocked SR flip-flop Fully fully-complimentary
CMOS implementation of SR flip Flop requires 8 transistors
Clocked operation will require extra transistors
Two Crossed Coupled Inverters
4 extra transistors for R, S, and CLK inputs
CMOS clocked SR flip-flop M4, M7, and M8
forms a ratioed Inverter
Q is high and R is applied
we must succeed in bringing Q below the switching threshold of the inverter M1-M2
Must increase the size of M5, M6, M7, and M8
Example 7.1: Transistor Sizing of Clocked SR Latch
(W/L)M1= (W/L)M3= 0.5mm/0.25mm (W/L)M2 =(W/L)M4 =1.5mm/0.25mm VM = VDD/2 Q = 0 VOL (Q=0) < VM (W/L)M5-6 ≥ 2.26 (W/L)M5 = (W/L)M6 ≥ 4.5
DC output voltage vs. individual
pulldown device Transient Response
Example 7.2: Propagation Delay of Static SR Flip-Flop
Problem 7.2 Complimentary CMOS SR FF
Instead of using the modified SR FF of Figure 7.8, it is also possible to use complementary logic to implement the clocked SR FF. Derive the transistor schematic (which consists of 12 transistors). This circuit is more complex, but switches faster and consumes less switching power. Explain why.
Multiplexer-Based Latches
Multiplexer-Based Latches
The feedback loop is off while output is changing Feedback is not to
be overridden to change the output
Transistor sizing is not critical to fuctionality
Clock load is 4Advantages Disadvantages
NMOS latch using Pass Transistors
Clock load = 2 Degraded logic 1
passed to the first inverter (VDD-VTN) For smaller values of
VDD Less noise margin Less switching
performance Static Power Dissipation
Master Slave Edge-triggered Register:Positive edge-triggered
Problem 7.3: Optimization of the Master Slave Register
I1 and I2 can be removed Functionality affected ?
Timing properties of Multiplexer-based Master-Slave Register
Set-up time Hold time Propagation Delay
Propagation Delay of Inverter (tpd_inv)
Propagation Delay of Transmision Gate (tpd_tx)
tsu = 3 tpd_inv + tpd_tx tc-q = tpd_tx (T3) + tpd_inv
(I6) thold = 0
Master Slave Edge-triggered Register:Negative Edge-trggerred
Draw a circuit based on transmission gate multiplexers
Set-up time simulation in SPICE Progressively skew the input with
respect to the clock edge until the circuit fails
Set-up time simulation
Tsetup = 0.21 nsec Tsetup = 0.20 nsec
Simulation of propagation delay
Tc-q = tpd_tx (T3) + tpd_inv (I6)
Tc-q(LH) = 160 ps Tc-q(HL) = 180 ps
Reduced Clock Load Feedback
transmission gates removed
Clock load = 4 Ratioed Logic T1 should be
properly sized so as to be able to change the I1I2 state
Reverse Conduction T2 can also drive
T1 I4 must be a weak
device to prevent it from driving T2
Non Ideal Clock Signals Assumption that clock
inversion takes ZERO time Effects of Capacitive loads
dissimilar capacitive loads due to different data stored in the connecting latches
Different routing conditions of the two signals
Clock Skew
Problems due to Clock Skew Direct Path B/W D
and Q Race Condition Can conduct on +ve
edge of clock
Solution to Clock Skew: Pseudostatic2-phase D register
Two phase Clock signal
2 non-overlaping phases
Dynamic Transmission Gate Edge triggered Register
tsu= tpinv tcq= 2tpinv + tptgate Needs Refereshing Clock Overlap can
cause the problem called Race
1-1 Overlap Increasing hold time
0-0 Overlap Toverlap0-0 < tT1+ tI1+ tT2 Input Signal D must
not be able to propagate through T2 During 0-0 o overlap
C2MOS – Clocked CMOSA Clock Skew Insensitive Approach
Positive Edge Triggered Master –Slave Register
Clocked CMOS CLK=0; Master
samples the inverted version of D on X
CLK=1; Master is in the HOLD mode and Slave passes the value on X to Q
0 – 0 Overlap
0 – 0 Overlap
1 – 1 Overlap
1 – 1 Overlap
C2MOS – Clock Overlap 0 – 0 overlap does not create any
problem 1 – 1 overlap puts a HOLD constraint
Dual Edge Registers It consists of two parallel
masterslave based edge-triggered registers, whose outputs are multiplexed using the tri-state drivers
The advantage of this scheme is that a lower frequency clock (half of the original rate) is distributed for the same functional throughput, resulting in power savings in the clock distribution network
True Single-Phase Clocked Register (TSPCR)
Positive Latch Negative Latch
Embedded logic
Example 7.4 Impact of embedding logic into latches on performance
Consider embedding an AND gate into the TSPC latch, as shown in Figure 7.31b. In a 0.25
mm, the set-up time of such a circuit using minimum-size devices is 140 psec. A conventional
approach, composed of an AND gate followed by a positive latch has an effective set-up time
of 600 psec (we treat the AND plus latch as a black box that performs both functions). The
embedded logic approach hence results in significant performance improvements.
Simplified TSPC latch / Split Output
Simplified TSPC Register
Reduced Implementaiton Area
Less Power Consumption
Reduced Clock Load
All nodes do not experience full logic swing
Reduced Performance
This also limits the amount of VDD scaling possible on the latch
ADVANTAGES DISADVANTAGES
Single-phase edge-triggered register
CLK = 0 Sampling inverted D
on node X. The second inverter
is in the precharge mode
M6 charging up node Y to VDD.
3rd inverter is in HOLD, M8 and M9 are off.
Positive Edge TriggeredSingle-phase edge-triggered register
On the rising edge of the clock, the dynamic inverter M4-M6 evaluates. If X is high on the rising edge, node Y discharges.
The third inverter M7-M8 is ON during the high phase, and the node value on Y is passed to the output Q.
Positive Edge TriggeredSingle-phase edge-triggered register
On the +ve phase of the clock, X transitions to a low if D transitions to a high level.
Input must be kept stable till the value on node X before the rising edge of the clock propagates to Y. This represents the hold time of the register
hold time less than 1 inverter delay since it takes 1 delay for the input to affect X.
The propagation delay of the register is 3 inverters since the value on node X must propagate to the output Q.
Finally, the set-up time is the time for node X to be valid, which is 1 inverter delay.
TSPC Edge-Triggered RegisterTransistor Sizing
D is low & X=Q~=1; Q=0. CLK is low, Y is precharged
high turning on M7. CLK transitions from low to
high, Y and Q~ start dis-charging simultaneously (through M4-M5 & M7-M8, respectively).
Once Y is sufficiently low, the trend on Q~ is reversed and the node is pulled high anew through M9.
Effects of Glitch and Solution
fatal errors, as it may create unwanted events when the output of the latch is
used as a clock signal input to another register). It
reduces the contamination delay of the register.
The problem can be corrected by resizing the relative strengths of the pull-down paths through M4-M5 and M7-M8, so that Y discharges much faster than Q.
This is accomplished by reducing the strength of the M7-M8 pulldown path, and by speeding up the M4 -M5 pulldown path.
TSPC Edge-Triggered RegisterTransistor Sizing