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Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
SEQUENTIAL LOGIC
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Sequential Logic
FF
’s
LOGIC
tp,comb
InOut
2 storage mechanisms
• positive feedback
• charge-based
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Positive Feedback: Bi-Stability
Vi1
Vo1=Vi2
Vo2
Vi1 Vo2
Vo1
Vi2
= V
o1
Vi2
= V
o1
Vi1 = Vo2
A
C
B
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Meta-StabilityV
i2 =
Vo1
Vi1 = Vo2
C
Vi2
= V
o1
Vi1 = Vo2
B
Gain should be larger than 1 in the transition region
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
SR-Flip Flop
S
R
QS
R Q
S R Q Q
0101
0011
Q100
Q010
S
R
Q
Q
QS
R Q
S R Q Q
1010
1100
Q101
Q011
Q
Q
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
JK- Flip Flop
S
R
Q
Q Q
J
K
QJ
K Q
Jn Kn Qn+1
0
0
11
0
1
01
Qn
0
1Qn
(b)
(c)
Q
(a)
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Other Flip-Flops
QJ
KQ
T
QJ
KQ
D
Q
Q
T Q
Q
D
Toggle Flip-Flop Delay Flip-Flop
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Race Problem
Q
Q
D
1
t
t
tloop
Signal can race around during = 1
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Master-Slave Flip-Flop
S
R
Q
Q Q
QS
R
Q
Q
J
K
MASTER SLAVE
QJ
K Q
PRESET
CLEAR
SI
RI
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Propagation Delay Based Edge-Triggered
In X
N2N1
Out
In
X
Out
tpLH
= Mono-Stable Multi-Vibrator
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Edge Triggered Flip-Flop
S
R
Q
Q
Q
J
K
Q
QJ
KQ
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Flip-Flop: Timing Definitions
DATA
STABLE
DATA
STABLE
In
Out
t
t
t
tsetup thold
tpFF
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Maximum Clock Frequency
FF
’s
LOGIC
tp,comb
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
CMOS Clocked SR- FlipFlop
VDD
Q
Q
RS
M1 M3
M4M2
M6
M5 M7
M8
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Flip-Flop: Transistor Sizing
0.0 1.0 2.0 3.0 4.0 5.00.0
2.0
4.0
VQ
(1.8/1.2)
(3.6/1.2)(7.2/1.2)
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
6 Transistor CMOS SR-Flip Flop
VDD
M1 M3
M4M2
M5R
S
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Charge-Based Storage
D
D
In
(a) Schematic diagram
(b) Non-overlapping clocks
Pseudo-static Latch
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Master-Slave Flip-Flop
D
InA
B
Overlapping Clocks Can Cause
• Race Conditions
• Undefined Signals
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
2 phase non-overlapping clocks
D
In
t12
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
2-phase dynamic flip-flop
DIn
Input Sampled
Output Enable
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Flip-flop insensitive to clock overlap
DIn
VDDVDD
M1
M3
M4
M2 M6
M8
M7
M5
section section
CL1 CL2
X
C2MOS LATCH
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
C2MOS avoids Race Conditions
DIn
1
M1
M3
M2 M6
M7
M5
1
DIn
VDDVDD
M1
M4
M2 M6
M8
M5
0 0
VDDVDD
(a) (1-1) overlap (b) (0-0) overlap
X X
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
PipeliningR
EG
RE
G
R
EG
log.
RE
G
RE
G
RE
G
.
RE
G
RE
G
logOut Out
a
b
a
b
Non-pipelined version Pipelined version
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Pipelined Logic using C2MOS
InF Out
VDD
VDD
VDD
C2C1
GC3
NORA CMOS
What are the constraints on F and G?
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Example
1
VDD
VDDVDD
Number of a static inversions should be even
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
NORA CMOS Modules
VDDVDD
PDN
In1In2In3
VDD
PUN
Out
VDD
Out
VDD
PDN
In1In2In3
VDD
In4
In4
VDD
(a)-module
(b)-module
Combinational logic Latch
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Doubled C2MOS Latches
VDD
Out
VDD
Doubled n-C2MOS latch
In
VDD
Out
VDD
Doubled n-C2MOS latch
In
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
TSPC - True Single Phase Clock Logic
VDD
Out
VDD
VDD
VDD
InStatic
Logic
PUN
PDN
Including logic into
the latch
Inserting logic between
latches
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Master-Slave Flip-flops
VDD
D
VDD
VDD
D
VDD
VDD
D
VDD
D
VDD
VDD
D
VDD
D
(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop
(c) Positive edge-triggered D flip-flopusing split-output latches
XY
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Schmitt Trigger
In Out
Vin
Vout VOH
VOL
VM– VM+
•VTC with hysteresis
•Restores signal slopes
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Noise Suppression usingSchmitt Trigger
VM+
VM–
VoutVin
t tt0 t0 + tp
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
CMOS Schmitt TriggerV DD
V in Vou t
M 1
M 2
M 3
M 4
X
Moves switching thresholdof first inverter
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Schmitt TriggerSimulated VTC
0 .0 1.0 2 .0 3 .0 4 .0 5 .0Vin (V )
0 .0
1 .0
2 .0
3 .0
4 .0
5 .0
VX
(V
)
0 .0 1.0 2 .0 3 .0 4.0 5 .0V in (V )
0.0
2.0
4.0
6.0
Vou
t (V
)
V M -
V M +
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
CMOS Schmitt Trigger (2)
In
VD D
V D D
Out
M1
M2
M3
M4
M5
M6
X
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Multivibrator Circuits
Bistable Multivibrator
Monostable Multivibrator
Astable Multivibrator
flip-flop, Schmitt Trigger
one-shot
oscillator
S
R
T
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Transition-Triggered Monostable
DELAY
td
In
Outtd
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Monostable Trigger (RC-based)
VDD
InOutA B
C
R
In
B
Outt
VM
t2t1
(a) Trigger circuit.
(b) Waveforms.
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Astable Multivibrators (Oscillators)
0 1 2 N-1
0 1 2 3 4 5
t (nsec)
-1.0
1.0
3.0
5.0
V (
Vol
t)
V1V3 V5
Ring Oscillator
simulated response of 5-stage oscillator
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Voltage Controller Oscillator (VCO)
In
VDD
M3
M1
M2
M4
M5
VDD
M6
Vcontr Current starved inverter
Iref Iref
Schmitt Triggerrestores signal slopes
0.5 1.5 2.5Vcontr (V)
0.0
2
4
6
t pH
L (
nsec
)
propagation delay as a functionof control voltage
Digital Integrated Circuits © Prentice Hall 1995Sequential Logic
Relaxation Oscillator
Out2
CR
Out1
Int
I1 I2
T = 2 (log3) RC