Digital Integrated...

Adib AbrishamifarEE Department

IUST

Lecture 10 – Dynamic CMOS

Digital Integrated Circuit Design

inputsNMOS LogicCircuit

CLKP

CLKN

CLK

IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20082/71

Contents

} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary


} As mentioned before Digital MOS circuits can be classified into two categories:} Static Circuits: require no clock or other periodic signal for

operation (except sequential logic). In these circuits at every point in time (except when switching) the output is connected to either GND or Vdd via a low resistance path

} fan-in of N requires 2N devices (n N-type + n P-type)

} Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic. These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes

} requires only N + 2 transistors (n+1 N-type + 1 P-type) } takes a sequence of precharge and conditional evaluation

phases to realize logic functions

Introduction


} Why Dynamic Logic?} In the area of high speed, higher Fan-in, extremely low

power dissipation, other digital logic circuit have been considered. In this lecture, two of these alternatives to CMOS are described. The circuits are basically NMOS or CMOS Gates with slight improvements. These are:} Dynamic CMOS Logic} CMOS Domino Logic

} Each of them have specific operating advantages over NMOS or CMOS, but exhibit disadvantages in other areas

Introduction


Contents



} Dynamic Gates use a clocked PMOS pullup} Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

Static Pseudo-NMOS Dynamic

φ Precharge Evaluate

Y

Precharge

Dynamic CMOS Logic


} The Foot} What if pulldown network is ON during precharge?} Use series evaluation transistor to prevent fight

AY

φ

foot

precharge transistorY

inputs

Y

inputs

footed unfooted

f f

Dynamic CMOS Logic


Dynamic CMOS Logic

} Dynamic CMOS Logic} To make the gate dynamic, a

clock pulse is applied to the gate of complementary P and N channel devices. This gate consists of an NMOS Logic circuit whose output node is prechargedto Vdd by the PMOS, when the clock is zero. The output node is discharged by the NMOS transistor connected to ground when the clock is high


CLKP

CLKN

CLK


Precharge (Clk = 0)Evaluate (Clk = 1)

Dynamic CMOS Logic

} Dynamic CMOS Logic


} Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation

} Inputs to the gate can make at most one transition during evaluation

} Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Dynamic CMOS Logic


Dynamic CMOS Logic

} Canonical Forms


Dynamic CMOS Logic

} Properties of Dynamic Gates} Logic function is implemented by the PDN only

• should be smaller in area than static complementary CMOS} Full swing outputs (VOL = GND and VOH = VDD)} Nonratioed - sizing of the devices is not important for proper

functioning (only for performance)} Faster switching speeds

• reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort

• reduced load capacitance due to smaller fan-out (Cext)• no Isc, so all the current provided by PDN goes into discharging

CL• Ignoring the influence of precharge time on the switching speed

of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL


Dynamic CMOS Logic

} Properties of Dynamic Gates} Power dissipation should be better

• consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating

• lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)

} But power dissipation can be significantly higher due to• higher transition probabilities• extra load on CLK

} PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn

• low noise margin (NML)} Needs a precharge/evaluate clock


Dynamic CMOS Logic

} Leakage Sources} Subthreshold conduction} Transistors can’t abruptly turn

ON or OFF} Reverse-biased PN junction

diode current• Is depends on doping levels And area

and perimeter of diffusion regions, typically < 1 fA/µm2

} Gate Leakage• Carriers may tunnel thorough very thin

gate oxides• Negligible for older processes

VDD

0 0.3 0.6 0.9 1.2 1.5 1.8

J G)

A/cm

2

10-9

10-6

10-3

100

103

106

109

tox

0. 6 nm0. 8 nm

1. 0 nm1. 2 nm

1. 5 nm

1. 9 nm

VDD trend

)


} Leakage Sources} Output settles to an intermediate voltage determined by a resistive

divider of the pull-up and pull-down networks} Once the output drops below the switching threshold of the fan-out

logic gate, the output is interpreted as a low voltage

Dynamic CMOS Logic

-0.5

0.5

1.5

2.5

0 20 40

Time (ms)

Volta

ge (V

)

CLK

Out


Leakage sources

CLK

VOut

Precharge

Evaluate

Dynamic CMOS Logic

} Leakage Sources} Subthreshold leakage is dominant in modern transistors


Dynamic CMOS Logic

} Solution to Charge Leakage

CLCL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Keeper


} Charge Sharing} Charge stored originally on CY is redistributed (shared) over CX

leading to static power consumption by downstream gates and possible circuit malfunction

} When ΔVout = - Vdd (CX / (CX + CY )) the drop in Vout is large enough to be below the switching threshold of the gate it drivescausing a malfunction

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

= =+Y

x Y ddx Y

CV V VC C

Dynamic CMOS Logic


} Solution to Charge Redistribution } Add secondary precharge transistors (at the cost of

increased area and power)• Typically need to precharge every other node• Secondary precharge transistors should be small because their

diffusion capacitance slows the evaluation (increase delay)• Big load capacitance CY helps as well

B

AY

x

secondaryprechargetransistor

Dynamic CMOS Logic


} Charge Sharing Example} What is the worst case voltage drop on y? (Assume all

inputs are low during precharge and that all internal nodes are initially at 0V)

Dynamic CMOS Logic

y

CLK

CLK

A A

B B B

CC

y = A B C

Ca =15fF

Cc =15fF

Cb =15fF

Cd =10fF

Loadinverter

ab

dc

Cy =50fF

y = A B C

Cd =10fFCd =10fF

Loadinverter

cB


Dynamic CMOS Logic

} Charge Sharing Example

( ) ( )( )( )

a c a c yVout Vdd C C C C C

2.5V 30 30 50 0.94V

∆ = − + + +

= − + = −


Dynamic CMOS Logic

} Backgate Coupling} Susceptible to crosstalk due to

• High impedance of the output node • Capacitive coupling

– Out2 capacitively couples with Out1 through the gate-source and gate-drain capacitances of M4


} Capacitive coupling means Out1 drops significantly so Out2 doesn’t go all the way to ground

Dynamic CMOS Logic

} Backgate Coupling

-1

0

1

2

3

0 2 4 6

Vol

tage

Time, ns

Clk

In

Out1

Out2

Due to backgate

Due to clk feedthrough


Dynamic CMOS Logic

} Clock Feedthrough} A special case of capacitive

coupling between the clock input of the precharge transistor and the dynamic output node due to the gate to drain capacitance

} So voltage of Out can rise above Vdd. The fast rising (and falling edges) of the clock couple to Out

CLCL

Clk

Clk

B

AOut

Mp

Me


-0.5

0.5

1.5

2.5

0 0.5 1

In &Clk

Out

Time, ns

Vol

tage

Clock feedthrough

Clock feedthrough

Dynamic CMOS Logic

} Clock Feedthrough


} Other Effects} Capacitive coupling} Substrate coupling} Minority charge injection} Supply noise (Ground bounce)} Floating output nodes

Dynamic CMOS Logic


} Floating output nodes} Solutions:

• Only connect to gates• Add staticizer to refresh the charge

Dynamic CMOS Logic


} Advantages:} For n inputs, dynamic logic requires

n+2 transistors} have small area, high speed and

compact layouts} Disadvantages:

} Circuit operation is more complex due to the required clock

} The inputs can only change during the precharge phase and must be stable during the evaluate portion of the cycle

} Need Monotonicity• can not be cascaded

Dynamic CMOS Logic


CLKP

CLKN

CLK


} Monotonicity} Dynamic gates require monotonically rising inputs

during evaluation


Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A

φ

Dynamic CMOS Logic


} Monotonicity Woes} Dynamic gates produce monotonically falling outputs during

evaluation} Illegal for one dynamic gate to drive another!

Dynamic CMOS Logic


V

t

Clk

In

Out1

Out2 ∆V

VTn

Only 0 → 1 transitions allowed at inputs!

Dynamic CMOS Logic

} Cascading


} Cascading} Input going from high to low during evaluation

• a is 5V when precharge b = 5V, c = 5V• During evaluation:

– Wanted: bà 0V, cà 5V– But, b takes some time to drop to 0V– Consequently, c may fall to some unknown value

} Solution} NP-CMOS} NORA Logic} Domino logic

Dynamic CMOS Logic

a

cb


Dynamic CMOS Logic

} NP-CMOS} Only 0 → 1 transitions allowed at inputs of PDN } Only 1 → 0 transitions allowed at inputs of PUN

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 11 0

0 00 1


Dynamic CMOS Logic

} NORA Logic} WARNING: Very sensitive to noise!

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 11 0

0 00 1

to otherPDN’s

to otherPUN’s


} An example

Dynamic CMOS Logic

A

Y=AB+C

BC


In1

In2In3

In4

Out

VDD

GNDφ

Dynamic CMOS Logic

} Dynamic 4 Input NAND Gate


In1

In2 PDNIn3

Me

Mp

CLK

CLK

Out

CLCL

} Power Consumption} Power only dissipated when previous Out = 0

Dynamic CMOS Logic


011

001

010

100

OutBA

} Power Consumption} Dynamic Power Consumption is Data Dependent

• Assume signal probabilities (Dynamic 2-input NOR Gate)• PA=1 = 1/2• PB=1 = 1/2• Then transition probability• P1→0 = Pout=0 = ¾

} Switching activity can be higher in dynamic gates!

Dynamic CMOS Logic


} Rules of Thumb} Dynamic logic is best for wide OR/NOR structure (e.g. bit-

lines), providing 50% delay improvement over static CMOS} Dynamic logic consumes 2x power due to its phase activity

(unconditional pre-charging), not counting clock power

Dynamic CMOS Logic


} Notes} No need to implement the complement of the function,

leading to smaller area} We can avoid the long PMOS chains} Handle the charge sharing problem and floating output

nodes} Input transistors should not change from on to off

during evaluation

Dynamic CMOS Logic


Contents



CMOS Domino Logic

} It is an extension of dynamic CMOS gates that allow cascading of stages

} The simple modification entails incorporating a static CMOS inverter at the output of each logic gate

A

W

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter


} Stage A should be precharged in Φ1 and evaluate inΦ2

} Stage B should be precharged in Φ2 and evaluate in Φ1

CMOS Domino Logic


} During precharge (clk=0), the output node of the dynamic gate is precharged high and the output node of the CMOS inverter is low. Then subsequent stages will be turned off during the precharge phase

} When the clk=1, the output of the driving gate will conditionally discharge, allowing the output of the inverter to conditionally go high. Each connected gate output can then make a transition from low-to-high, in sequence

} There is no restriction on the number of logic stages that can be cascaded provided that all stages can evaluate during one clock pulse

CMOS Domino Logic


n- network

ev

V

1

W

pc

2

X Y

} pc = Φ1 and ev = Φ2

CMOS Domino Logic

cycle

1

2

precharge evaluate

input latchedhere

output latchedhere

pc = 1 ev = 2


} Won’t work! If pc = Φ2 and ev = Φ1

CMOS Domino Logic


CMOS Domino Logic

} Why Domino?} Like falling dominos!


} Produces monotonic outputs


W

Precharge

X

Y

Z

A

φ

B C

φ φ φ

C

AB

W X Y Z =X

ZH H

AW

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter

CMOS Domino Logic


} Domino Optimizations} Each domino gate triggers next one, like a string of dominos toppling

over} Gates evaluate sequentially but precharge in parallel Thus evaluation

is more critical than precharge} HI-skewed static stages can perform logic} Static inverter can be optimized to match fan-out

S0

D0

S1

D1

S2

D2

S3

D3

φ

S4

D4

S5

D5

S6

D6

S7

D7

φ

YH

CMOS Domino Logic


} Leakage} Dynamic node floats high during evaluation

• Transistors are leaky (IOFF ≠ 0)• Dynamic value will leak away over time• Formerly miliseconds, now nanoseconds!

} Use keeper to hold dynamic node• Must be weak enough not to fight evaluation

A

φH

2

2

1 kX Y

weak keeper

CMOS Domino Logic


} Noise Sensitivity} Dynamic gates are very sensitive to noise

• Inputs: VIH ≈ Vtn• Outputs: floating output susceptible noise

} Noise sources• Capacitive crosstalk• Charge sharing• Power supply noise• Feedthrough noise• And … !

CMOS Domino Logic


CMOS Domino Logic

} Designing with Domino Logic} If all the inputs come from other domino gates, then all the inputs will be low

during the precharge. You don’t need to explicit evaluate transistor} Need to be a little careful. When precharge begins, the first gate’s output must

precharge before the next gate can precharge. Both evaluate and prechargeripple in this scheme. But, if there is already a tall stack, transistor ratioing will let precharge win anyway. (but you waste power until the precharge ripples)


VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

CMOS Domino Logic

} Footless Domino} The first gate in the chain needs a foot switch

Precharge is rippling – short – circuit current} A solution is to delay the clock for each stage


} Example} During precharge, x, y, z = 1, x, y = 0} During evaluation, x = 0 when a = b = 1} Therefore, z = a b c d

CMOS Domino Logic

a

b

x

c

xy

d

y z


} Advantages:} Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS

requires 2n)} Single clock can be used to precharge and evaluate all stages at the

same time} It is attractive for high-speed circuits} 1.5 – 2x faster than static CMOS} Widely used in high-performance microprocessors

} Disadvantages:} Each logic block must incorporate a separate inverter} Each block performs only non-inverting logic} Monotonicity} Leakage} Charge sharing} Noise

CMOS Domino Logic


} Dual Rail Domino} Domino only performs noninverting

functions• AND, OR but not NAND, NOR, or XOR

} Dual-rail domino solves this problem• Takes true and complementary inputs • Produces true and complementary

outputs

invalid11‘1’01‘0’10

Precharged00Meaningsig_lsig_h

Y_h

f

φ

φ

inputs

Y_l

f

CMOS Domino Logic


} Example AND/NAND} Given A_h, A_l, B_h, B_l} Compute Y_h = A * B, Y_l = ~(A * B)

} Pulldown networks are conduction complements

CMOS Domino Logic

Y_hφ

φ

Y_lA_h

B_hB_lA_l

= A*B= A*B


} Example XOR/XNOR} Sometimes possible to share transistors

Y_hφ

φ

Y_lA_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B

CMOS Domino Logic


} Rules of Thumb} Typical domino keepers have W/L = 5-20% of effective width

of evaluate tree} Typical domino output buffers have a beta ratio of ~ 6:1 to

push the switch point higher for fast rise-time

CMOS Domino Logic


Contents



} We noted that dynamic inputs never make 1 to 0 transitions while in evaluation

} Two solutions:} Precharge outputs low using an inverting gate

(standard domino)} Delay the evaluate clock until inputs settle (CD

domino)

CD Domino Logic


} Self-timed dynamic logic family} Consists of a dynamic gate, and an optional

delay element for the clock signal

CD Domino Logic

OR2

clk(i) clk(i+1)delay

Out = a+bMpre

Meval

a b

OR2

clk(i) clk(i+1)delay

Out = a+bMpre

Meval

a b


} Advantages} Uses single-rail circuits, rather than dual-rail for

standard domino} Provides both inverting and non-inverting functions} High-speed, large fan-in NOR and OR circuits

CD Domino Logic


CD Domino Logic

} Delay Matching} CD domino requires delay matching between the

slowest dynamic gate at a level and a delay element} A 20% margin is typically added to the delay of the

fixed delay element to account for PVT variations} Thus, 20% of the speed gain possible with CD domino

is not realized} Average speed gain of (60+20)% is theoretically

possible} Use digitally programmable delay elements

(PDEs) to reduce the margin and attain a speed improvement without affecting the reliability in the presence of variations


} Clocking Scheme} The circuits are fully levelized} The delay element on each level is tuned to the

slowest gate at its level, plus a 20% margin

CD Domino Logic


Contents



} Positive feedback does not exist

Dynamic CVSL

{In }InC

F F

C NMOSLogic Array


Contents



} It is one type of Dynamic CVSL with positive feedback} By this logic the low level output is guaranteed to zero in

evaluation phase

Sample-Set Differential Logic (SSDL)

{In }In

C

F F

C

NMOSLogic Array


Contents



Summary

} This lecture describes many basics CMOS Logic Gates which require clock or other periodic signal for operation

} These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes

Date post:	05-Aug-2020
Category:	Documents
Upload:	others
View:	0 times
Download:	0 times

Digital Integrated...

Documents