Digital Labmanual i

8/2/2019 Digital Labmanual i

1/58

Digital electronics Lab Page 1

INDEX

Exp.

No:

Date Name of Experiment Page no: Facultys

signature

1 Study of logic gates using discrete

components

2 Adders and Subtractors

3 Combinational logic design using 74XX ICs

4 Binary to gray and gray to binary conversion

5 Pulse detector circuit

6 Estimate the propagation delay in logic gates

7 Flip-flop

8 Adder/ Subtractor circuit using 7483

9 Design and implementation of BCD adder

10 Design and implementation of 2bit magnitudecomparator

11 Design and implementation of multiplexerand demultiplexer

12 Design and implementation of shift register

13 Construction and verification of

Asynchronous counter

14 Design and implementation of Synchronous

counter, Ring counter and Johnson counter

15 Digital Clock


2/58


Exp no: 1 Date:

STUDY OF LOGIC GATES

Aim: To construct the basic and universal gates using discrete components and verify the truth

table

Components required: Transistor, resistors, diodes, LED

Theory:

1.OR-GATE

OR gate has two or more inputs and a single output and it operates in accordance with the following

definitions .The output of an OR Gate is high if one or more inputs are high .When all the inputs are

low then the output is low..If two or more inputs are high state then the diodes connected to these

inputs conduct and all other diodes remain reverse biased so the output will be high and OR functionis satisfied.

2. AND GATE

AND gate has two or more inputs and a single output and it operates in accordance with the

following defenitions.The output of an AND gate is high if all inputs are high. If Vr is chosen i.e.

more positive than Vcd then all diodes will be conducting upon a coincidence and the output will be

clamped at 1.If Vr is equal to Vcd then all diodes are cut off and output will raise to the voltage Vrif

not all input have the same high value then the output of AND gate is equal to Vi (min0)

3. NOT-GATE.

The NOT gate circuit has a single output and a single input and perform the operation of negation in

accordance with definition ,the output of NOT Gate is high if the input is low and the output is low or

zero if the input is high or 1

4. NOR GATE

A negation following on OR is called NOT-OR Gate. As shown in figure if V0 is applied as input

signal to the diodes then both diodes are forward biased. Hence no voltage is applied to emitter base

junction and total current is passed through the LED and it glows which indicates high or one state

5. NAND GATE

The NAND Gate can be implemented by placing a transistor NOT gate after the AND gate circuit

with diodes. These gates are called diode transistor logic gates. If V0 is applied to input of the diode

then the diode D1&D2 will be forward biased. Hence no voltage applied across base emitter junction


3/58


and this junction goes into cut off region .Hence total current from source Vce will flow through LED

and it flows which indicate the one state or high state.

Circuit diagrams:

OR GATE:

AND GATE:

NOT GATE:


4/58


NAND GATE:

NOR GATE:


5/58


Truth Tables:

AND GATE: OR GATE:

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

NOR GATE: NAND GATE:

NOT GATE:

A A

0 1

1 0

Procedure:

1. Connect the circuit as per diagram2. Apply 5V from RPS for logic 1 and 0v for logic 03. Measure the output voltage using digital multimeter and verify the truth table4. Repeat the same for all circuits

A B Y=AB

0 0 0

0 1 0

1 0 0

1 1 1

A B Y=(A+B)

0 0 1

0 1 0

1 0 0

1 1 0

A B Y=(AB)

0 0 1

0 1 0

1 0 0

1 1 0


6/58


Answer the following questions:

1. What are the universal gates? Why are they called universal gates?2. What is the other name of EX-NOR gate?

Observations and Conclusions:


7/58


Exp No: 2 Date: ..

HALF/FULL ADDER & HALF/FULL SUBTRACTOR

Aim: To realize Half/full adder and half/full Subtractor. Using X-OR and Basic gates

Components required: IC7404, IC7408, IC7486, IC7432

Circuit Diagram:


8/58


Truth Table:


9/58


Truth Table:

Procedure:

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on Vcc and apply various combinations of input according to the truth table.

4. Note down the output readings for half/full adder and half/full Subtractor, sum/difference and

the carry/borrow bit for different combinations of inputs.

Observation and Conclusions:


10/58


Exp no: 3 Date:

COMBINATIONAL LOGIC DESIGN USING 74xx ICs

Aim: A Warning buzzer is to sound when the following conditions apply:

a. Switches A, B, C are on.b. Switches A and B are on but switch C is off.c. Switches A and C are on but switch B is off.d. Switches C and B are on but switch A is off.

Draw a truth table for this situation and obtain a Boolean expression for it.

Minimize this expression and draw a logic diagram using only a) NAND b) NOR gates.

Components Required: .

Truth table:

A B C O/P


11/58


Logic diagram:


12/58


Procedure: -



3. Switch on Vcc and apply various combinations of input according to truth table.

4. Note down the output readings for the required combinations of inputs.

Observations and conclusion:


13/58


Exp No: 4 Date:

BINARY TO GRAY AND GRAY TO BINARY CONVERSION

Aim: - To convert given binary numbers to gray codes and gray to binary numbers.

Components required:.

Truth table:

Binary to Gray : Gray to binary:

G2 G2 G0 B2 B1 B0B2 B1 B0 G2 G1 G0


14/58


Circuit Diagram:


15/58


Procedure:

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.

3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at

respective pins and outputs G0, G1, G2, G3 are taken for all the 16 combinations of

the input.

4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at

respective pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations

of inputs.

5. The values of the outputs are tabulated.

Observations and Conclusion:


16/58


Exp No: 5 Date:

PULSE DETECTOR CIRCUIT

Aim: To study the Pulse detector circuit

Components required: CD4001 (CMOS NOR gate)

Theory:

The single NOR gate and three inverter gates create this effect by exploiting the propagation delay

time of multiple, cascaded gates. In this experiment, use three NOR gates with paralleled inputs to

create three inverters, thus using all four NOR gates of a 4001 IC.

Normally, when using a NOR gate as an inverter, one input would be grounded while the other act as

the inverter input, to minimize the capacitance and increase the speed. This particular pulse detector

circuit produces a high output pulse at every falling edge of the clock (input) signal

Circuit diagram:


17/58


Pin out of CMOS IC:

Procedure:

Construct the circuit as given, connect 1MHz clock as input. Observe the input and output waveforms

on the C.R.O.

Observation and Conclusion:


18/58


Exp. No- 6 Date:

ESTIMATE THE PROPAGATION DELAY IN LOGIC GATES

Aim: To estimate the propagation delay of TTL inverter and CMOS inverter

Components required: TTL -74LS04, CMOS-CD4049

Circuit Diagram:

Procedure:

1. Verify the gates2. The VCC and GND should connect to the concerned pins.3. Observe the LED output and measure both the input and output voltages using a digital

multimeter with the data switch on both positions.

I/p (LOW)= -----------------V

O/P(HIGH)= ------------------V

I/P (HIGH) = -------------------V

O/P (LOW) = -------------------V

4. Six gates are connected serially and observe the o/p voltages of each o/p and i/p


19/58


5. Input is connected to 1MHz digital clock and display the input of first gate on oscilloscopeand the output of the sixth inverter on oscilloscope .The output waveform is delayed by the

sum of the propagation delays through the six inverters .Use the oscilloscope techniques to

measure the time difference between rising/falling edges on the output of last inverter.

Sketch the input and output waveforms (label TPHL,TPLH propagation delays on sketch)

Formulas:

Propagation delay , tpxx =

M= Multiplier used on the oscilloscope (will usually be 1 or 0)

G=number of logic gates used.

Frequency= 1/period

Propagation delay:

Propagation delay from a change on an input to a change on the output.TPHL

is the propagation delay for an input change causing a HIGH to LOW change on the output(this does

NOT REFER to input change).TPLH is the propagation delay for an input change causing a LOW to

HIGH change on the output.The figure below define TPHL,TPLH for inverting and non- inverting

gates.


20/58



21/58


Observations and conclusion:


22/58


Exp No: 7 Date: .

FLIP-FLOP

Aim: Truth table verification of Flip-Flops: (i) RS-Type (ii) D- Type (iii) T- Type.

(iv) JK-Type

Components Required:

Circuit Diagram& Truth table:

i) RS Flip-Flop:

ii) D Flip Flop:

Qn Qn R S Qn+1 Qn+1

0 1 0 0

1 0 0 0

0 1 0 1

1 0 0 1

0 1 1 0

1 0 1 0

0 1 1 1

1 0 1 1


23/58


iii) T Flip-flop:

iv) M/S JK flip flop:


24/58


Procedure:

1. Connections are made as per circuit diagram.

2. Verify the truth table for various combinations of inputs.

Observations and conclusions:


25/58


Exp No: 8 Date: .

ADDER/SUBTRACTOR CIRCUITS USING 7483

Aim: To design and set up the following circuits using 4 bit binary adder IC 7483

i) 4 bit binary adderii) 4 bit add/subtract circuit

Components required: IC 7486, IC 7483, IC 7400.

Theory:

The 7483 is a TTL IC with four full adders in it. This means it can add nibbles. To add bytes, we

need to use two 7483 ICs.

4 bit binary adderA3A2A1A0 and B3B2B1B0 are inputs and Cout S3S2S1S0 is the output. CARRY IN

pin is ground. This circuit is also called a nibble adder.

4 bit add/subtract circuitThe circuit set up is shown in figure. To add the nibbles, SUB is to be

made 0. To subtract B3B2B1B0 from A3A2A1A0, SUB is to be made 1. EXOR gates function as

controlled inverters. When SUB = 1, B3B2B1B0 is complemented. Now A3A2A1A0, complemented

version of B3B2B1B0 , and 1 at Cin pin are added together. Coutis ignored. Thus the 2s complement

of subtrahend is added with minuend. If minuend is less than subtrahend, the obtained output will be

the 2s complement of difference. For example

Procedure:

1. Test all components and IC package using digital IC testers.

2. Set up the nibble adder and try a few nibbles addition. Verify the working of the

circuit.

3. Set up the add/ subtrator circuit. Verify the working of the circuit.


26/58


Circuit Diagram:

4 bit binary adder:

4 bit add/subtract circuit:


27/58


Observations and conclusions:


28/58


Exp No: 9 Date: ..

DESIGN AND IMPLEMENTATION OF BCD ADDER

Aim: To design and implement BCD adder using 4 bit binary adder IC 7483.

Components required: .

Theory:

BCD Addition:

Binary Coded Decimal is a method of using binary digits to represent the decimal digits 0 through 9.

The valid BCD numbers are (0000 to 1001)BCD. Each digit of the decimal number will be

represented by its four bit binary equivalent. Ex: (127)10 - BCD equivalent (0001 0010 0111)2.

In BCD addition the following three cases are observed,

1. The resulting BCD number equal to less than (1001)BCD.

2. The resulting BCD number greater than (1001)BCD.

3. Carry is generated in the BCD addition.

For case 2 and 3, the result is added with correction factor (0110)BCD so that the result is in valid

BCD number.

BCD ADDER:

The two BCD inputs to be added are applied at inputs A and B of the first binary adder IC 7483.

The sum output of the first binary adder is given to the B input of the second binary adder. The A

input of the binary adder is given (0110)BCD when a carry is generated from the first adder or when

sum from the first binary adder is greater than (0110)BCD, else A input is (0000)BCD. The following

Boolean expression is used to find whether (0110)BCD or (0000)BCD needs to be applied to the A

input,

Cout = Cout1 + S4 (S3 + S2)

Where S4, S3, S2, S1 are the sum of the BCD from the first binary adder with S4 as the MSB and S1

as the LSB. Cout1 is the carry output from the first binary adder.


29/58


Procedure:



3. Apply and verify the various combination of input according to the truth table for BCD adder.

Circuit diagram:


30/58




31/58


Exp No: 10 Date: ..

DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR

Aim: To design and implement of 2 bit Magnitude Comparator for the Condition

A = B

A > B

A < B

Draw a truth table for this situation and obtain a Boolean expression for it. Minimize this expression

and draw a logic diagram.

Components Required:IC7408, IC7432, IC7404, IC748

Theory: The comparison of two numbers is an operation that determines one number is greater than,

less than (or) equal to the other number. A magnitude comparator is a combinational circuit that

compares two numbers A and B to determine their relative magnitude. The outcome of the

comparator is specified by three binary variables that indicate whether A>B, A=B (or) A


32/58


Logic Diagram:


33/58


Observations & Conclusions:


34/58


Exp No: 11 Date:..

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

Aim: To design and implement multiplexer and demultiplexer using logic gates and IC

Components Required: -74LS04, 74LS11, 74LS32, 74LS151,74LS154

Function Table:

Circuit diagram for multiplexer:

S1 S0 Input Y


35/58


Use 74LS151 to implement the logic function F=A B C


36/58


Truth table

Truth table:

Logic Diagram:

S0 S1 Output


37/58


Observations conclusions:


38/58


Exp No: 12 Date:

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

Aim: -To construct and verify the truth table of a shift register using D- Flip-flop.

Components Required: IC7474, IC7404, IC7432, IC7408

Theory:

A binary FLIP-FLOP is a one bit memory storage cell . n FLIP-FLOP can store n bits.

This series of FLIP-FLOP are called Registers. Registers in which data is entered or / and taken out in

serial form are referred to as shift registers , since bits are shifted in the FLIP-FLOP with the

occurrence of clock pulses either in the right (right shift register) as well as in the left direction (leftshift register)

There are four types of shift registers.

a) Serial in serial out (SISO)

b) Serial in parallel out (SIPO)

c) Parallel in serial out (PISO)

d) Parallel in parallel out (PIPO)


39/58


Circuit diagram:

SHIFT REGISTER (SIPO):


40/58


SHIFT REGISTER (PIPO):


41/58


SHIFT REGISTER (SISO):

When the Input is 1, after the 4th

clock pulse, A gives the output as 1

When the Input is 0, after the 4th

clock pulse, A gives output as 0


42/58


SHIFT REGISTER (PISO):


43/58


Procedure :

1. Verify the flip flop.2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to truth

table.4. By applying the clock pulse, all input combinations are given and the

outputs are verified with the truth table

Questions:

1. What is a register?2. What is a shift register?3. What is a parallelin,parallel-out ,shift register?4. What is a universal shift register?5. What are the applications of shift registers?Observations & Conclusions


44/58


Exp No: 13 Date

CONSTRUCTION AND VERIFICATION OF 4 BIT ASYNCHRONOUS COUNTERS AND

MOD10/MOD12 ASYNCHRONOUS COUNTER

Aim: To construct and verify the 4bit ripple counter, mod10/mod12 Asynchronous counter

Components required: IC7476

Theory: A counter is a register capable of counting number of clock pulse arriving at its clock input.

Counter represents the number of clock pulse arrived. A specified sequence of state appears as

counter output. This is the main difference between a register and a counter. There are two types of

counter, synchronous and asynchronous. In synchronous common clock is given to all flip flops and

in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is

clocked by Q or Q output of previous stage. Because of inherent propagation delay time all flipflops are not activated at same time which resultsin asynchronous operation.

Pin details of IC 7476:


45/58


Logic diagram for 4bit ripple counter:

Truth table:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 07 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1


46/58


Logic diagram for Mod 10 counter:

Truth table:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 06 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0


47/58


3bit up/down counter:

State diagram:

When M=1


48/58


When M=0

Truth table:

Questions:

1. How many flipflops are required to build an asynchronous counter to count 0 to 19?2. Draw a mod -3 asynchronous counter?3. How many flipflops are needed to count mod-128 binary counter?


M Q2 Q1 Q0

1

1

1

11

1

1

1

M Q2 Q1 Q0

0

0

0

00

0

0

0


49/58


Exp No-14 Date.

DESIGN AND IMPLEMENTATION OF 4BIT SYNCHRONOUS COUNTER, RING

COUNTER AND JOHNSON COUNTER

Aim: To design and implement 4bit synchronous counter, ring counter and Johnson counter

Components required: IC7473, 7408, 7476

Theory: Synchronous and asynchronous counters provide same outputs. The difference is that in the

synchronous counters all flip flops work in synchronism with the input clock pulse. That means, the

output of all the flip flops in the counter change state at the same instant. Therefore,the propagation

delay occurring in asynchronous counter is eliminated in synchronous counters .Synchronous

counters for any given count sequence or modulus can be designed and setup by the following

procedure.

1. Find the number of flip flpos the relation M=2NwhereM is the modulus of the counter and Nis minimum number of flip flops required, N=log2M

2. Write down the count sequence (FF outputs) in a tabular form.3. Determine the flip flops inputs which must be present for the desired next state using

excitation table of flip flops

4. Prepare Karnaugh maps for each FF input in terms of FF outputs as the inputvariables.Obtain the minimized expressions from K-maps

5. Set up the circuit using FFs and other gatesExcitation table of JK F/F:

Q Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0


50/58



51/58


2) Design and implement mod 7 synchronous counter:


52/58



53/58


Ring counter and Johnson counter:

Theory: Ring counter and Johnson counter are basically shift registers

Ring counter: It is constructed using JK flip flop by connecting Q and Q outputs from one flipflop to

the J and K inputs of the next flipflop.The output of the final flipflop are connected to the input of

the first flipflop.To start the counter , first flipflop is set using preset facility and the remaining

flipflops are reset using reset input .When clock signal arrives,this set condition continues to shiftaround the ring.

Ring counter using Dflipflops are made by connecting the Q output of last

flip flop to the D input of the first flipflop.As it can be seen from the truth table ,there are four

unique output states for this counter ,rendering a mod-4 ring counter.Ring counter is called divide by

N counter where N is the number of flipflops.

Johnson counter: The modulo number of ring counter can be doubled by making a small change in

the ring counter circuit .The Q and Q output of the last flipflop are connected to the J and K input of

the first flipflop respectively.This is the Johnson counter.

Intially all the flipflops are reset.After the first clockpulse FF0 is set and

remaining FF are reset .After fourth clock pulse all flipflops are set.After fifth clockpulse FF0 is reset

and the remaining flipflops are set.After the eighth clock pulse all flipflops are reset .There are eight

different output conditions creating a mod-8 johnson counter.Johnson counter is also called twisted

ring counter or divide by 2N counter.

Procedure:

1.Set up the ring counter and set any Q ouput using PRESET and apply monopulses using switch in

the trainer kit to the clk input2. Note down the states of the ring counter output s on the truth table for successive clocks

3.Repeat the steps 1 and 2 for the Johnson co

unter


54/58


Truth table and Timig diagram:


55/58


Johnson counter:

Truth table and waveforms:


56/58


Observations &Conclusions:


57/58


Exp No: 15 Date:

DIGITAL CLOCK

Aim: Design a digital clock circuit and verify the output

Components required: IC7490

Theory: A block diagram showing the functions to be performed is given below, the first divide by

60-counter changes state once each second and has 60 discrete states. It can there fore, be decoded to

provide signals to display seconds. This counter is referred to as the seconds counter. The second

divide by 60 counter changes state once each minute and has 60 discrete states .It can thus be

decoded to provide the necessary signals to display minutes. This counter is then the minutes counter

.The last counter changes state once each 60 minutes(one each hour).Thus if it is divide by 12

counter, it will have 12 states that can be decoded to provide signals to display the correct hour. This,

then, is the hours counter.

Circuit diagram:

Seconds counter


58/58

Draw the circuits of minutes counter, hours counter

Observations & conclusions:

Date post:	05-Apr-2018
Category:	Documents
Upload:	venkata-rajendra-sadhu
View:	217 times
Download:	0 times

Digital Labmanual i

Documents