LOGIC DESIGN MCQ [Publish Date] 1) BCD stands for_____________________ a. Binary Coded Decimal b. Binary Coding decode c. Binary code discuss d. Binary code domain 2) All fractional decimal number is split into ____________ a. Two Parts b. Single Parts c. Three Parts d. All the Above 3) The transistor can represent the value ___________ by off state and the value ________ by on state a. 0 and 1 b. 1 and 0 c. 2 and 1 d. 3 and 1 4) The base of Octal number system is ______________ different ways a. 8 b. 7 c. 6 d. 5 5) The base of Hexadecimal number system is ___________ means different ways. a. 16 b. 15 c. 14 d. 11 6) How to represent the Hexadecimal value “1A3F” in decimal format. a. 671910 b. 789610 c. 9635 10 d. 45632 10 7) Match The Following Table 1) 4 bits a) Word 2) 8 bits b) Half Word 3) 16 bits c) Byte
2) All fractional decimal number is split into ____________a. Two Partsb. Single Partsc. Three Partsd. All the Above
3) The transistor can represent the value ___________ by off state and the value ________ by on statea. 0 and 1b. 1 and 0c. 2 and 1d. 3 and 1
4) The base of Octal number system is ______________ different waysa. 8 b. 7c. 6d. 5
5) The base of Hexadecimal number system is ___________ means different ways.a. 16b. 15c. 14d. 11
6) How to represent the Hexadecimal value “1A3F” in decimal format.a. 671910
b. 789610
c. 963510
d. 4563210
7) Match The Following Table
1) 4 bits a) Word2) 8 bits b) Half Word3) 16 bits c) Byte4) 32 bit d) Nibble
a. D , c , b , cb. A , b , c , dc. C , b, d , ad. B , c , a , d
LOGIC DESIGN MCQ [Publish Date]
8) The MSB Stand For ____________________a. Most Significant Bitb. Most Signified Bitc. Most Sign Bitd. Most Signal Bit
9) The LSB Stands For __________________________a. Least Significant Bitb. Least Sign Bitc. Least Signal Bitd. Least Sign Broad
10) The MSB “0” represent the _____________ valuea. Positive Valueb. Negative Valuec. Single Valued. Double Value
11) The _____________ complement is slightly different from the signed magnitude numbera. 1’s Complementb. 2’s Complementc. 3’s Complementd. 4’s Complement
12) The _____________ Complement is asymmetric system with additional bit is requireda. 2’s Complementb. 1’s Complementc. 3’s Complementd. 4’s Complement
13) convert 100.26510 into binarya. 1100100.0100b. 11111.00000c. 101010.0001d. 111101.0000
14) Convert 1A2C16 into Binary Valuea. 0001 1010 0010 11002
16) The signed magnitude representation is one of the methods to represent the________ and _______ number in binary system
a. Negative And Positiveb. Positive And Negativec. Negative And Signd. All The Above
17) All binary bits are complemented and resented along with the ___________ bita. Sign Bitb. Complement Bitc. Positive Bitd. Negative Bit
18) This is a powerful yet simple technique which minimizes the hardware implementation of signed arithmetic operations in a __________ machine.
a. Digital Machineb. Analog Machinec. Client Machined. Server Machine
19) The 2N–1 is often referred to as the ____________ for computing the excess representation of the numbera. Magic Numberb. Simple Numberc. Dynamic Numberd. Static Number
20) Rules for determining significance (integers):
1. A nonzero digit is always significant2. The digit '0' is significant if it lies between other significant digits3. The digit '0' is never significant if it precedes all the nonzero digits
a. 1 and 2 b. 1 and 3 c. 2 and 3d. 1 2 3
21) The range of values represented by an 8-bit binary number is _____.a. 0 to 255.b. 0 to 155c. 0 to 156d. 0 to 256
22) The result of 7 – 2 using 1’s complement notation isa. (144)8
b. (154)8
LOGIC DESIGN MCQ [Publish Date]
c. (169)8
d. (123)8
23) The bit pattern 1011 in 1’s complement notation isa. (0.0100)2
b. (154)8
c. (169)8
d. (123)8
24) The bit pattern 1110 in 2’s complement notation isa. 0100b. 1100c. 1111d. 10101
25) The significant digits of 0012340 are _______.a. 0101b. 1101c. 1110d. 1010
26) The bit pattern 1101 Excess Number converted value is ________.a. – 2b. -1c. -3d. -4
27) The digit _________ is never significant if it precedes all the nonzero digitsa. 0b. 1c. 2d. 3
28) Decimal means base __________.a. 10b. 8c. 2d. 16
29) The decimal value of the bit pattern 11111111 is _________.a. 255b. 263c. 155d. 235
30) This concept becomes important when we address the IEEE Single Precision __________ standarda. Floating-Point standard.b. Binary Number Standard
LOGIC DESIGN MCQ [Publish Date]
c. Decimal Number Standardd. Hexa Decimal standard
Unit -231) Any basic ____________ units can be used to construct the digital circuits
a. 2 Statesb. 1 Statesc. 3 Statesd. 4 States
32) The Boolean sum operator is represented by “+” _________a. ORb. ANDc. EX-ORd. EX- NOR
33) The Boolean product operator is represented by “•” or _________a. ANDb. ORc. Ex-ORd. EX-NOR
70) (X’+Y’) • (X’ + Y) =_____________ a. Y’b. Yc. X’d. X
71) X + X’ = _______________a. 1b. 0c. Ad. A’
72) What Is The name of This gates
a. Nandb. Andc. Ord. Ex-or
73) The functional completeness of the _____________ gate has be taken as advantage while constructing logic circuits in digital systems
a. Nandb. Andc. Ord. Ex- or
74) _________________ gate followed by an inverter can be used to implement OR gatea. NORb. ORc. NANDd. NOT
75) NOR is a ___________ complete operationa. Functionallyb. Logically
LOGIC DESIGN MCQ [Publish Date]
c. Dynamicallyd. Broadly
If76) either one of the input is HIGH, then the output will be _________ Ex Or Gates
a. Lowb. Highc. Middled. All the above
77) The XNOR gate is a digital logic gate whose function is the inverse of the exclusive __________ gatea. ORb. NOTc. NANDd. EX OR
78) The XOR or Mod-2 addition operation is defined by the equation is_________.a. A B A’B AB’b. A B AB AB’c. A B AB’ AB’d. A B A’B’ AB’
79) The NOR Gate output for input values 1 and 0 is _______.a. 0b. 1c. Ad. A’
80) Exclusive NOR is defined as __________.a. NOTb. ANDc. ORd. NAND
UNIT 381) In a digital system, there are two voltage levels of electrical signals i.e., __________ and ___________
a. 0v and 5vb. 1v and 6vc. 3v and 8vd. 4v and 9v
82) An algebra developed in the nineteenth century by ________________ a. George Booleb. Bill Gatesc. Denis Ritched.
LOGIC DESIGN MCQ [Publish Date]
83) ______________ is a variable which can have either 0 or 1 as its valuea. Boolean variableb. Float Variablec. Double Variabled. Integer Variable
84) A _______________is an expression using Boolean variables {X1, X2,….Xn} and the operations of a Boolean algebraa. Boolean expressionb. Logical Expressionc. Dynamic Expressiond. Binary Expression
85) A Boolean product m1, m2, m3…mn is said to be a ___________a. Mintermb. Maxtermc. MediumTermd. LongTerm
86) One way to determine the smaller set is by using _________ lawa. DeMorgan’sb. Idempotentc. Dominanced. Involution
87) f = x'y'z' + x'y'z + x'yz' + x'yz + xyz' + xyz What is the Output a. x' + yb. x' + y’c. x'+ yd. x + y’
88) If x and y is 0 and 1, the Boolean function xy+xy’ result is ____.a. 0b. 1c. Ad. A’
89) ________________a telecommunication engineer has invented Karnaugh Maps.a. Maurice Karnaughb. George Boolec. Bill Gatesd. Denis Ritchee.
90) In ___________ the Karnaugh map has been developed in Bell Labs while studyinga. 1953 b. 1957
LOGIC DESIGN MCQ [Publish Date]
c. 1856d. 1756
91) _________________ are generally used in simplification of two, three or four variables Boolean functiona. K-mapsb. Gatesc. Flip – Flopd. Counter
92) The simple functions in Boolean function are known as _________________a. product functionb. Functionc. Variabled. Data
93) An ______________ of a function is a product term that is included in the function…a. Implicantb. Explicantc. Extrad. Inter
94) A ___________of a function is an implicant of the function that is not included in any other implicant of the functiona. prime implicantb. Implicantc. Explecantd. Non Implement
95) Implicants that cover as many cells of the map as possible are called __________.a. Prime implicantsb. Implicantc. Explecantd. Private
96) A Karnaugh map is a _______ representation of the truth table for a Boolean Functiona. 2-dimensionalb. 1-dimensionalc. 3-dimensionald. 4-dimensional
97) Match The Following
X Y Z MinTerm1)0 0 0 a) a'b'c'2)0 0 1 b) a'b'c3) 0 1 0 c) a'bc'
a. 1-> a 2 -> b 3 -> cb. 1-> c 2 -> b 3 -> a
LOGIC DESIGN MCQ [Publish Date]
c. 1-> a 2 -> c 3 -> bd. 1-> c 2 -> b 3 -> a
98) Match The Following
X Y Z MaxTerm1)0 0 0 a) a+b+c2)0 0 1 b) a+b+c'3) 0 1 0 c) a+b'+c
a. 1-> a 2 -> b 3 -> cb. 1-> c 2 -> b 3 -> ac. 1-> a 2 -> c 3 -> bd. 1-> c 2 -> b 3 -> a
99) Find The Following Equeation Output
x y z x^y (x^y)^z0 0 0 0 00 0 1 1 00 1 0 1 10 1 1 1 0
100) We could define a ________ operator "|"a. Nandb. ORc. NOTd. Ex-OR
101) A minterm expansion can be simplified using the identities and laws of Boolean algebraa. TRUEb. FALSE
102) K-maps get cumbersome and other techniques like _____________ Method is useda. Tabular Methodb. Simple Methodc. Mathematic Methodd. Logical Method
103) The Boolean expressions will not be equivalent to the _____________ product functiona. k-mapsb. Gatesc. Counter
LOGIC DESIGN MCQ [Publish Date]
d. Flip Flop104) _____________is represented by one product block and the other product represents y.
a. x’b. xc. 0d. 1
105) A horizontal _____________ can be done for 3-variable map, horizontala. ‘wrap around’b. Aroundc. Simpled. Long
106) The ___________ groups are used to obtain the simplest forma. largest sizeb. Small Sizec. Medium Sized. Short Size
107) LSI Stands For_________ a. Large Scale Integrationb. Large Scan Integrationc. Large State Integrationd. Large Scale Inititu
108) ELSI Stands For_________ a. Extra-large scale integratedb. Extra-large scale integratedc. Extra scale integratedd. Extra-loaded scale integrated
109) VLSI Stands For_________ a. Very Large Scale Integrationb. Very Load Scale Integrationc. Very Large State Integrationd. Very Large Stand Integration
111) Minimal cost- it may be cheaper to use certain components as opposed to othersa. True
LOGIC DESIGN MCQ [Publish Date]
b. False112) Minimised number of gates - one interpretation of the ___________ solution,
a. 'simplest'b. Largetsc. Shortd. Long
113) Minimised number of _______________ interconnections, which are a source of unreliabilitya. chip-to-chipb. Register To Registerc. Memory To Memoryd. Counter To Counter
114) Minimal propagation delay- in cases where the very fastest __________ operation is requireda. Circuitb. Registerc. Counterd. Ram
Unit- 4115) _________ operations is known as combinational circuits
a. Booleanb. Gatesc. Counterd. Register
116) Combinational circuits are used to construct the computer’s _________a. CPUb. Ramc. HDDd. Register
117) A _______________ can be implemented by using above Boolean functionsa. half-adderb. Full Adderc. Adderd. 3’addre
a. A (XOR) B (XOR) Cb. A (XOR) B (NOR) Cc. A (OR) B (XOR) Cd. A (OR) B (XNOR) C
119) ______________to Seven segment decoder is the combination circuit which is used very commonlya. BCDb. Binary
LOGIC DESIGN MCQ [Publish Date]
c. Decimald. Hexa
120) Counting as we have been taught since kindergarten is based on the _____________ number systema. Decimalb. Binaryc. Octald. Hexa
Unit-4121) This Combinational Gates Are Represented In _____________
Adder
a. Half Adderb. Full Adderc. Adderd. Multiplexer
122) A __________ adder circuit adds the carry in C along with the two inputs A and Ba. Fullb. Halfc. Adderd. All the Above
123) ___________gate there is only one discrepancy when inputs are, therefore without changing the resulting logica. XORb. NANDc. ANDd. OR
124) The approach used for designing an adder can be used to design a ____________a. substractorb. Adderc. Full Adderd. Half Adder
125) Comparators can be used in a _________________
LOGIC DESIGN MCQ [Publish Date]
a. CPUb. RAMc. REGISTERd. COUNTER
126) A __________________ is a digital device which decodes the original information from the encoded inputsa. Decoderb. Encoderc. Multiplexerd. De-Multiplexer
127) A digital comparator is a hardware electronic device that compares two numbers in _______form and generatesa. Binaryb. Decimalc. Hexad. Octal
128) An _____________is a device used to change a signal (such as a bitstream) or data into a codea. Encoderb. Decoderc. Multiplexerd. Mux
129) A ______________ encoder is such that if two or more inputs are given at the same timea. Priorityb. Assignc. Decoded. Encode
130) Priority encoders can be easily connected in arrays to make _______________ encodersa. Largerb. Smallc. Mediumd. Short
131) In electronics, multiplexing of many signals is performed by the device known as ________a. Multiplexer b. Demultiplexerc. Adderd. Half Adder
132) Many ___________ And ___________signals can be given as input signals for the multiplexera. analog And digitalb. Degital or digitalc. analog or Anlogd. analog or decode
133) A multiplexer is a switch that has multiple inputs and ______________ output
LOGIC DESIGN MCQ [Publish Date]
a. Singleb. Multiplec. A and Bd. Not An above
134) In _____________ circuit design, the values given for the selection line will be either zero or one.a. Digitalb. Logicalc. Analogd. Decode
135) In larger _______________ , using n selection pins 2n input signals can be multiplexeda. Multiplexersb. Demultiplexerc. Adderd. Half Adder
136) In electronics, a _____________ is a device which separates the input signal to multiple output signalsa. Demultiplexerb. Multiplexerc. Curcuitd. Logic
137) At the receiving end demultiplexer can be used as a complementary to the multiplexera. Trueb. Flase
138) A _______________ is a function G(i) of the integers i, that for each integer N ≥0is one-to-onea. Gray codeb. Binary Codec. Hexa Coded. Decimal Code
139) ________________code is most commonly used technique in constructing digital systemsa. Grayb. Binary Codec. Hexa Coded. Decimal Code
140) The __________________ of i with i=2 performed to generate the Gray codea. Bitwise exclusive or (XOR)b. Exclusive or (OR)c. Nord. NOT
141) The Gray codes are named after Frank Gray who patented the idea of using Gray codes in shaft encodersa. Trueb. False
LOGIC DESIGN MCQ [Publish Date]
142) An algorithm or a circuit which translates back the __________________ to integer is requireda. Gray codeb. Binary Codec. Hexa Coded. Decimal Code
143) In digital system, decimal numbers are encoded to binary sequence using ______________techniquea. binary coded decimal b. Binaryc. Hexad. Decimal
144) The advantage of the BCD encoding is that the conversion of ______________ sequence to decimal digitsa. Binaryb. Decimalc. Hexad. Logical
145) The drawbacks of the BCD encoding are the complexity of the ________circuits which are used to implement the a. Digitalb. Logicalc. Analogd. Degit
146) Thus, the BCD encoding for the number 256 would bea. 0010 0101 0110b. 0010 0101 0111c. 0010 0101 1111d. 0010 1111 0110
147) By mapping each __________ to a different charactera. Nibbleb. Bytesc. Bitsd. Broad
148) Than binary encoded numbers ___________ encoded numbers can be easily displayeda. BCDb. Binaryc. Degitald. Logital
149) Generally, integer ___________ And _____________ operation are involved in conversion of binarya. Multiplication And Divisionb. Multiplication or Additionc. Multiplication or Subtractiond. Multiplication or Addition
LOGIC DESIGN MCQ [Publish Date]
150) In packed BCD encoding two digits are placed in a ______________ bytea. Singleb. Multiplec. Longd. Binary
151) Packed ______________ encoding is also known as simply packed decimala. BCDb. Binaryc. Digitald. Logical
152) An ______________ system uses Zoned decimal to representing numeric digitsa. IBM mainframeb. Microsoftc. Iballd. BCD
153) In this encoding, the digit is stored in lower four __________________ of the byte.a. Bitsb. Bytesc. Logicald. Degital
154) ________________ systems use a zone value of 1111 (hex F); this yields bytes in the range F0 to F9a. EBCDICb. ASCIIc. EBCDICd. Binary
155) The ____________________ bits are called the zone bitsa. Upperb. Lowerc. Midiumd. Extent
156) The EBCDIC codes for the characters ____________ through ____________a. 0 to 9b. 0 16c. 0 to 2d. 0 to 8
157) _____________ systems use a zone value of 0011 (hex 3), giving character codes 30 to 39 (hex).a. ASCIIb. EBCDICc. EBDCd. ADC
LOGIC DESIGN MCQ [Publish Date]
158) The current IBM databases and processors still use ___________________ dataa. BCDb. Binaryc. Decimald. Hexa
159) ___________ is done by adding the nines' complement plus 1a. Subtractionb. Adderc. Half Adderd. Full Adder
160) It is a way to represent values with a balanced number of ________ And ____________ numbersa. positive and negativeb. Adder and Subtractionc. Substraction and negatived. Degital And Logical
161) The ________________ binary number represents the smallest valuea. Smallestb. Longestc. Degitald. Logical
162) The logic design using traditional methods have been superseded largely by the _________ and _______circuitsa. MSI and LSIb. VLSI AND LSIc. ELSI AND LSId. LSI AND LSI
163) Then the Boolean function is implemented in ________________ circuits after minimizing ita. SSIb. LSIc. VLSId. ELSI
164) Adding sufficient pins on an _______________package to access each gate in a chip is not economical.a. ICb. Registerc. Memoryd. RAM
Unit -5165) William Eccles and F.W.Jordan invented the first flip flop
a. Trueb. False
166) A powerful model is required to build a complex ___________ system
LOGIC DESIGN MCQ [Publish Date]
a. Digitalb. Analogc. Decoded. Encode
167) combinational circuits such as universal gates and memory such as __________________and flip flopsa. latchesb. Flip Flopc. Registerd. Counter
168) Both the inputs to an NOR gate are low, the output will be_____________.a. Highb. Lowc. Midiumd. Largest
169) Where S stands for set and R stands for reseta. Trueb. False
170) As the circuit has ________________stable statesa. Twob. Onec. Multipled. Single
171) Causing of wrong output because of the timing dependencies is known as __________a. Hazardb. Latchc. Multiplexerd. Gates
172) One way to do that is to interpose AND gates between the S and R inputs and the ___________ circuit.a. Latchb. Hazardsc. Gatesd. Multiplexer
173) The idea of clocking is applied to S-R latch, the problem of what should happen when __________a. S=R=1b. S=r+1c. S=r-1d. S=r *1
174) The concept of a D latch, where the bit to be stored is applied to the S input of a latcha. Trueb. Fale
LOGIC DESIGN MCQ [Publish Date]
175) The two basic flip flops in __________devices make the circuit insensitivea. Master Slaveb. Z K c. S Rd. Letch
176) This circuit might have asynchronous __________ Or ___________which changesa. Reset or Setb. Set And Resetc. A And Bd. Not In ABove
177) The circuit which is capable of remembering the applied input is called a __________a. flip flop.b. Gatesc. Cercuitd. Multiplexer
178) Two __________ And __________ gates can be used to construct a flip flopa. NOR And NANDb. Nand And Norc. Or And Nord. Not and Nand
179) The functionality of the flip flop can be explained using cross coupled two NOR gates or NAND gates.a. Trueb. False
180) The current state of the output is determined by the feeding back the ___________ statesa. Previousb. Nextc. Middled. Last
181) This kind of outputs is inconsistent logically and also the circuit will be in ________ statea. Unstableb. Stablec. Fixedd. Unfix
182) The circuit which stores a single bit is described by a keyword ________a. latch.b. Flip Flopc. Decoderd. Mux
183) Usually the master slave devices are implemented using _____________ flip flopsa. Clocked
185) SR latch is the fundamental latch in _________ circuitsa. Digitalb. Logicalc. Dynamicd. Static
186) the JK flip flop circuit symbol, the clock input is given for ______________a. >b. +c. –d. .
187) The symbol of _________ flip flop
a. D Flip Flopb. Z K Flip Flopc. S R Flip Flopd. Master Slave Flip Flop
LOGIC DESIGN MCQ [Publish Date]
188) The ______________ does not have the master slave properties.a. edge-triggeredb. Z K Flip Flopc. D Flip Flopd. Master Slave Flip Flop
189) A synchronous sequential _____________ is made up of flip-flops and combinational gatesa. Circuitb. Registerc. Flip Flopd. Gates
190) By connecting two gated D latches in series a ___________a. Master-Slaveb. Z K Flip Flopc. D Flip Flopd. S R Flip Flop
191) A negative _____________ flip flop can be determined by removing the left most invertera. Edge Triggeredb. Z K Flip Flopc. D Flip Flopd. S R Flip Flop
192) An __________ gate is used to connect the data input to the S input of an S-R latcha. ANDb. NOTc. NANDd. OR
193) As the second flip flop responds for the changes from first flip flop (master) this circuit is called _______a. Master Slaveb. J K Flip Flopc. S R Flip Flopd. Clock Flip Flop
194) The input variables are Q0, Q1, and x; the outputs are the variables J0, K0, J1 and K1a. Trueb. False
195) An important application of flip-flops is in the design digital __________a. Countersb. Registerc. Flip Flopd. Letch
196) The number of _____________is determined from the number of states needed in the circuita. Flip Flops
LOGIC DESIGN MCQ [Publish Date]
b. Gatesc. Counterd. Letch
197) At the same time, the enable to the slave will be changed from low to high and the signala. Trueb. False
198) ____________flip flop responds during the negative edge of the enable input.a. Master Slaveb. Z K c. S Rd. D
199) The value at input X is shifted to the leftmost position in 3 clock cycles.a. Trueb. False
200) This circuit might have asynchronous reset or set which changes the present value of the output irrespective of ___a. clock signalb. Data Signalc. Pulsed. Signal
Unit 6201) Shift registers are typically used as converters between __________ and _____________ devices
a. serial and parallelb. Dynamic And Staticc. Logical And Paralald. Logical And Serial
202) We can think of __________as delay elementsa. shift registersb. Registerc. Counterd. Synchronous Counter
203) The answer was again moved back to one of the shift register, generally known as the _______a. Accumulatorb. Program Counterc. Registerd. MAR
204) SISO stands For__________a. Serial Input Serial Outputb. Serial Input Serial Outc. Serial In Serial Outputd. Serial Inter Serial Output
LOGIC DESIGN MCQ [Publish Date]
205) SIPO Stands For____________a. Serial Input Parallel Outputb. Serial Input Serial Outc. Serial Input Sampl Outputd. Serial Input PArtionall Output
206) PISO Stands For ________________a. Parallel Input Serial Outputb. Parallel Input Serial Putc. Parallel In Serial Outputd. Parallel Internal Serial Output
207) PIPO Stands For ______________a. Parallel Input Parallel Outputb. Parallel Input Parallel Outc. Parallel In Parallel Outputd. Parallel Input Parallel put
208) If we connect inputs and outputs of a _____________shift register, we get so called circular shifta. serial-in serial-outb. Serial Input Parallel Output c. Parallel Input Serial Output d. Parallel Input Parallel Output
209) Let us call this ___________________ linea. Read/Writeb. Write/Write c. Read/Read
210) The __________register is mainly used to shift a given set of bits and present it to the next stage as illustrated belowa. PIPOb. SISOc. SIPOd. SISA
211) Additional control pins may be provided for changing the direction of the ______________a. data shiftb. Register Shiftc. Curcuit Shiftd. Memory Shift
212) The previously loaded data may be ________by one bit position if LD/SH'=0 for the succeeding negative going clock edgesa. shifted rightb. shifted Leftc. shifted Downd. shifted Up
213) We need to shift left, the FFs need to be rewired. Compare to the previous __________
LOGIC DESIGN MCQ [Publish Date]
a. right shifterb. Left shifterc. Down shifterd. Up shifter
214) As long as the same data is present it will be re-loaded on succeeding _____________a. Clocksb. Pulsec. Signald. Register
215) This problem is remedied in the _________ by the addition of another AND gate to the multiplexera. 74ALS299b. 74ALS285c. 74ALS125d. 74ALS741
216) The buffers shown are necessary for real physical ___________a. ICb. Registerc. Counterd. Memory
217) The 74LS395 IC resembles very much like our theoretical ______________registera. PIPO shiftb. SISO shiftc. PISO shiftd. PIIO shift
218) The AND-OR _________________ at the data input to the FF'sa. Multiplexerb. Demultiplexerc. Decoderd. Encoder
219) In this "real part", __________ must be low if the data needs to be available at the actual output pinsa. OCb. ACc. QCd. DC
220) _______ AND _________ have been reverseda. SI And SOb. OI And OD
LOGIC DESIGN MCQ [Publish Date]
c. DI And SId. SI And DI
221) This problem is remedied in the 74ALS299 by the addition of another __________gate to the multiplexera. ANDb. ORc. NANDd. NOT
222) If SH/LD' is changed to SH/LD'=1, the AND gates labeled __________a. loadb. Waitc. Runningd. Executing
223) The next clock CLK will clock the data to _________And ________ And _________a. QA QB QCb. QD QF QCc. QI QB QCd. QF QD QC
224) A data pattern is presented to inputs DA a. DB DC DDb. DB DC DSc. DA DB DDd. DB DF DD
225) The shift register works much like a SISO register and D1 acts like a. ‘Data In’ lineb. ‘Data Out’ linec. ‘Data ’ lined. ‘Data Put’ line
226) The first few cycles, the number of which is equal to number of _____________in the registera. flip-flopsb. Logic Gatesc. Curcuitd. Register
227) Input for shifting can be loaded into the register in ______________a. Parallelb. Serialc. Sequenced. Unsequence
228) To switch between data-input and data-shift mode, we use a signal______________.a. ‘Write/Shift’ b. ‘Read/Shift’
LOGIC DESIGN MCQ [Publish Date]
c. ‘Write/Store (W/S)d. ‘Write/Loaded (W/S)
229) Input for shifting can be loaded into the register in __________and the shifted outputa. Parallelb. Serialc. Sequenced. LOaded
230) ____________leaves on the SO connection, where it could cascade to another shifter SIa. QAb. DAc. IAd. QD
UNIT 7231) This trigger is usually supplied to a counter in the form of a signal called
a. Clockb. Pulsec. Signald. Data
232) _______________ counter these show increase of count valuea. Up countersb. Down Conterc. Ripple Counterd. Decade counters
233) ______________ these show decrease of count valuea. Down countersb. Ripple Counterc. Decade countersd. Up counters
234) ______________counters are realized by connecting output of a SISOa. Ring countersb. Ripple Counterc. Decade countersd. Up counters
235) A ________________counter is constructed using serial-in and serial-out (SISO)a. Johnsonb. Ripplec. Decade d. Up e.
LOGIC DESIGN MCQ [Publish Date]
236) DAC stands For _____________a. digital-to-analog convertersb. digital-to- Digital convertersc. digital-to-Decode convertersd. digital-to-Analogy converters
237) Many user applications require counter outputs in the form of decimal digits in place of ________format.a. Binaryb. Heaxac. Decimald. Octal
238) The counting sequence is known as ____________sequencea. Johnsonsb. Ripplec. Decaded. UP
239) An _________________counter, which counts from 0 to 7a. Octalb. Decimalc. Hexad. Binary
240) A ___________counter can be constructed using a SISO(serial-in serial-out) shift registera. Ringb. Ripplec. Decaded. UP
241) MNC stands for _____________a. Modulo N counterb. Module N counterc. Mod N counterd. Modern N counter
242) The ___________ counter has two external input channels which corresponds to the counta. Modulo Nb. Ripplec. Decaded. UP
243) Output of each stage is fed to the S (set) input of next stage after _________ a. ANDb. ORc. NANDd. NOR
LOGIC DESIGN MCQ [Publish Date]
244) The _________form of flip-flops FF1 through FF4 in response to the clock signala. Waveb. Signalc. Loadedd. Pulse
245) This is a Johnson counter implemented using 5 bit ________ shift registera. SISOb. SISSc. PISOd. SIPO
246) The commercial CMOS integrated circuits that implement this are __________________a. CD 4017 and 4022b. CD 4017 and 4023c. CD 4014 and 4022d. CD 4015 and 4022
247) In a 5 bit Johnson counter only ten out of ____________ states are actually useda. 32b. 45c. 20d. 8
248) Now the question is what if the counter flip-flops show an ___________ statea. Invalidb. Not validc. Correctd. Not correct
249) Once can also assign any _________ state which is out of Johnson sequencea. Illegalb. Legalc. Logicald. Dynamic
250) This is the output of ____________ and ____________gates which in turn take inputs from flip-flopsa. AND And NORb. NAND and NORc. NOT and NORd. NOR and NOR
251) D flip-flops and hence the circuit is ________________a. Synchronous.b. Asynchronous.c. Squencial
LOGIC DESIGN MCQ [Publish Date]
d. Logical252) The __________ input is asynchronous
a. RESETb. SETc. Clockd. Decode
253) All but one flip-flop in a ____________counter will be in the same state which could be either 0 or 1a. Ringb. Ripplec. Decaded. UP
254) The counter itself increases or resets the output value on demanda. Trueb. False
255) To allow ___________implementations based on master-slave flipflopsa. Hardwareb. Softwarec. Logicald. Phycal
256) Each specification describes a bit-slice of the counter and could be implemented by a _________flip-flopa. Master-Slaveb. D c. Z Kd. S R
257) The ____________ counter has two external input channels which corresponds to the counta. Modulo Nb. Ripplec. Decaded. UPe.
258) The signal received on the second input line which correspondsa. Trueb. False
259) with a suitable modification of the feedback it is possible to achieve an odd-numbered cyclea. Trueb. False
260) Possible 4 bit ring counter sequences are ______ ___________ __________ _________a. 0001, 0010, 0100, 1000b. 0001, 0010, 0100, 1111
LOGIC DESIGN MCQ [Publish Date]
c. 0001, 0010, 0100, 1101d. 1001, 0010, 0100, 1000
Unit-8261) The implementation can be done using digital ____________
a. ICb. Registerc. Counterd. Memory
262) The design is generic and can be customized to suit different type of road junctions with minor changesa. Trueb. False
263) The ________ bit counter IC2 is wired in such a way that it works like a ______ bit countera. 4 And 3b. 8 And 16c. 16 And 32d. 32 and 64
264) In applications where __________ switching options are requireda. Multipleb. Singlec. Twod. Ten
265) Depending on the power that is switched, size and ____________ naturea. Physicalb. Logicalc. Dynamicd. Local
266) A switch can be considered to be a __________ which either allows or disallows certain entitya. gateb. Flip Flopc. Registerd. Counter
267) The mechanical or electromechanical part which helps the contacts to physically touch and separate are called _____a. Actuatorsb. Registerc. Counterd. Mux
268) The nomenclatures are normally used in logic and wiring diagramsa. Trueb. False
269) A switch with both types of contacts is called a changeover switch or "make-before-break"
LOGIC DESIGN MCQ [Publish Date]
a. Trueb. False
270) Alternatively, small __________displays may be provided on each of the input units to displaya. LEDb. CRTc. LCD
271) __________scoring equipment keeps track of the points, gamesa. Electronicb. Megnaticc. Logicald. All the Above
272) A jumper on the input of the ___________allows the usea. DS2438b. DS2444c. DS2489d. DS2487
274) A fixed resistor could replace the variable _________a. Resistorb. Counterc. Memoryd. Gatway
275) Another possibility is to use several DS2406 ______________a. 1-wire switchesb. 2-wire switchesc. 3-wire switchesd. 4-wire switches
276) Once its set, put the ______________ in the A-B position to read pressurea. Jumperb. Pinc. Coded. Coax
277) An Excel spreadsheet can be used to calculate intermediate values.a. True
LOGIC DESIGN MCQ [Publish Date]
b. False278) The dart includes a barcode card reader that permits identification of league
a. Trueb. False
279) Inter-game communication within an establishment is provided either by ____________the darta. Hardwiringb. Softwareingc. Technicald. Dynamic
280) The operating range will be from _____________ To ____________a. 28.00 inHg to 32.00 inHgb. 28.00 inHg to 52.00 inHgc. 68.00 inHg to 32.00 inHgd. 28.00 inHg to 50.00 inHg
281) Resolution will be greater than .01 inHg from sea level to ________ feeta. 10,000b. 50,000c. 20,000d. 30,000
282) The interface will be standard Dallas ________________ 1-wire.a. Semiconductorb. Flip Flopc. Curcuitd. Register
283) Because the unit will be designed for indoor operation, it can be externally powered.a. Trueb. False
284) This table calculates the station pressure for both the minimum _________ and the maximum ________a. 28.00 and 32.00b. 58.00 and 42.00c. 68.00 and 32.00d. 28.00 and 52.00
285) The station pressure is then converted to ___________ pressure sensor voltsa. MPX4115Ab. MPX4116Ac. MPX4117Ad. MPX4118A
286) The gain of 30 was chosen to allow maximum output voltage swing for all altitudesa. Trueb. False
LOGIC DESIGN MCQ [Publish Date]
287) The resulting op amp output voltages are listed in _________ Output columna. OAb. QAc. DAd. TA
288) The __________ ohm resistor sets the gain to 10a. 40.2Kb. 44.2Kc. 46.2Kd. 47.2K
289) The variable resistor allows adjustment of the offset voltage from ____________ to _________a. 2.0v to 4.0v.b. 2.0v to 6.0v.c. 2.0v to 9.0v.d. 2.0v to 7.0v.
290) The user to edit the file to fine-tune the calibration if desireda. Trueb. False
Unit -9291) In __________ George Stibitz connected a New Hampshire teletype to a computer system in New York
a. 1940b. 1947c. 1856d. 1999
292) ________ maintained a monopoly in the US for many years by lettinga. AT&Tb. IBMc. Microsoftd. Linux
294) Call originators transmitting at _________ or _________a. 1070 or 1270 Hzb. 1070 or 1289 Hzc. 1076 or 1270 Hzd. 1085 or 1270 Hz
295) DVD stands for_____________________________
LOGIC DESIGN MCQ [Publish Date]
a. Digital Versatile Discb. Digital Ventiled Discc. Digital Venod Discd. Digital Ver Disc
296) Most _____________s are of the same dimensions as compact discsa. DVDb. CDc. LCDd. DSD
297) Modem which stands for ________________a. Modulator-Demodulatorb. Modulator-Decodec. Modulator-demodd. modulator-demod
298) POTS Stands For___________a. Plain Old Telephone Systemsb. Plain Old Telephone Synchronisec. Plain Old Telephone Slotd. Plain Over Telephone Systems
299) A modem that switches it state _________ times/seca. 600b. 500c. 100d. 200
300) Each baud if it transmits 4 bits, it is said to be a _____ bit/sec modema. 2400b. 4500c. 6400d. 2890
301) Cable modems and _____________modems are some faster modems used by internet users dailya. ADSLb. DSLc. BroadBandd. Logical
302) ___________modems use optical fibers to transmit dataa. Opticalb. Logicalc. Dynamicd. Static
303) Smartmodem introduced by Hayes Communications in ___________
LOGIC DESIGN MCQ [Publish Date]
a. 1981b. 1970c. 1990d. 1451
304) Using Smartmodem, computer can directly dial the phone using corresponding commandsa. Trueb. False
305) BBS stands For_________a. Bulletin board systems b. Bulletin broadband systems c. Bulletin boarding systems (BBSs)d. Broadcase board systems (BBSs)
306) GeoPort modem released by ___________was similar onea. Appleb. Samsungc. Nokiad. Karbon
307) Computer can convert an image into _________format which is then sent through modema. Faxb. Datac. Imaged. Signal
308) Modems that are used currently are composed of an _________ part and a digital parta. Analogb. Degitalc. Signald. Pulse
309) Only for the operations which work at ___________ bpsa. 300b. 500c. 600d. 700
310) In ________ to send the data using 300bps modemsa. Orderb. Out Of Boundc. In Orderd. Un Order
311) In Bell 103 system, __________ and _________ Hz tones are played to senda. 1070 Hz and 1270b. 1170 Hz and 1270
LOGIC DESIGN MCQ [Publish Date]
c. 1270 Hz and 1270d. 1370 Hz and 1270
312) ______________is used in the systems whose speed is equal to or more than 1200bpsa. Phase shift keyingb. TSMc. TTMd. TTL
313) In _________ Gottfried Ungerboeck from IBM Zurich Research Laboratory applieda. 1980b. 1989c. 1990d. 1998
314) An _________modem manufactured to conform to the V.34 protocola. ISAb. VISAc. EISAd. ISP
315) V.34 modems once the standard was ratified __________a. 1994b. 1999c. 1956d. 1999
316) In the late 1990s Rockwell and U.S. Robotics introduced new technologya. Trueb. False
317) The standard digital transmission in modern networks is _____________ kbit/sa. 64b. 90c. 60d. 30
318) The digital ______technique was applied to increase the upload speed to a maximum of 48 kbit/sa. PCMb. DCMc. VBMd. DRF
319) ISP Stands For__________________a. Internet Service Providerb. Internal Service Providerc. Increase Service Providerd. Instrument Service Provider
LOGIC DESIGN MCQ [Publish Date]
320) Direct broadcast satellite, WiFi, and mobile phones all use modemsa. Trueb. False
Unit ->10321) ADC Stands for__________
a. analog-to-digitalb. analog-to-digitc. analogical - to-digitald. analog-to-descrive
322) An _________ takes in analog continuous signal that is to be transformeda. ADCb. DACc. ADSd. DRF
323) Reference voltage measurement range = ________ to ________ voltsa. 0 to 7b. 0 to 9c. 0 to 16d. 0 to 26
324) Even though ___________ to ________ conversion process is a non-linear processa. analog-to-digitalb. Degital to Analog
325) the ________ stands for the linear relationshipa. ADCb. DACc. SDFd. DFS
326) PDF stands for _______________a. probability density functionb. probability dens Fundationc. probability density Faberd. prility density function
327) CDF stands For_________________a. cumulative distribution functionb. cumulative distributed functionc. cum distribution functiond. cumve distribution function
328) ____________ implementation imperfections cause all the ADCsa. Physicalb. Logical
LOGIC DESIGN MCQ [Publish Date]
c. Dynamicd. Static
329) ___________ conversion has to convert the flow of continuous analog in time into digital valuesa. ADCb. DACc. DSCd. FDC
330) Sampling input signals at regular intervals of time, is the way ADCs worka. Trueb. False
331) DAC performance are enhanced using dithers as discussed previously i.e.a. Trueb. False
332) LSB Stands for_________a. Least Significant Bitb. Last Sigtnificant Bitc. Lose Significant Bit
333) The errors which are occurred due to physical imperfections are known as __________ errorsa. Nonlinearityb. Linierc. Logicald. System
334) The output of _________ is given as input to DAC.a. Up-downb. Downc. Upd. Ripple
335) Undesired deviation of clock value from the periodic signal is known as ___________.a. Clock jitterb. Clockc. Pulsed. Signal
336) __________combines above techniques in a single implementationa. Hybrid DACsb. Dynamicc. Logicald. Static
337) _______________combines binary weighted principle for the LSBsa. Segmented DACb. Segmented ADC
LOGIC DESIGN MCQ [Publish Date]
c. Segmented DASd. Segmented DFD
338) In order to reproduce signals of frequency ___________kHza. 30b. 40c. 50d. 60
339) ________________ is the simplest type of DACa. Pulse Width Modulatorb. TDMc. TTMd. TTL
340) _____________port came up digital inputs started dominatinga. HDMIb. PSc. COMPORTd. SERIAL
