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Digital Logic Design

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Digital Logic Design. Lecture # 23 University of Tehran. Outline. MSI Parts as a Register Shift Register MSI Parts as a Shift Register. MSI Parts as a Register. We will be discussing the 7400 register series which is a rather popular series of registers. - PowerPoint PPT Presentation
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Digital Logic Design Lecture # 23 University of Tehran
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Page 1: Digital Logic Design

Digital Logic Design

Lecture # 23University of Tehran

Page 2: Digital Logic Design

Outline

MSI Parts as a Register Shift Register MSI Parts as a Shift Register

Page 3: Digital Logic Design

MSI Parts as a Register We will be discussing the 7400 register series

which is a rather popular series of registers. 74ls373: This register is made up of 8 latches

and to have a clock enable the following structure is used:

1D

1D

1D

1D

1D

1D

1D

1D

Ls373

C1

en

1D

C1

D7

Q7…. 1D

C1

D0

Q0

en

z7 z0

Page 4: Digital Logic Design

MSI Parts as a Register (continued…) When the enable signal is high although

clocking is done, the values of the latches won’t appear on the output lines. The following figure shows us how this enable line can be used to select which one of the numerous registers’ value is to be set on the output bus:

1D

AC1

en

88

1D

BC1

en

88

sel A

sel B

bus

System clk

bus

01234567

0 1 2 3 4 5 6 7

Page 5: Digital Logic Design

MSI Parts as a Register (continued…) Quote: Sometimes although a register may be

able to store for instance 32 bits, only 16 communication lines are used that will load or send out data in two clock pulses.

Page 6: Digital Logic Design

MSI Parts as a Register (continued…) 74ls377: This register can be used where a bus

is linked to the input of more than one register and we want to be able to choose into which one, data will be loaded. Here we have lost the ability to bus the outputs. In order to be able to bus the outputs we need to use three state packages.

1D88

G1

1C2

Ls377 2D88

G1

1C2

2D88

G1

1C2

load A

load B

Abus

544 8

544 8

Bbus

544 8

8

Page 7: Digital Logic Design

MSI Parts as a Register (continued…) The reason we have either load control on a

register package or three state control and not both at the same time is that packages have a standard number of pins and thus both can’t be on the package at the same time.

Using outer three state packages or AND-OR structures for bussing wastes a lot of space, thus using the components with three state outputs are preferable, except when we want to use a component on two busses we will have to use some form of extra hardware.

Page 8: Digital Logic Design

MSI Parts as a Register (continued…) 74ls374: This package is very similar to that of

the 74ls373. The only particular difference is that here we are allowed to feeding of outputs through combinational logic back into the register and this is because we have flip flops instead of latches in the 74ls373:

1D

1D

1D

1D

1D

1D

1D

1D

Ls374

C1

en

Page 9: Digital Logic Design

MSI Parts as a Register (continued…) Consider the following figure. We can add the

contents of CReg and AReg, and put the total in CReg using this circuit and activating the control signals selAReg, add and selCReg. This will be done in two clock pulses and this is why the clock frequency must be carefully decided (according to the longest path delay of the circuit).

1D88

C1

ensel AReg

AReg

1D88

C1

ensel BReg

BReg

1D88

C1

ensel CReg

CReg

88

8

8

inputbus

addsuband

Page 10: Digital Logic Design

MSI Parts as a Register (continued…) The following structure shows how the clock

enable of the registers actually works:

As we mentioned before, gating must not be done on the clock, because it can easily give this input hazards that we don’t want.

1

0

input

C22D

en

Q

Page 11: Digital Logic Design

MSI Parts as a Register (continued…) In system designs, such as the latter example,

all control signals last from one rising edge to the next one. Remember that the clock frequency is determined by the longest common path.

Page 12: Digital Logic Design

Shift Register Let’s observe the values of the flip flops in this

shift register for the next couple of clock pulse:

1 0 0 1 1

1 100

1

1 100

0 0

Page 13: Digital Logic Design

Shift Register (continued…) We are actually shifting our data to the right

on every clock pulse. Shift registers are widely used in parallel to

serial converters which find applications in computer communications.

Page 14: Digital Logic Design

MSI Parts as a Shift Register 74ls164: This package has two inputs and

eight outputs. It can be useful in serial to parallel conversion of data but not parallel to serial because there is no parallel loading.

1D

74Ls164

C1

R

&

Page 15: Digital Logic Design

MSI Parts as a Shift Register (continued…) We now want to see how universal shift

registers are made. Consider the following circuit:

1 00123

1 00123

Q QQ

m0

m1

Page 16: Digital Logic Design

MSI Parts as a Shift Register (continued…) In the last diagram, you can see that 4 modes

of operation exist. When m1m0 is 00, nothing happens, that is the contents of the flip flops don’t change due to feed backing. m1m0=01 puts us in right shift mode and 10 in left shift, whereas m1m0=11 gives us parallel load. This structure can be used in a shift register to give us parallel to serial conversion abilities.

Page 17: Digital Logic Design

MSI Parts as a Shift Register (continued…) 74ls194: This package give us right and left

shifting as well as parallel load in mode 11.

right

C4/1

R01

/2

3,4D1,4D

3,4D

3,4D

2,4D

3,4D

left

Parallel Load

Ls194

4


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